Changes for GCC 2.2.1, from version 2.1. Changes in TAGS, INSTALL, and *.info* have been omitted; you can update these files using make. Likewise cexp.c and *-parse.c. Before installing the diffs below, execute the following commands: mv config/xm-sparcv4.h config/xm-spcv4.h mv config/xm-i386sun.h config/xm-sun386.h mv config/xm-hp800.h config/xm-pa.h mv config/hp800.c config/pa.c mv config/hp800.h config/pa.h mv config/hp800.md config/pa.md rm Makefile.dos mv README-ALTOS README.ALTOS mv README-ENCAP README.ENCAP mv README-mips README.MIPS mv README.trad README.TRAD rm README-TOWER README.CRDS README-bugs mv config/mips-news5.h config/mips-n5.h mv config/mips-gnews5.h config/mips-gn5.h rm config/t-convex config/t-rs6000 rm config/x-hp800hpux config/hp800hpux.h rm config/x-m88k rm print-self*.c diff -rc2N gcc-2.1/.gdbinit gcc-2.2.1/.gdbinit *** gcc-2.1/.gdbinit Sat Oct 12 15:54:08 1991 --- gcc-2.2.1/.gdbinit Fri Mar 27 18:39:11 1992 *************** *** 63,67 **** --- 63,80 ---- end + define pbs + set print_binding_stack () + end + + document pbs + In cc1plus, print the current binding stack, frame by frame, up to and + including the global binding level. + end + # Don't let abort actually run, as it will make # stdio stop working and therefore the `pr' command below as well. b abort + + # Make gdb complain about symbol reading errors. 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Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the + library `Frob' (a library for tweaking knobs) written by James Random Hacker. + + , 1 April 1990 + Ty Coon, President of Vice + + That's all there is to it! diff -rc2N gcc-2.1/ChangeLog gcc-2.2.1/ChangeLog *** gcc-2.1/ChangeLog Tue Mar 24 22:26:47 1992 --- gcc-2.2.1/ChangeLog Tue Jun 9 23:11:22 1992 *************** *** 1,2 **** --- 1,3989 ---- + Tue Jun 9 20:52:05 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * Version 2.2.1 released. + + * Makefile.in (clean): Don't delete unprotoize.c. + + * configure: Fix typo in modifying INSTALL variable in Makefile. + + Mon Jun 8 15:14:09 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * Version 2.2 released. + + * Makefile.in (extraclean): Delete *.rej and *.orig under config. + Delete *.xtar. + (dist): Update README *before* making tar file. + Fix quoting of error message about gcc.texi; exit if that test fails. + Don't print error messages from ln. + + * assert.h [__cplusplus]: Use `extern "C"' around __eprintf decl. + + * configure (rs6000-*-mach*, pyramid-*-*, mips-sgi-*): + Patterns made canonical. + (rs6000-*-mach*): Fix typo in `xmake_file'. + + * configure (i386-*-osfrose*): Renamed from i386-osfrose*. + + * Makefile.in (.NOEXPORT): Moved after `all'. + Comments put on separate lines. + + Mon Jun 8 18:33:01 1992 Michael Meissner (meissner@osf.org) + + * configure (mips-dec-osf*): Set xmake_file to x-mips. + + Sun Jun 7 15:55:34 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * gcc.c (set_spec): Fix braino in "appending" spec values. + + * integrate.c (expand_inline_function): Fix dumb bug in last change. + + Sun Jun 7 07:16:25 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * romp.md: Disable two more define_splits during the first sched + pass until long-standing sched.c bug is fixed. + + Thu Jun 4 16:49:56 1992 Jim Wilson (wilson@sphagnum.cygnus.com) + + * reorg.c (dbr_schedule): Global registers are needed at function end. + + Sat Jun 6 17:07:16 1992 Torbjorn Granlund (tege at david.ultra.nyu.edu) + + * pyr.md (shift patterns): Declare output_shift. + (movdi, movdf): Declare output_move_double. + + Sat Jun 6 15:07:11 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * Makefile.in (c-parse.o): Depend on c-parse.h. + + * reload.c (find_reloads): Fix typo in format string. + + * mips.c (override_options): BSD 4.3 does line buffering differently. + + * Makefile.in (SYSCALLS.c.X): Put GCC output in file, not /dev/null. + (mostlyclean): Delete temp file. + + * configure (handling broken_install): Add -c option. + + Sat Jun 6 11:34:00 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * gstdarg.h (va_arg): Fix typo incrementing AP. + + Sat Jun 6 16:27:18 1992 Michael Meissner (meissner@osf.org) + + * mips-n5.h, mips-sysv.h: Include sys/param.h, not types.h. + + Fri Jun 5 19:00:36 1992 Howard Chu (hyc@hanauma.jpl.nasa.gov) + + * fx2800.h (ASM_OUTPUT_FUNCTION_PREFIX): Output a nop before + every function, to accomodate tdescs. Also, save function + name in current_function_original_name for use in i860.c. + Also define OUTPUT_TDESC to get ABI-compliant tdesc info + generated for each function. + + * i860.c (function_epilogue): Add code to output tdesc info + after each function. Tdesc structure versions 1-4 are + supported. + + * i860v4.h (ASM_FILE_END) [OUTPUT_TDESC]: Output a null tdesc entry + after the last function in a file. + + Fri Jun 5 19:03:22 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * collect2.c (main, scan_prog_file): Use bcopy, not memcpy. + + Fri Jun 5 16:27:18 1992 Michael Meissner (meissner@osf.org) + + * mips.h, mips.c, mips.md: Undo June 3 changes. + + * mips-n5.h, mips-sysv.h (getpagesize): If _SC_PAGE_SIZE is undefined, + use NBPC defined in sys/types.h. + + Thu Jun 4 14:36:43 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * cse.c (delete_dead_from_cse): Don't delete anything inside a libcall. + + * Makefile.in (install-libgcc): Depend on install-dir. + + * c-lex.c (yylex): Suppress int out of range warning if -traditional. + + Thu Jun 4 23:34:05 1992 Howard Chu (hyc@hanauma.jpl.nasa.gov) + + * fx2800.h (DBX_OUTPUT_ENUM): Add missing argument, add a + missing semi-colon. + (ASM_OUTPUT_DOUBLE): undef definition from i860v4.h, replace + with definition used in i860.h. + (ASM_OUTPUT_FLOAT): same as above + Also undef MD_EXEC_PREFIX which is defined in i860v4.h. + Also define I860_STRICT_ABI_PROLOGUES for ABI-compliant function + prologues. + + Thu Jun 4 13:15:30 1992 Jim Wilson (wilson@sphagnum.cygnus.com) + + * enquire.c (fake_f_rep): Use __extension__ to avoid pedantic warnings. + + * cse.c (cse_process_notes): Don't stick VOIDmode into *_extract. + + * c-decl.c (get_parm_info): For forward parm decls, check for + non-parm before checking TREE_ASM_WRITTEN. + + Thu Jun 4 13:57:47 1992 Tim Moore (moore at defmacro.cs.utah.edu) + + * pa.h (reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS): Delete + FP_OR_SNAKE_FP_REGS (useless), add GENERAL_OR_FP_REGS, + GENERAL_OR_SNAKE_FP_REGS. + (ASM_DECLARE_FUNCTION_NAME): Handle DImode arguments correctly. + (PROFILE_BEFORE_PROLOGUE, FUNCTION_PROFILER): Do the same thing + for BSD and HPUX. + + * pa.c (output_function_prologue): Do profiling right (compatible + with HPUX). + (output_arg_descriptor): Handle DImode argument registers. + + Thu Jun 4 13:48:24 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * reload1.c (reload): Count reload register used by caller-save + handling in any basic block that contains a CALL_INSN. + + Thu Jun 4 09:23:19 1992 Ron Guilmette (rfg at ncd.com) + + * i860v4.h (ASM_OUTPUT_DOUBLE, ASM_OUTPUT_FLOAT): Remove leading 0r. + (ASM_OUTPUT_FLOAT): Use .float (not .single). + + Fri Jun 5 14:58:43 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * pyr.h (REGNO_OK_FOR_{INDEX,BASE}): Correctly test reg_renumber. + * configure (pyramid): Turn it back on. + + Thu Jun 4 11:26:55 1992 Torbjorn Granlund (tege@mole.gnu.ai.mit.edu) + + * pa.c (output_move_double): Handle overlapping moves between + registers. + + Wed Jun 3 22:08:18 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * fold-const.c (fold, NOP_EXPR case): Don't drop intermediate in + (unsigned int) (unsigned short) char-variable. + + Wed Jun 3 11:18:43 1992 Ron Guilmette (rfg at ncd.com) + + * stdarg.h (va_arg): Use casts to avoid doing (pedantically invalid) + arithmetic on `void *' values when __svr4__ is defined. + + Wed Jun 3 17:51:21 1992 Torbjorn Granlund (tege@zevs.sics.se) + + * longlong.h (sparc): Test symbol __sparcv8__ for sparc.h conformance. + + Wed Jun 3 16:22:38 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * sparc.c (print_operand): Correct typo. + (sparc_type_code): Correctly handle C int and float types. + + * sparc.h (CONSTANT_ALIGNMENT): Align strings to 8 byte boundary. + (DATA_ALIGNMENT): Likewise for character arrays. + + * i960.c (function_prologue): Fixed calculation of offsets for + compiler's register save area. + + * sparc.md (mulsi3,mulsidi3,umulsidi3,divsi3,udivsi3): Patterns + added to support V8 sparc architectures. + * sparc.h (TARGET_DEFAULTS): Add -mv8 and -msparclite options. + + * reload1.c (reload): If can't satisfy reload for a group of more + than two registers, then abort to avoid an infinite loop. + (count_possible_groups): Skip to last reg of group, not first reg + of next group. + + Wed Jun 3 14:35:00 1992 Tom Wood (wood at gen-rtx) + + * c-lex.c (yylex): Let skip_white_space handle \r. + + * expr.c (expand_builtin, fsqrt case): Stabilize the argument in + case a library call is done. + + * final.c (final_scan_insn): Function begin, and block begin/end + notes are "real" in that they depend on the current line number. + + Wed Jun 3 14:34:28 1992 Michael Meissner (meissner@osf.org) + + * mips.md (andsi3_internal2): Fix typo in previous change, to + use %3, the clobbered register, instead of %@, the assembler + temporary. + (iorsi3_internal2): Ditto. + (xorsi3_internal2): Ditto. + + * mips.h (MIPS_VERSION): Bump Meissner version # to 20. + (final_prescan_insn): Add declaration. + (lui_int): Add declaration. + (FINAL_PRESCAN_INSN): Just call final_prescan_insn. + + * mips.c (lui_int): New function, return true if value fits in a + LUI instruction. + (final_prescan_insn): Move the checking for filling the delay + slots here from the FINAL_PRESCAN_INSN macro. If the safe + attribute is set, we do not need a NOP to fill a load delay slot. + + * mips.md (safe attribute): New attribute to indicate that the + current insn is safe to fill a delay slot even if the register + operand(s) are set in the load instruction which has the delay + slot. This is for and/ior/xor expansions that have a large + constant integer as operand[2]. The load of the constant can + overlap the load. + (andsi3, iorsi3, xorsi3): Replace logical define_insn's with + define_expand's that either map directly to the hardware + instruction, or have a clobbered register to load the large + constant into. This is instead of using $1 to hold the + intermeidate value. Set the safe attribute to yes for the cases + where we need to load the integer. Add define_split's to break + the large logical operations into the separate pieces. + + Wed Jun 3 00:00:36 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * cccp.c (do_warning): Do just a warning, not an error. + + Tue Jun 2 17:30:09 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * cse.c (cse_basic_block): When a jump becomes unconditional, + check whether this caused TO to be deleted. + + Tue Jun 2 16:11:42 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * combine.c (subst, case IF_THEN_ELSE): Don't try reversing + something that isn't a comparison. + + Tue Jun 2 16:50:47 1992 Jim Wilson (wilson@sphagnum.cygnus.com) + + * cccp.c (do_pragma): Don't warn about #pragma once if used in a + system header file. + + Tue Jun 2 15:21:07 1992 Michael Meissner (meissner@osf.org) + + * mips.h (MIPS_VERSION): Bump Meissner version # to 19. + (ASM_OUTPUT_DOUBLE): Call mips_output_double. + (ASM_OUTPUT_FLOAT): Call mips_output_float. + + * mips.c (mips_output_double): If REAL_VALUE_TO_TARGET_DOUBLE is + defined, use it to split the floating point value into 2 long + integers, and print them out in hex. Otherwise use .double. + (mips_output_float): If REAL_VALUE_TO_TARGET_FLOAT is defined, use + it to split the floating point value into a long integer, and + print in out in hex. Otherwise use .float. + + * dec-osf1.h (new file): Config file for DEC's offical OSF/1 + product (as opposed to the OSF/1 reference port from OSF). + + * configure: Support mips-dec-osf1 target. + * config.sub: Support mips-dec-osf1 target. + + * decstatn.h (CPP_PREDEFINES): If CPP_PREDEFINES is defined, don't + supply another definition. Also, define _SYSTYPE_BSD. + + Mon Jun 1 00:04:01 1992 Ron Guilmette (rfg at ncd.com) + + * gstdarg.h (va_list) [__svr4__]: Typedef it to `void *'. + * va-sparc.h (__va___list) [__svr4__]: Typedef this as `void *'. + + Sun May 31 15:26:32 1992 John F Carr (jfc at Achates.mit.edu) + + * calls.c (stack_arg_under_construction): New variable. + (store_one_arg): Set stack_arg_under_construction before calling + expand_expr if expand_expr might call a constructor to initialize + a stack argument. + (expand_call): Push the stack around function calls if + stack_arg_under_construction is nonzero. + Also copy structure_value_addr in that case. + Push the stack around an inline function if it makes calls + and there are outgoing arguments on the stack which must be preserved. + Move the call to expand_cleanups_to before that. + Do this stack adjustment before computing argument locations. + + Sun May 31 01:03:51 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * sdbout.c (sdbout_symbol): Test DECL_IGNORED_P only for + variables and types. + * dwarfout.c (output_decl): Never ignore a FUNCTION_DECL + even if DECL_IGNORED_P is set. + + Sat May 30 07:07:55 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * rs6000.h, romp.h (FUNCTION_ARG): Fix typo in last change. + + * combine.c (subst, significant_bits, simplify_comparison): + Only look at STORE_FLAG_VALUE if comparison result is integer. + + Fri May 29 18:04:45 1992 Ron Guilmette (rfg at ncd.com) + + * dwarfout.c (output_decl): Moved test for ERROR_MARK node out of + switch statement and added a test for DECL_IGNORED_P after that. + (dwarfout_file_scope_decl): Check input node to see if it is an + ERROR_MARK before checking for DECL_IGNORED_P. Also makes sure that + any node marked as DECL_IGNORED_P isn't also a function definition. + + Fri May 29 14:46:06 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * integrate.c (expand_inline_function): + Don't discard setting return value from a volatile source. + + * c-decl.c (init_decl_processing): If traditional, strlen returns int. + (sizet_ftype_string): Deleted. + + * expr.c (expand_builtin, fsqrt case): Return proper mode if arg error. + + Fri May 29 13:36:32 1992 Tom Wood (wood@dg-rtp.dg.com) + + * m88k.c (m88k_builtin_saveregs): Don't copy result to a register. + + * m88k.h (FIXED_REGISTERS): Allow use of r1. + (REG_LEAF_ALLOC_ORDER): Choose r1 last. + (REG_ALLOC_ORDER): Choose r1 before any preserve register. + (ORDER_REGS_FOR_LOCAL_ALLOC): Switch between orderings. + * m88k.c (m88k_layout_frame): Save r30 when used as an ordinary + register. + + * m88k.h (CHECK_FLOAT_VALUE): Delete, not needed. + * m88k.c (check_float_value): Delete, not needed. + + * m88k.c (mostly_false_jump): Fix return check. + + * m88k.md (mstore type): Delete. + (return, indirect_jump): These are jumps, not branches. + * m88k.c (eligible_for_epilogue_delay): No TYPE_MSTORE insns. + + Fri May 29 12:33:21 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * reload1.c (emit_reload_insns): Add missing arg to gen_input_reload. + + Fri May 29 06:43:15 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * rs6000.h, romp.h (FUNCTION_ARG): Don't put variable-sized + operands in registers. + + * explow.c (emit_stack_{save,restore}): Don't call validize_mem + on a null rtx. + + * cse.c (cse_insn): Don't call canon_reg on entry from + hash table; instead, call it after we did the substitution. + + Thu May 28 18:47:00 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * fixincludes (malloc.h): Allow space or tab btwn typedef and char. + + Thu May 28 17:35:37 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * reload1.c (reload_as_needed): Properly disable optional reload + that we can't do. + Don't abort if disabled reload uses a register we don't have. + + Thu May 28 14:43:01 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * next.c (get_directive_line): Declare it. + + * defaults.h (ASM_OUTPUT_ASCII): Use unsigned chars. + + * i860v4.h, i386v4.h, sparcv4.h (ASM_OUTPUT_FLOAT, ASM_OUTPUT_DOUBLE): + Use the override definitions only if word order matches host. + + Wed May 27 17:32:36 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * unroll.c (find_splittable_givs): When completely unrolling loop, + precompute giv value into a reg before loop if it is complex. + + * sparc.c (singlemove_string): Handle SFmode CONST_DOUBLE. + * sparc.h (PREFERRED_RELOAD_CLASS): Don't allow reloads of + constants to FP registers, nor reloads of FP constants that won't + match the 'E' constraint. + * sparc.md (movsf-1): Add pattern to efficiently handle SFmode + constants. + + * sparc.md (lo_sum:DI pattern): Use constraint "0" for operand 1. + + * i960.h (OVERRIDE_OPTIONS): Disable function inlining. + + * function.c (assign_parms): When MAYBE_REG_PARM_STACK_SPACE, + don't assume that register parameters already have a stack slot. + * i960 (*): Change all tests of current_functions_args_size from + 48 to 0 due to above change. + * i960.md (*): Likewise. + + * sparc.h (LONG_DOUBLE_TYPE_SIZE): Add ifdefed out definition. + (FIXED_REGISTERS): g4 is not a fixed register. + (RETURN_IN_MEMORY): Define. + (FUNCTION_ARG_PASS_BY_REFERENCE): Also pass TFmode by reference. + + * fixincludes: Fix stdio.h and math.h for Ultrix 4.0. + + Tue May 26 15:29:21 1992 Brendan Kehoe (brendan@cs.widener.edu) + + * x-we32k: new file, need alloca.o + * xm-we32k.h [NO_SYS_SIGLIST]: define this + * we32k.h [STRICT_ALIGNMENT] define as `1' + [NO_WAIT_H]: also define this + * collect2.c [NO_WAIT_H]: don't include sys/wait.h if this is + defined. + + * Makefile.in (clean): rm libgcc1.null. + + Wed May 27 15:36:51 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * real.h (REAL_VALUE_TO_TARGET_SINGLE): Test HOST_BITS_PER_WORD right. + + * i386sco.h (SIZE_TYPE): New definition. + + * c-typeck.c (build_binary_op): When shortening, handle case + where op0 and arg0 are different but have same width. op1/arg1 too. + + * toplev.c (compile_file): Cast xmalloc when arg to setvbuf. + + * expmed.c (expand_divmod): Clear can_clobber_op0 if doing mod. + + * Makefile.in (protoize.1, unprotoize.1): Delete target before mv'ing. + (mostlyclean): Delete tmp-unproto.1. + + * sdbout.c (sdbout_symbol, sdbout_toplevel_data): Test DECL_IGNORED_P. + * dwarfout.c (dwarfout_file_scope_decl): Likewise. + + Wed May 27 13:48:36 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * i386.md (ashldi3,ashrdi3,lshrdi3): Fix typo in comparison. + + Wed May 27 02:11:22 1992 Ron Guilmette (rfg at ncd.com) + + * i386v4.h, i860v4.h, sparcv4.h: Include real.h. + (ASM_OUTPUT_FLOAT, ASM_OUTPUT_DOUBLE): + New definitions, if host and target formats match. + + * real.h (REAL_VALUE_TO_TARGET_SINGLE, REAL_VALUE_TO_TARGET_DOUBLE): + Defined, but only if host and target formats match. + + Wed May 27 06:20:26 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * reload1.c (reload_as_needed): For asm insn, check all reload + insns for validity. + (emit_reload_insns, gen_input_reload): Remove previous change that + checked them here. + * recog.c (constrain_operands, case 'm', 'o', 'g'): Accept pseudo if + reload is in progress. + + Tue May 26 19:24:21 1992 Richard Kenner (kenner@vlsi1.ultra.nyu.edu) + + * combine.c (combinable_i3pat): Allow a hard register as the + destination even if SMALL_REGISTER_CLASSES if source is a CALL. + + * emit-rtl.c (gen_lowpart_common): Fix handling of int->float + union conversions. + + Tue May 26 19:23:43 1992 Jim Wilson (wilson@sphagnum.cygnus.com) + + * a29k.h (HARD_REGNO_MODE_OK): Don't let anything larger than + UNITS_PER_WORD be allocated to an odd numbered register. + + Tue May 26 15:22:27 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * config.sub (defaulting the OS): Separate subversions with periods. + + * limits.h: Fix condition for defining long-long macros, to suit libc. + + * Makefile.in (specs): New target. + (gcc): Don't write `specs' here. + (start.encap): Depend on `specs'. + (all.cross): Depend on EXTRA_PARTS. + (rest.cross): New target. + + * c-common.c (declare_function_name): + Set TREE_USED, not TREE_NO_UNUSED_WARNING. + + Tue May 26 04:52:53 1992 Michael Meissner (meissner@osf.org) + + * loop.c (loop_has_volatile): New static variable to record + whether the loop has any volatile references in it. + (prescan_loop): Set loop_has_volatile. + (check_dbra_loop): Don't reverse loop if there are any volatile + references in it. + + Mon May 25 16:04:08 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * i386gas.h (ASM_OUTPUT_OPCODE): Translate "repnz" to "repne". + * seq386gas.h (ASM_OUTPUT_OPCODE): Likewise. + + Mon May 25 15:53:31 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * optabs.c (emit_indirect_jump): Emit barrier here. + * stmt.c (expand_computed_goto): Not here. + + Mon May 25 06:22:59 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * cse.c (canon_reg): Must call validate_change if insn has any + MATCH_DUPs even if replacing a pseudo with another pseudo. + + * explow.c (emit_stack_{save,restore)}: Call validize_mem on save area. + + * combine.c (simplify_shift_const, case PLUS): Simplify cases where + the PLUS is just turning on bits that will be shifted out. + + * emit-rtl.c (gen_lowpart_common): Add new case for single-word + float->integer conversion; all others already present. + Check for -fpretend-float in this and the other cases. + + * stmt.c (expand_goto): Fix typo in previous change. + + * reload1.c (gen_input_reload): When checking for validity of + reloads made for asms, also check the constraints. + + * explow.c (allocate_dynamic_stack_space): Don't add to size + if we aren't going to need to align the size. + + * fold-const.c (fold, case *_DIV_EXPR): Fold (a * C1) / C2 for + some C1 and C2. + + Sun May 24 14:07:53 1992 Ron Guilmette (rfg at ncd.com) + + * toplev.c (main): + Fix typo setting use_gdb_dbx_extensions in xcoff case. + + * c-decl.c (pushdecl): Call `build_type_copy' rather than calling + `c_build_type_variant' to duplicate a type. + + Sun May 24 16:56:09 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * reload1.c (reload): Refine setting of basic_block_needs. + + Sun May 24 15:43:08 1992 John F Carr (jfc at Achates.mit.edu) + + * combine.c (try_combine): Don't split an insn if that would move + a use of a register across a set of the same register. + + Sun May 24 14:50:38 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * reg-stack.c (constrain_asm_operands): Ignore constraint letters + following '#' in each alternative. + + Sun May 24 02:28:45 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * gcc.c (pexecute): New alternative definition for OS2. + Take SEARCH_FLAG as arg instead of FUNC. + (execute): Change call to pexecute. + + * toplev.c (main): Don't run ps for -dm if on OS2. + + * cccp.c (main): Use PATH_SEPARATOR computing num_dirs. + (path_include): Likewise, setting q. + + * gcc.c: Include sys/file.h. + + * Makefile.in (extraclean): Delete install1.texi. + + Sat May 23 14:14:06 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * crtstuff.c (__do_global_ctors) [not INVOKE__main]: Make body empty. + + * fold-const.c (float_error): Renamed from const_binop_error. + (const_binop, fold_convert): + Call set_float_handler around REAL_VALUE_TRUNCATE. + + * Makefile.in ($(srcdir)/INSTALL): New target. + (doc): Depend on that. + ($(srcdir)/gcc.info, $(srcdir)/cpp.info): Delete $(srcdir) from deps. + ($(srcdir)/gcc.info): List all subfiles as deps. + + * math-68881.h: Use %! instead of fpcr. + + * install.sh: New file. + * configure: Changed install_with_cp to broken_install. + Test that flag for the host, not for the target. + If set, use install.sh. + + * Makefile.in (EXTRA_HEADERS): New variable. + (USER_H): Use that. + * configure: Let alternatives set EXTRA_HEADERS via var header_files. + (m68k-...): Set header_files to install math-68881.h. + + * Makefile.in (install-dir): Create (libsubdir)/include. + (install-limits-h, install-float-h): Depend on install-dir. + + * Makefile.in (gcc.xtar): Warn if version in gcc.texi is old. + + * genconfig.c (main): Add 1 when outputting MAX_RECOG_OPERANDS. + Initialize to just 9. + + * gcc.c (MD_STARTFILE_PREFIX_1): New config macro. + (main): Use that like MD_STARTFILE_PREFIX. + + Sat May 23 08:13:38 1992 John F Carr (jfc at Achates.mit.edu) + + * reload1.c (reload): Copy MEM_IN_STRUCT_P flag when converting + pseudo register to equivalent memory location. + + Sat May 23 07:12:15 1992 Michael Meissner (meissner@osf.org) + + * x-iris (OLDCC): Add -cckr to turn off strict ANSI checking. + + * mips.c (current_function_name): Delete definition, function.c + defines this and mips.h has a declaration. + + * longlong.h (mips umul_ppmm): Use "d" constraint instead of "r", so + that we know the value is an integer register. + + Sat May 23 01:14:49 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * vax.h (PRINT_OPERAND): Undo last change. + Fix the comment instead. + + * x-dpx2200, x-dpx2300 (ALLOCA_FINISH, AS): New variables. + + Fri May 22 01:52:22 1992 Ron Guilmette (rfg at ncd.com) + + * svr4.h (MD_EXEC_PREFIX): Added definition. + + * protoize.c [POSIX]: Include dirent.h rather than sys/dir.h. + (_POSIX_SOURCE): Undef before defining. + (getpwd): Change declaration to an `extern'. + (open): Add declaration in the #if 0 section along with fprintf. + (link, unlink, access, execvp): Add `extern' declarations. + (strlen): Don't mention arg type in declaration. + (main): Declare `params' as `const char *' to avoid botch when doing + test-protoize-simple. + + Fri May 22 17:15:36 1992 John F Carr (jfc at Achates.mit.edu) + + * calls.c (expand_call): Allocate stack space for arguments passed + in registers when OUTGOING_REG_PARM_STACK_SPACE is defined and + stack space has not been preallocated. + + Fri May 22 17:16:55 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * combine.c (simplify_comparison): Try to reduce size of a + constant by changing comparison code; don't only do for 1 and -1. + + * reload.h (reg_equiv_memory_loc): Declare. + * reload.c (refers_to_regno_for_reload_p): Use reg_equiv_memory_loc + instead of reg_equiv_mem and reg_equiv_address; look for constant. + (reg_overlap_mentioned_for_reload_p): LIkewise. + Use new function to check for MEM. + (refers_to_mem_for_reload_p): New function. + * reload1.c (reg_equiv_memory_loc): No longer static. + + Fri May 22 17:15:12 1992 Ron Guilmette (rfg at ncd.com) + + * Makefile.in (test-protoize-simple): Only delete files made by this + target (not the man pages!) + (test-protoize-simple): Use -x option to avoid munging getopt.h. + (test-protoize-simple): Fixed number of differences message. + (mostly-clean): Properly remove all temp files relating to protoize/ + unprotoize. + (install-common): Force removal of previously installed g++ and c++ + command files before trying to install new ones. + + * spc-sol2.h: New file. + + * configure (sparc-*-solaris2*): New configuration added. + + * x-sparcv4 (X_CFLAGS): Removed -Bstatic and -dn options. + + Fri May 22 15:30:05 1992 Chip Salzenberg (chip@tct.com) + + * c-common.c (declare_function_name): Move from c-decl.c. + Construct function names instead of expecting them as parameters. + Set TREE_READONLY and other attributes before calling pushdecl. + * c-decl.c (init_decl_processing, store_parm_decls): Calls changed. + (declare_function_name): Remove to c-common.c. + + * cp-decl.c (init_decl_processing, store_parm_decls): + Call declare_function_name. + + Fri May 22 12:15:16 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * sparcv4.h (ASM_OUTPUT_CASE_LABEL): Define. + + Fri May 22 11:40:00 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * x-dpx2200, x-dpx2300 (CFLAGS): Definition deleted. + + * c-decl.c, cp-decl.c (pushdecl): No shadow warnings if DECL_IGNORED_P. + + * c-decl.c (declare_function_name): + Change names to __FUNCTION__ and __PRETTY_FUNCTION__ + + * vax.h (PRINT_OPERAND): In M case, don't complement after subtract 1. + + * c-lex.c (yylex): Use pedwarn for overflow warnings. + Pedwarn if constant doesn't fit its type. + + Fri May 22 13:32:39 1992 Chip Salzenberg (chip@tct.com) + + * xcoffout.h (DBX_TYPE_DECL_STABS_CODE): Was DBX_DECL_STABS_CODE. + + Fri May 22 08:31:16 1992 Torbjorn Granlund (tege@hal.gnu.ai.mit.edu) + + * longlong.h (all machines): Define UMUL_TIME and UDIV_TIME. + Auxiliary formatting changes. + (header): Define __CLOBBER_CC and __AND_CLOBBER_CC. + (__sparc__ macros): Use them. + (__hppa__ add_ssaaaa,sub_ddmmss): Accept zero using `M' constraint. + (__hppa__ umul_ppmm): Define if _PA_RISC1_1. + (__mc88110__ umul_ppmm,udiv_qrnnd): New. + (__pyr__ umul_ppmm): Rewrite. + (default count_leading_zeros): Make it work for 64 bit longs. + + Fri May 22 06:27:31 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * cse.c (cse_insn): Invalidate a volatile destination. + + * expmed.c (expand_divmod): Correctly handle volatile operands. + + Fri May 22 06:26:50 1992 Chip Salzenberg (chip@tct.com) + + * rs6000.h (ASM_DECLARE_FUNCTION_NAME): Use new function + xcoffout_declare_function(). + * rs6000.c (output_epilog): Shorten internal label. + (output_toc, output_function_profiler): Likewise. + * xcoffout.c (xcoffout_declare_function): New function, created + to localize knowledge of end-of-function internal label. + (xcoffout_end_epilogue): Shorten internal label. + + Thu May 21 15:31:42 1992 Jim Wilson (wilson@sphagnum.cygnus.com) + + * reorg.c (relax_delay_slots): Clear INSN_FROM_TARGET_P when + remove insns from a delay slot. + + Thu May 21 13:54:15 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * reload.c (find_reloads): + Don't abort for % in last operand in asm_operands. + + * alloca.c: Make symlink to master copy. + + * stmt.c (expand_asm_operands): Count nclobbers properly. + + * explow.c (allocate_dynamic_stack_space): Call mark_reg_pointer. + + * c-parse.y (stmt, WHILE case): Start loop *after* parsing end test. + (do_stmt_start): Broken out from DO rule. + (stmt, DO case): Use that. + Add error-handler rule for parse error in end test. + + * sparc.h (ADDITIONAL_REGISTER_NAMES): Support `cc'. + + * c-lex.c (yylex): Pedwarn if `f' constant exceeds range of `float'. + Just once even if `f' appears twice. + This and the like warning for `double' are only if -pedantic. + + Thu May 21 08:46:30 1992 Jim Wilson (wilson@sphagnum.cygnus.com) + + * Makefile.in (STAGESTUFF): Add stamp-proto. + + Thu May 21 04:04:33 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * svr3.h (LOCAL_LABEL_PREFIX): Override as a period. + (ASM_OUTPUT_INTERNAL_LABEL, ASM_GENERATE_INTERNAL_LABEL): + Use LOCAL_LABEL_PREFIX. + * dpx2.h (LOCAL_LABEL_PREFIX): Definition deleted. + * tower-as.h (LOCAL_LABEL_PREFIX): Override as empty. + + Wed May 20 23:29:15 1992 (Eric Youngdale at youngdale@v6550c.nrl.navy.mil) + + * config-gcc.com: Take care of situation if sources are NFS mounted. + + Wed May 20 14:35:10 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * jump.c (jump_optimize): Add additional validation check to + case that detects "if (foo) bar++;". + + Wed May 20 13:18:09 1992 Tim Moore (moore@defmacro.cs.utah.edu) + + * pa.md : Changed "xy" constraints to "x" constraints. + (movsi+6): Let "r" registers match too. Add define_split to change + into 2 insns if needed. + (decrement_and_branch_until_zero): New pattern. + * pa.h (FUNCTION_ARG_PASS_BY_REFERENCE): Fix for TYPE == 0. + (REGISTER_MOVE_COST): Do stuff for SNAKE_FP_REGS. + (PRINT_OPERAND_ADDRESS): Write CONST_INT case. + + Wed May 20 00:04:55 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * ns32k.h (NS32K_DISPLACEMENT_P): Fix typo. + * ns32k.md (extzv-1): New pattern for extracting from SImode. + + * g++: -M suppresses -lg++. + + * svr3.h (DO_GLOBAL_CTORS_BODY): Flush spurious #endif. + + * reload1.c (gen_input_reload): New arg IS_ASM. Can now return 0. + (emit_reload_insns): Pass new arg. Error if it returns 0. + + * configure: Use $cpu_type to default $tm_file. + + * configure, config.sub: Correct we32 to we32k. + * configure (decstation-dec): Deleted--doesn't fit as machine alias. + (we32k): Add company default. + (fx2800): This is a machine alias, not a company default. + + * configure (i386-*-bsd*, we32-att-sysv*, m68k-crds-unos*): + Missing *'s added at ends of config names. + + * c-typeck.c (convert_arguments): Use warn_for_assignment to handle + -Wconversion. Fix typo in width-mismatch test. + + * svr3.h (ASM_GENERATE_INTERNAL_LABEL): Put a * at the front. + + Tue May 19 21:53:05 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * Makefile.in (clean): Add -f in rm *.dvi. + + * x-dpx2200, x-dpx2300 (CFLAGS): Make value conditional on CC. + + * genattrtab.c (simplify_test_exp, evaluate_eq_attr): + Delete tests of current_alternative_string; they caused bugs. + + * cross-test.c: New file. + * Makefile.in (cross-test, cross-test.o): New targets. + (all.cross): Depend on cross-test. + + * c-decl.c (declare_function_name): Fix bug in previous change. + + Tue May 19 19:57:39 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * i960.h (FUNCTION_ARG_BOUNDARY): Return mode's alignment if type 0. + + * calls.c (expand_call): Set MEM_IN_STRUCT_P for aggregate return + values in memory. + + * function.c (locate_and_pad_parm): Use MAYBE_REG_PARM_STACK_SPACE + if defined. + * i960.c (i960_function_arg_advance): Put MUST_PASS_IN_STACK + parameters on the stack. + (i960_function_arg): Likewise. + + * m68k.md (zero_extendqisi2+1): Add condition to exclude MEM/MEM + case which would require reloading. + + * unroll.c: Delete incorrect Feb 26 1992 change. + (copy_loop_body): For combined address givs, scale giv_inc by the + two giv's multiplicative factors if they are different. + + * i960.md (zero_extendqisi2): Add comment. + + * combine.c (apply_distributive_law): Don't distribute subregs + which change the mode class. + + * fixincludes: Fix memory.h for SunOS. + + * sparc.h (EXTRA_CC_MODES, EXTRA_CC_NAMES): Add CCFPEmode, for + compares which should generate exceptions for qNaNs. + (SELECT_CC_MODE): Use CCFPEmode for non EQ/NE FP compares. + * sparc.c (normal_comp_operator): Handle CCFPEmode. + (C_MODES, output_cbranch): Likewise. + * sparc.md (cmpdf, cmpsf): Modify patterns to use fcmpe for CCFPE + mode, and fcmp for CCFP mode. + + From rfg: + * sparc.h: Declare output_move_quad, output_fp_move_quad and + output_floatsitf2. + * sparc.c (mem_aligned_8): New function. + (output_move_double): Clean up a little. Call mem_aligned_8. + Load operands[] into register variables for efficiency. + (output_move_quad, output_fp_move_quad): New functions. + (output_floatsitf2): New function. + (print_operand): Support 'S' and 'T'. + * sparc.md (cmptf, movtf, extendsftf2, extenddftf2, trunctfsf2, + trunctfdf2, floatsitf2, fix_trunctfsi2, addtf3, subtf3, multf3, + divtf3, negtf2, abstf2, sqrttf2): New patterns added for TFmode + support. + + Tue May 19 19:34:10 1992 Ron Guilmette (rfg at ncd.com) + + * i386v4.h (DBX_REGISTER_NUMBER): Fixed DWARF numbers for + x86 floating-point registers. + + Tue May 19 15:30:32 1992 Mats Lofkvist (d87-mal@nada.kth.se) + + * fixincludes: Fix return type of malloc and friends. + + Tue May 19 13:30:16 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * config.sub (iris4d): If $os is some kind of Irix, don't clobber it. + Make the default -irix4. + + * c-decl.c (declare_function_name): New arg printable_name. + Declare __PRINTABLE_NAME__. + (init_decl_processing, store_parm_decls): Pass the new arg. + + Tue May 19 09:50:01 1992 Tom Wood (wood@dg-rtp.dg.com) + + * m88k.c (output_options): Check profile_block_flag. + (m88k_layout_frame): Ditto. + (output_function_block_profiler): Save and restore the parameter + registers when calling __bb_init_func. + (output_block_profiler): Use @LPBX2. + + * m88k.h (CASE_VECTOR_INSNS): Choose a table of branch + instructions or addresses. The latter is a win for the m88110. + (ASM_OUTPUT_CASE_END): Nothing needed for table of addresses. + (ASM_OUTPUT_ADDR_VEC_ELT): Use "br" or "word". + * m88k.md (casesi, casesi_jump): Updated. + + * m88k.md (m88110 function units): Count in half cycles. + + * m88k.md (call insns): Clobber rather than use r1. + + * m88k.c (m88k_layout_frame): Fix m88k_fp_offset for zero case. + + Mon May 18 10:38:20 1992 Michael Meissner (meissner@osf.org) + + * iris.h (DEFAULT_SIGNED_CHAR): Define as 0 for compatibility with + IRIS defaults. Patch from kevin@tamri.com (Kevin Dalley). + + * xm-irix4.h (HAVE_VPRINTF): Define. + + * x-iris (CLIB): Add -lmalloc. + + * mips.md (fp_comp functional unit): Use adder functional unit + instead to more closely model MIPS behavior and make genattrtab + faster. + (transfer functional unit): Use memory functional unit instead. + (sqrt functional unit): Use divide functional unit instead. + (branch_zero): If CSE has folded a value which is constant, and + the jump would be omitted, do not eliminate putting a jump there. + This causes bad code to be generated when using gas, since the + previous instruction may be a load which had it's delay slot + filled by the 'branch', and the next instruction depends on the + value loaded. + + * mips-at.c (whole file): Delete, no longer needed. + + * mips-at.md (whole file): Delete, no longer needed. + + * Makefile.in (stamp-attrtab): Remove $(srcdir) in front of + $(PREMADE_ATTRTAB) so that MIPS builds can be done in + subdirectories. + + * t-decrose (PREMADE_ATTRTAB*): Don't define, genattrtab is now fast + enough that we don't have to save a pre-made genattrtab.c. + (LIBGCC1): Use libgcc1.null rule to turn off building libgcc1.a. + + * t-decstatn (PREMADE_ATTRTAB*): Don't define, genattrtab is now fast + enough that we don't have to save a pre-made genattrtab.c. + (LIBGCC1): Use libgcc1.null rule to turn off building libgcc1.a. + + * t-mips (PREMADE_ATTRTAB*): Don't define, genattrtab is now fast + enough that we don't have to save a pre-made genattrtab.c. + (LIBGCC1): Use libgcc1.null rule to turn off building libgcc1.a. + + * mips.h (ASM_OUTPUT_CONSTRUCTOR,ASM_OUTPUT_DESTRUCTOR): Define. + Patch from wilson@cygnus.com. + (DEFAULT_SIGNED_CHAR): Don't define if already defined. + + Mon May 18 01:34:38 1992 Kayvan Sylvan (kayvan@satyr.Sylvan.COM) + + * svr3.h (DO_GLOBAL_CTORS_BODY): Start at end, if STACK_GROWS_DOWNWARD. + + Mon May 18 01:34:38 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * Makefile.in (protoize.o, unprotoize.o): + Do nothing, but depend on stamp-proto. + (stamp-proto): New target. Compile both protoize.o and unprotoize.o. + + * configure (ns32k-ns-genix): Commented out. + + * expmed.c (expand_mult): Use synth_mult even if not -O. + + Sun May 17 02:54:21 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * c-decl.c (push_parm_decl): Pedantic warning if shadowing typedef. + + * c-typeck.c (constant_expression_warning): New function. + (store_init_value): Call that. + * tree.h (TREE_CONSTANT_OVERFLOW): New flag. + + * c-lex.c (yylex): "exceeds range" warning changed to pedwarn. + * c-decl.c (grokdeclarator): Likewise for duplicate keywords. + + * c-typeck.c (build_unary_op): For increment operators, + test TREE_READONLY in operand, not the data type. + + * unprotoize.c: New file. + * Makefile.in (unprotoize.o): Use that. + + * c-decl.c (init_decl_processing): Make global decl for __NAME__. + (store_parm_decls): Make local decl for __NAME__. + (declare_function_name): Subroutine for that. + * toplev.c (rest_of_decl_compilation): + Ignore initialized statics if DECL_IGNORED_P is set. + * c-lex.c (yylex): Convert invisible initialized char array vars + to string constants. + + * c-decl.c (get_parm_info): Change error message. + + Sat May 16 21:25:21 1992 Paul Eggert (eggert@twinsun.com) + + * fold-const.c (fold): Do not fold X-X to 0 if X is floating point. + + * cse.c (simplify_unary_operation): - -X simplifies to X even + with IEEE floating point. + + Sat May 16 14:14:50 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * Makefile.in (clean): Delete *.dvi. + (distclean): Not here. + + * Makefile.in (install-man): Ignore errors in all commands. + + * combine.c (expand_compound_operation): + Don't simplify extending a const_int. + + * ns32k.h (NS32K_DISPLACEMENT_P): New macro. + (INDIRECTABLE_1_ADDRESS_P): Use that. + * ns32k.md (addsi3): Likewise. + + Sat May 16 07:47:11 1992 Tom Wood (wood@dg-rtp.dg.com) + + * m88k.h: Override SET_ASM_OP in svr4.h. + + Sat May 16 00:10:09 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * c-parse.y (parmlist_1): Add pedantic warning. + + Fri May 15 13:10:07 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * configure (i386-*-sco3.2v4*): New file. + * config.sub: For SCO, produce -sco3.2v2. For ISC, make just -isc. + + * dbxout.c (DBX_TYPE_DECL_STABS_CODE): Was DBX_DECL_STABS_CODE. + (DBX_OUTPUT_ENUM): Pass type as arg; make it do the whole job. + + * svr4.h (ASM_BYTE_OP): Delete the tab. + (SET_ASM_OP): New definition. + + * Makefile.in (gcc.xtar): Depend on doc. + (gcc.info, cpp.info): Duplicate rules deleted. + + * i386.c (handle_pragma): Use SET_ASM_OP, not DEF_ASM_OP. + + Fri May 15 12:38:18 1992 Jim Wilson (wilson@sphagnum.cygnus.com) + + * final.c (final_scan_insn): Don't set new_block when within a + sequence. Set it after the last insn of the sequence. + + Fri May 15 07:23:09 1992 Tom Wood (wood@dg-rtp.dg.com) + + * m88k.c (m88k_handle_pragma_token, output_short_branch_defs): + Use SET_ASM_OP. + + Fri May 15 14:54:54 1992 Howard Chu (hyc@hanauma.jpl.nasa.gov) + + * fx2800.h: Replace Ron Guilmette's version with working version. + Tested on Concentrix 2.1 and 2.2. + + * i860.c (singlemove_string): Comparison of const0_rtx was in the + wrong place and would never be reached. Added check for negative + short int constants. + (output_size_for_block_move): call singlemove_string instead of + just emitting a mov. + (sfmode_constant_to_ulong): eliminate bogus "# error" directive. + + * t-fx2800, x-fx2800, xm-fx2800.h: New files. + * configure: Corresponding changes. + + * dbxout.c (DBX_MEMPARM_STABS_LETTER): New macro. + (dbxout_type): Check for DBX_OUTPUT_ENUM. + (dbxout_parms): Use DBX_MEMPARM_STABS_LETTER. + (dbxout_block): Check for DBX_OUTPUT_LBRAC, DBX_OUTPUT_RBRAC. + + Thu May 14 18:26:13 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * sparcv4.h (ASM_OUTPUT_ALIGN_JUMP_TABLE, ASM_OUTPUT_INTERNAL_LABEL, + ASM_GENERATE_INTERNAL_LABEL): Delete. + + Thu May 14 13:51:01 1992 Chip Salzenberg (chip@tct.com) + + * toplev.c (compile_file): Use IO_BUFFER_SIZE for finput. + * xm-i386sco.h, xm-rs6000.h (IO_BUFFER_SIZE): Defined. + + Thu May 14 15:21:24 1992 Roland McGrath (roland@albert.gnu.ai.mit.edu) + + * config.sub: Recognize "none" as a valid os. + + Thu May 14 13:37:52 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * function.c (assign_parms): Make new stack slot if entry stack + slot isn't aligned as much as the mode wants. + And don't make an eqv for entry_parm in that case. + * sparc.c (output_move_double): Assume memory always ok for ldd, std + except when explicit offset from stack. + + * c-decl.c (duplicate_decls): + Don't warn about qualifier mismatch for a function. + + * c-decl.c (grokdeclarator): Give explicit list of types to promote + to int (and sometimes to unsigned int) for parms. + + * Makefile.in (gcc.info, cpp.info): New targets. + (gcc.xtar): Depend on those. + + * expmed.c (extract_bit_field): Don't fail to compute + all of a DImode value. + + * dwarfout.c (SET_ASM_OP): Renamed from DEF_ASM_OP. + (ASM_OUTPUT_DEF): Use SET_ASM_OP. + * m88k.h (SET_ASM_OP): Renamed from DEF_ASM_OP. + * sparcv4.h (DEF_ASM_OP): No need for #undef. + + * cccp.c (main): Handle -iprefix option instead of GCC_EXEC_PREFIX. + * gcc.c (process_command): Set gcc_exec_prefix. + (do_spec_1): Handle %I. + (default_compilers): Use %I when running cpp. + + * protoize.c (savestring, savestring2): Change parm decls. + + * i860.h, we32k.h (CONST_COSTS): Add missing parm OUTER_CODE. + + * i386v4.h (DEF_ASM_OP, WEAK_ASM_OP): Deleted. + + Wed May 13 17:23:45 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * rtl.c (init_rtl): For byte_mode and word_mode, use first fit. + + * protoize.c (munge_compile_params): Increase size of temp_params. + + Wed May 13 13:30:40 1992 Chip Salzenberg (chip@tct.com) + + * i386sco4.h: New file. + + Tue May 12 23:23:51 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * expr.c (expand_increment): A subreg as op0 is not necessarily a copy. + Treat subregs like regs. + + * c-typeck.c (mark_addressable): Different messages for reg var + if reason is a use in a nested function. + + Tue May 12 14:28:22 1992 Tom Wood (wood at gen-rtx) + + * gcc.c (process_command): -save-temps uses a switches entry. + + Tue May 12 21:24:46 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * collect2.c (vfork): Declaration deleted. + + Tue May 12 06:16:49 1992 Niklas Hallqvist (niklas@appli.se) + + * tower-as.h: Added support for basic block profiling. + + Tue May 12 02:34:45 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * unx386.h (AS3_SHIFT_DOUBLE): New macro to print shift-double + opcodes. + + * i386gas.h (AS3_SHIFT_DOUBLE): Redefine for GAS shift-double rules. + (GAS_MNEMONICS): New macro to force use of opcodes for GAS. + * seq386gas.h (AS3_SHIFT_DOUBLE,GAS_MNEMONICS): Likewise. + + * i386.c (print_operand): Use GAS_MNEMONICS to choose long-long + opcode suffix. + + * i386.md (ashldi3,ashrdi3,lshrdi3): Split into separate + recognizers for constant and variable shifts. + Use AS3_SHIFT_DOUBLE for variable shifts. + (all shifts and rotates): Don't allow memory operands for shift + count. + (bit set/clear): Don't allow non-CONST_INT constants as SET_SRC. + (movstrsi,cmpstrsi,strlensi): Allow any address_operand within + a MEM:BLK, not just register_operand. + (movstrsi): Rewrite to avoid match_dup on the address_operand + above. + + Mon May 11 23:31:47 1992 Mike Stump (mrs@albert.gnu.ai.mit.edu) + + Sun May 10 18:44:58 Per Bothner (bothner@cygnus.com) + + * dbxout.c (dbxout_type_methods): Only emit final semi-colon + of method list of we have emitted any methods. (The converse + of only emitting the operation name initially if needed.) + + Mon May 11 22:45:18 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * reload.c, reload1.c: Use reg_overlap_mentioned_for_reload_p and + refers_to_regno_for_reload_p instead of the normal versions. + * reload.c (reg_overlap_mentioned_for_reload_p): New function. + + Mon May 11 22:44:50 1992 Ron Guilmette (rfg at ncd.com) + + * integrate.c (expand_inline_function): Copy LABEL_NAMEs to new + copies of CODE_LABELs. + * tree.c (decl_function_context, decl_type_context): Renamed `fndecl' + formal parameter to `decl' throughout these functions. + + Mon May 11 18:43:45 1992 Paul Eggert (eggert@twinsun.com) + + * cccp.c: (deps_file): Deleted. + (main): Do not open deps_file until needed. + Check error status of dep_stream and stdout more carefully. + (timestamp): New function; avoids calling localtime unless needed. + (special_symbol, initialize_builtins): Use new timestamp function. + + Mon May 11 20:48:26 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * genix.h: Added #error, since this hasn't been updated. + + Mon May 11 14:33:32 1992 Ron Guilmette (rfg at ncd.com) + + * dwarfout.c (is_pseudo_reg): New function. + (location_attribute): Use `is_pseudo_reg'. + (location_or_const_value_attribute): Use DECL_INCOMING_RTL as the + basis for forming the location decsriptor for any register parameter + which was optimized into non-exitance. + + * dwarfout.c (DWARF_VERSION): New (default) definition. + (ASM_OUTPUT_DWARF_STACK_OP, ASM_OUTPUT_DWARF_FMT_BYTE, + ASM_OUTPUT_DWARF_TYPE_MODIFIER, ASM_OUTPUT_DWARF_DATA1): Output tab + before ASM_BYTE_OP. + (ASM_OUTPUT_DWARF_ADDR_CONST): Encapsulate all statements in a + `do { ... } while (0)' + (data_member_location_attribute, bit_offset_attribute): Both fixed + to use alignment of declared type of field as the "containing object" + size. + (location_or_const_value_attribute): Fixed to use DECL_INCOMING_RTL + only for parms passed in memory. + (output_decl): Don't output DIEs for externals if DWARF_VERSION == 1. + + Sun May 10 17:18:33 1992 Torbjorn Granlund (tege@hal.gnu.ai.mit.edu) + + * pa.h (CPP_PREDEFINES): Define for BSD here. + Remove conditional #ifdef hpux. + * pa-hpux.h, pa-ghpux.h (CPP_PREDEFINES): Define for hpux here. + * pa.h (CPP_SPEC): Define. + + Sun May 10 12:12:06 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * Makefile.in (clean): Delete unprotoize.c. + + * stmt.c (expand_decl): Set MEM_IN_STRUCT_P right in dynamic case. + + * expr.c (get_inner_ref): Handle ARRAY_REF only if constant offset. + Handle non-PLUS_EXPR variable offset by assuming multiple of byte. + (expand_assignment, expand_expr): Fix gen_rtx added in last change. + + Sat May 9 02:39:58 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * expr.c (get_inner_reference): New output arg poffset. + (expand_assignment, expand_expr): Pass new arg. Handle nonzero offset. + (do_jump): Pass new arg but ignore result. + * fold-const.c (optimize_bit_field_compare, decode_field_reference): + Pass the new arg. Just return 0 if offset comes back nonzero. + + * reload.c (find_equiv_reg): Always test valueno >= 0. + + * c-aux-info.c: Don't include param.h or errno.h; don't declare errno. + + * rtl.c (read_rtx): Fix error in prev change. + + * gcc.c (process_command): Handle -print-libgcc-file-name. + (main): Handle print_libgcc_file_name by printing the name. + + * c-decl.c (finish_struct): Use TYPE_PRECISION to see whether + bitfield's type is narrower than int, for promoting to int. + + * cccp.c (struct definition, struct reflist): New field `rest_args'. + (struct arglist): Likewise. + (rest_extension, REST_EXTENSION_LENGTH): New var and macro. + (create_defnition): Recognize `...' and set flag in arglist. + (collect_expansion): Propagate flag to definition. + (macroexpand): Check flag when parsing arglist. + Special handling for ## next to a rest arg. + (macarg, macarg1): New arg rest_arg affects parsing in macarg1. + + * genattrtab.c: Misc speedups and size reductions. + (check_attr_test): Set RTX_UNCHANGING_P for tests of const attributes. + Also for symbol_ref and comparison ops. + (make_canonical): Likewise. Also check for degenerate cond values. + (operate_exp, simplify_cond, insert_right_side, evaluate_eq_attr): + Avoid copying in some cases. Detect opportunities to simplify. + (compute_alternative_mask): Avoid atoi in most cases. + (copy_rtx_unchanging): New function. + (evaluate_eq_attr, simplify_test_exp): Use that. + + * genattrtab.c (optimize_attrs): Work pattern by pattern, + doing all the work for each pattern before moving on. + Use temp_obstack during simplification, then copy the end result. + (temp_obstack): New obstack. + (clear_struct_flag): New subroutine. + (SIMPLIFY_TEST_EXP): Test MEM_IN_STRUCT_P. + (simplify_test_exp): Add code for debugging stop. + Avoid consing when possible; sometimes free storage. + Check MEM_IN_STRUCT_P. Add shortcuts. + + * genattrtab.c: Add simplification per alternative (not in use now). + (insn_n_alternatives): New array filled in by gen_insn. + (current_alternative_string): Nonzero means we are simplifying + for a particular alternative. Value is string for that numeral. + (SIMPLIFY_ALTERNATIVE): New macro simplifies eq_attr for alternative. + (evaluate_eq_attr, simplify_test_exp): Call SIMPLIFY_ALTERNATIVE. + (simplify_by_alternatives, count_sub_rtxs): New functions. + + * genattrtab.c (attrs): Now an array indexed by first char. + (MAX_ATTRS_INDEX): Length of above. + (find_attr, main): Use that new data structure. + + * genattrtab.c: Clarify use of hash-consing: + (hash_obstack): New obstack. + (attr_hash_add_rtx, attr_hash_add_string): Use hash_obstack. + (attr_rtx): Use hash_obstack if object is hashed. + Set RTX_INTEGRATED_P if object is hashed. + Don't hash object if subexpressions aren't hashed. + If making symbol_ref, hash the symbol name. + Uniquize const_int with value 0 or 1. + (attr_equal_p): New compare function; uses RTX_INTEGRATED_P. + (simplify_and_tree, simplify_or_tree, simplify_test_exp): Use that. + (attr_copy_rtx): New; copy all but hashed subexpressions. + (attr_eq): New function. + (attr_numeral): New function. + (check_attr_test): Use attr_eq. Hash symbol_ref and comparison ops. + (check_attr_value): Return modified value. Callers changed. + Hash symbol_ref. + (convert_set_attr_alternative): Use attr_eq and attr_numeral. + (convert_const_symbol_ref): Hash symbol_ref and eq. + (make_alternative_compare): Use attr_numeral. + (alternative_name): Fill in using hasher. + (copy_boolean): Hash a boolean expression if possible. + + Fri May 8 23:10:18 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * i386.md (ashldi3,ashrdi3,lshrdi3): Fix typo in output template. + + * cse.c (cse_insn): Handle SUBREGs in CLOBBERs. + + Fri May 8 14:55:17 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * Makefile.in (PREMADE_ATTRTAB, PREMADE_ATTRTAB_MD): New vars. + (stamp-attrtab): Use them, to use presupplied file if suitable. + * t-mips, t-decstatn, t-decrose (PREMADE_ATTRTAB, PREMADE_ATTRTAB_MD): + Defined. + * mips-at.md, mips-at.c: New files. + + * c-common.c (shorten_compare): Extend "always 0" warning + to fencepost case with le or ge. + + * cccp.c (pass_thru_directive): Don't output a newline. + (initialize_builtins): Add explicit newlines in sprintfs. + + Fri May 8 14:49:12 1992 Michael Meissner (meissner@osf.org) + + * mips.md (adddi3): Force -32768 into a register, since the + define_insn's won't accept that one value. + (all attributes): Where an attribute is set to the same value in all + alternatives, don't use the alternative notation, since it will make + genattrtab somewhat faster. + + * rtl.c (read_rtx): Use the current obstack to read in strings, + rather than repeated malloc/realloc's. + + Thu May 7 18:41:03 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * calls.c (expand_call): Never set must_preallocate if no stack args. + + Thu May 7 16:52:56 1992 Torbjorn Granlund (tege@hal.gnu.ai.mit.edu) + + * pa1*: New names for pa1.1*. + * configure: Corresponding changes. + + * m68k.md (u?mulsidi3): Don't permit immediates for operand 2. + (u?mulsidi3 recognizers): Split into immediate/nonimmediate cases. + * m68k.md ({zero,sign}_extend recognizers): Remove `n' from constraint + if predicate doesn't permit constants. + + Thu May 7 15:42:32 1992 Michael Collison (collison at osf.org) + + * i386rose.h (ASM_OUTPUT_FLOAT, ASM_OUTPUT_DOUBLE): Fix these to + avoid printing NaNs, and infinity. + (SUBTARGET_SWITCHES): Add OSF dependent switches for half-pic + support. + (MASK_HALF_PIC, TARGET_HALF_PIC): Likewise. + (CC1_SPEC): Map pic-none, pic-lib, pic-extern and pic-calls + to appropriate half-pic compiler switches. + (LINK_SPEC): If not -noshrlib or -pic-none, pass -warn_nopic. + Allow user to pass -noshrlib directly. + (OPTIMIZATION_OPTIONS): Customize levels for OSF. + (CONSTANT_ADDRESS_P: Add check to determine if we have a + half-pic constant. + (ENCODE_SECTION_INFO): Check to see if we have a half-pic + declaration. + (ASM_DECLARE_OBJECT_NAME): Output the label (definition) for a + object and check to see if it is half-pic. + (ASM_DECLARE_FUNCTION_NAME): Likewise but for functions. + + Thu May 7 15:56:51 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * reload.c (find_reloads): Remover unterm comment from recent changes. + + * genattrtab.c (compute_alternative_mask): Usually bypass atoi. + + Thu May 7 15:56:51 1992 Tom Wood (wood@dg-rtp.dg.com) + + * genattrtab.c (fill_attr): Do nothing for constant attribute. + (check_attr_test): Set unchanging flag for constant attribute. + (write_test_expr): Expand constant attributes here. + + Thu May 7 06:01:46 1992 Michael Meissner (meissner@osf.org) + + * decrose.h (CPP_SPEC): Fix typo in last change. + + Wed May 6 17:39:31 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * convex.h (HAVE_STRERROR, vfprintf, WTERMSIG, WEXITSTATUS): Deleted. + + * dbxout.c (dbxout_type): Don't repeat a cross-reference + merely because full is nonzero. + + * calls.c (expand_call): + Avoid rounding error testing copy_to_evaluate_size. + + * xm-mipsbsdn.h: Renamed from xm-mipsbsdnews.h. + * xm-sun386.h: Renamed from xm-xm-i386sun.h. + * configure: Corresponding changes. + + Wed May 6 23:11:55 1992 John F Carr (jfc at Achates.mit.edu) + + * cse.c (simplify_binary_operation): Support MIN and MAX for + SImode and narrower integers. + + Wed May 6 17:25:37 1992 Michael Meissner (meissner@osf.org) + + * mips.h (MIPS_VERSION): Bump Meissner version # to 18. + (mips_cpu_attr): New define, which is the mips_cpu variable recast + to the attr_cpu enumeration for mips.md. + (HALF_PIC_NUMBER_PTRS, HALF_PIC_NUMBER_REFS): Add dummy + definitions if halfpic.h is not included. + + * mips.c (function_epilogue): Print half-pic stats if -mstats and + the stats are non-zero. + + * mips.md (cpu attribute): Just use symbol_ref "mips_cpu_attr" + instead of a four way if statement. + (movsi_internal, movhi, movqi): Use 'z' constraint for fpsw, not 's'. + + * halfpic.h (half_pic_number_ptrs): Add counter for the number of + pointers generated. + (half_pic_number_refs): Add counter for the number of references. + + * halfpic.c (half_pic_number_ptrs): Add counter for the number of + pointers generated. + (half_pic_number_refs): Add counter for the number of references. + (half_pic_ptrs): Update new counters. + + * decstatn.h (CPP_SPEC): Define __LANGUAGE_x__ and __LANGUAGE_x + where x is C_PLUS_PLUS, OBJECTIVE_C, C, or ASSEMBLY. Fix + undef'ing LANGUAGE_C for .S files. + (HALF_PIC_PREFIX): Define as '$Lp.'. + + * decstatn.h (CPP_SPEC): Define __LANGUAGE_x__ and __LANGUAGE_x + where x is C_PLUS_PLUS, OBJECTIVE_C, C, or ASSEMBLY. + + * mips-tfile.c (toplevel): Don't define anything in the standard + headers, such as open, etc. + (add_procedure): Delete unused variable orig_fdb. + + * mips-tdump.c (toplevel): Don't define anything in the standard + headers, such as open, etc. + + * collect2.c (main): Don't pass -f switches to GCC when + building the constructor table. + (write_c_file): Put extern in front of all external declarations. + (scan_prog_file, COFF varient): On ECOFF systems, check whether + the header pointer is non-NULL before using it. + + * cp-lex.c (store_pending_inline): Cast obstack_copy arg to char *. + (copy_lang_decl): Cast bcopy args to char *. + + Wed May 6 13:28:58 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * i960.h, i960.c (hard_regno_mode_ok): Use unsigned int not short. + + * Makefile.in (USER_H): Add va-i960.h. + + Wed May 6 07:31:54 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * explow.c (emit_stack_{save,restore}): New functions. + * expr.h: Declare them and enum save_level. + * calls.c (expand_call): Call emit_stack_save. + * expr.c (expand_builtin, case BUILT_IN_ALLOCA): Likewise. + * function.c (delete_handlers): Make test for insn that sets + a slot more general. + (expand_function_end): Call emit_stack_{save,restore}. + * stmt.c (declare_nonlocal_label): Call emit_stack_save. + (expand_goto_internal): Likewise. + (expand_goto): Likewise. + Copy slots so they don't get instantiated incorrectly; also + update use of virtual regs and frame pointer. + (expand_end_bindings): Call emit_stack_restore. + (expand_decl): Call emit_stack_save. + Set current_function_calls_alloca when allocating variable-sized + objects. + * rs6000.md ({save,restore}_stack_{block,function,nonlocal}): New. + + Tue May 5 13:17:29 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * configure (a29k-*-*, i960-*-*): New default configurations. + + * i960.c, i960.h, i960.md, xm-i960.h, va-i960.h: New files. + + * gstdarg.h, gvarargs.h: Include va-i960.h for i960. + + * calls.c (expand_call): Call REG_PARM_STACK_SPACE once and save + result. Add code to Use new macros MAYBE_REG_PARM_STACK_SPACE and + FINAL_REG_PARM_STACK_SPACE. + (store_one_arg): New parameter reg_parm_stack_space. + * function.c (assign_parms): Use MAYBE_REG_PARM_STACK_SPACE. + + * cse.c (NONZERO_BASE_PLUS_P): Don't consider arg pointer by itself + to be non-zero, because it isn't on the i960. + + * dbxout.c (dbxout_symbol): Use decl_function_context not + TREE_PERMANENT to identify function local statics. + + * integrate.c (copy_rtx_and_substitute): Also remap SYMBOL_REFs + that point to LABEL_REFs in the constant pool. + + * expr.c (expand_expr, PLUS case): Canonicalize MULT + when associating a constant. + + Tue May 5 12:56:29 1992 Torbjorn Granlund (tege@mole.gnu.ai.mit.edu) + + * pa.c (singlemove_string): Make it global. + * pa.md: Add high:DI and lo_sum:DI patterns. + + Tue May 5 12:04:56 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * c-typeck.c (build_array_ref): Require int index *after* promotion. + + * convex.h (REG_OK_FOR_{BASE,INDEX}_P): Virtual regs that will + turn into stack_pointer_rtx are not valid for indexing. + + * config.sub: NeXT is BSD, not SysV. + + * att386.h (ASM_OUTPUT_INTERNAL_LABEL, ASM_GENERATE_INTERNAL_LABEL): + Undef before defining. + + * dbxout.c (dbxout_parms): Handle invisible reference parms. + + Tue May 5 22:48:54 1992 Niklas Hallqvist (niklas@appli.se) + + * Makefile.in (test-protoize-simple): + Change tmp-protoize* to tmp-proto*. + (mostlyclean): Remove that temporary file. + + Tue May 5 09:35:30 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * i386.c (print_operand): Handle VOIDmode CONST_DOUBLE correctly. + + * reload.c (find_reloads): Recompute `code' before preferred_class. + + Mon May 4 00:23:29 1992 Ron Guilmette (rfg at ncd.com) + + * svr3.h (ASM_OUTPUT_INTERNAL_LABEL, ASM_GENERATE_INTERNAL_LABEL): + Added definitions appropriate for most svr3 systems. + + * protoize.c (volatile): Define to nothing if !defined(__STDC__). + (setjmp, longjmp): Declared external if not defined as pp-macro. + (include_defaults): Fix type of `fname' field. + (compiler_file_name): Fixed type. + (savestring): Fixed type of `size' parameter. + (savestring2): New function. + (string_list_cons): Removed trailing blanks from parm declaration. + (find_file): Moved comments out of formal parm declarations area. + (munge_compile_params): Fixed type of `temp_parms'. + (gen_aux_info_file): Construct new filename using `savestring2'. + (find_extern_def): Suppress annoying warnings about missing + definitions for extern functions. + (edit_fn_declaration): Declare `clean_text_p' as `volatile' not as + `VOLATILE'. + (scan_for_missed_items): Make text of warning more obvious. + (edit_file): Make text of warning shorter. + + * libgcc2.c (__builtin_new): Changed arg type to `size_t'. Moved + nested declaration of malloc out to file-scope. + (__builtin_vec_new): Prototype preceeding function declarations. + (__builtin_vec_new, __builtin_vec_delete): Changed types of non-pointer + arguments and local variables to `size_t'. + (__clear_cache): Use type `void *' variables to store addresses. + (__do_global_dtors): Use unsigned type for counters. + (__main): Add explicit type to declaration of `initialized'. + + Mon May 4 16:16:56 1992 Tom Wood (wood at dg-rtp.dg.com) + + * dwarfout.c (dwarfout_file_scope_decl): Ignore a global register + variable. + + Mon May 4 08:28:18 1992 Torbjorn Granlund (tege@mole.gnu.ai.mit.edu) + + * pa-ghpux.h, pa-hpux.h: #define HAVE_ATEXIT. + + * genextract.c (print_path, main): Make the generated code use + `pat', not `insn', except for fatal_insn_not_found. Remove + insn_code variable from generated code, and switch directly on + INSN_CODE (insn). + + * hppa*: Rename to be unique in first 8 characters. + * configure: Corresponding changes. + + Mon May 4 00:20:39 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * reload.c (find_reloads): Compute preferred_class after + calling find_reloads_toplev or equivalent. + + * vax.h (PRINT_OPERAND): Add codes M, h, b. + + * ns32k.h (PREFERRED_RELOAD_CLASS): Change GEN_AND_MEM_REGS + to GENERAL_REGS. + + * config.sub: Recognize we32 and 3b*. + + * varasm.c (readonly_data_section): Move after data_section. + + * Makefile.in (print-rtl.o): Compile also for host machine. + (genattrtab): Link in host's print-rtl.o. + + * i386v4.h (ASM_OUTPUT_ALIGNED_LOCAL): Deleted. Dfn in svr4.h is good. + + Sun May 3 21:39:22 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * i386.h (RTX_COSTS): Add missing break. + + Sun May 3 19:40:50 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + From law: + * sparc.md (fp unit attributes): Change result ready delays to + match how the FP unit really works. + + * sched.c (schedule_block): Don't move USE at the end of any block. + + From rfg: + * sparc.c (handle_pragma_token): Added new function (based on original + `handle_pragma_token' in i386.c). + * sparcv4.h (INIT_SECTION_PREAMBLE): Definition added. + (PUSHSECTION_FORMAT): Added leading tab. + (HANDLE_PRAGMA): Added definition to handle #pragma weak (based on + original definition in i386v4.h). + + From jfc: + * sched.c (insn_costs): New variable. + (insn_cost): Save cost of insn in insn_costs to avoid recomputation. + (sched_analyze_2): Handle UNSPEC_VOLATILE. + (schedule_insns): Init insn_costs. + + * sparc.c (output_move_double): Correctly check for constant + DFmode addresses. Assume that DFmode addresses with MEM_IN_STRUCT_P + set are always aligned. + + Sun May 3 16:52:06 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * gcc.c (PATH_SEPARATOR): New macro. From Alex Zatsman. + (process_command): Use it when scanning a path. + + * expr.c (expand_builtin): Cast icode to int for indexing. + + * xm-i386dos.h: New file. + * configure.bat: Use that file. + * gcc.c (EXECUTABLE_SUFFIX): Remove special default for MSDOS. + (putenv): Remove conditionals for MSDOS, since HAVE_PUTENV now defined. + + * c-typeck.c (build_array_ref): Promote after -Wchar-subscripts test. + + * c-decl.c (builtin_function): If traditional and name is user-visible, + set DECL_BUILT_IN_NONANSI. + + * cccp.c (PATH_SEPARATOR): Add default definition. + (main): Use that. + + Sun May 3 08:17:02 1992 Torbjorn Granlund (tege@hal.gnu.ai.mit.edu) + + * pyr.h (FRAME_POINTER_REGNUM): Work around pyr cpp bug. + + * xm-hppa.h (NO_SYS_SIGLIST): Define. + + Sat May 2 15:03:08 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * callc.c (emit_call_1): Restore inhibit_defer_pop after popping args. + + Thu Apr 30 20:00:00 1992 DJ Delorie (dj@ctron.com) + + * configure.bat: Complete rewrite to use Makefile.in. + * Makefile.dos: File deleted. + + Thu Apr 30 23:38:00 1992 Per Bothner (bothner@rtl.cygnus.com) + + * xcoffout.h (DBX_FINISH_SYMBOL): Use DECL_ASSEMBLER_NAME + instead of DECL_NAME when writing out a global symbol. + (Makes a big difference for C++ static class members.) + + Thu Apr 30 23:13:01 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * fold-const.c (fold, comparisons): Don't call omit_one_operand in + a case where the operand isn't really being omitted. + + * combine.c (distribute_notes, case REG_DEAD): Don't write a USE for + a partially-dead register if we already wrote one. + + Thu Apr 30 21:51:29 1992 Tom Wood (wood at dg-rtp.dg.com) + + * Makefile.in (enquire.o, install-common-headers): Make these work + when $(srcdir) is . + + * c-decl.c (init_decl_processing): Use void_ftype_any as the type + for _exit, exit and abort. + + Wed Apr 29 21:42:30 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * genattrtab.c (insn_name_ptr): Define so we could link with + debug_rtx. + + * genattrtab.c (check_attr_test, simplify_test_exp): Copy expression + before setting as unchanging. + (make_canonical): Set result as unchanging after calling + convert_const_symbol_ref. + (evaluate_eq_attr): When returning original expression, set it + as unchanging. + + Wed Apr 29 13:30:33 1992 Michael Meissner (meissner@osf.org) + + * halfpic.c (half_pic_ptr): Allocate space for the NULL byte. + + Wed Apr 29 06:28:35 1992 Ron Guilmette (rfg at ncd.com) + + * dwarfout.c (src_coords_attribute): Don't #ifdef code based on + DWARF_DECL_COORDINATES. + (name_and_src_coords_attributes): Do #ifdef calls to `lookup_filename' + and `src_coords_attribute' based on DWARF_DECL_COORDINATES. Also, + pop out of .debug section temporarily while calling `lookup_filename'. + + Wed Apr 29 02:01:03 1992 Mike Stump (mrs@albert.gnu.ai.mit.edu) + + * Complete another Cygnus <--> FSF merge. + + Tue Apr 28 19:24:52 1992 Mike Stump (mrs at rtl.cygnus.com) + + * cp-init.c (do_friend): Handle overloaded and extern "C" + friends correctly. + + Mon Apr 27 21:04:40 1992 Mike Stump (mrs at rtl.cygnus.com) + + * cp-search.c (build_vbase_vtables_init): Don't set + flag_this_is_variable to -2 when not doing a ctor. + + * cp-class.c (build_vbase_path): Don't unconditionally set + code to be a PLUS_EXPR. + + Mon Apr 27 14:14:08 1992 Mike Stump (mrs at rtl.cygnus.com) + + * cp-decl.c (grokdeclarator): Allow contructors to be friends. + Cannot find anything prohibiting it. + + Mon Apr 27 13:26:20 1992 Mike Stump (mrs at rtl.cygnus.com) + + * cp-init.c (do_friend): bullet proof handling of friends, + fixes problem introduced on Apr 26 18:24:35. + + Sun Apr 26 23:18:24 1992 Mike Stump (mrs at rtl.cygnus.com) + + * cp-call.c (ideal_candidate): Allow one to overload static + member functions without dumping core. + + Sun Apr 26 18:44:57 1992 Jim Wilson (wilson@sphagnum.cygnus.com) + + * cp-tree.c (break_out_calls): Call build1 instead of build for + trees with only one operand to avoid abort in build. + + Sun Apr 26 18:24:35 1992 Mike Stump (mrs at rtl.cygnus.com) + + * cp-init.c (do_friend): Allow extern "C" functions to be + friends. + + Sat Apr 25 02:57:07 1992 Mike Stump (mrs at rtl.cygnus.com) + + * cp-*.[chy]: Fix all pedantic warnings to be pedwarn. + + Sat Apr 25 01:46:50 1992 Mike Stump (mrs at rtl.cygnus.com) + + * cp-tree.c (break_out_calls): Handle NULL_TREE properly. + + Fri Apr 24 23:49:39 1992 Mike Stump (mrs at rtl.cygnus.com) + + * cp-type2.c (store_init_value): Provide an error message + about bad syntax instead of core dumping. + + Fri Apr 24 16:46:03 1992 Mike Stump (mrs at rtl.cygnus.com) + + Fri Apr 24 18:55:45 1992 Chip Salzenberg (chip@tct.com) + + * cp-parse.y (component_decl): Fix small problem to take us + back down to 14 reduce/reduce errors. + + Thu Apr 23 19:48:54 1992 Mike Stump (mrs at rtl.cygnus.com) + + Wed Apr 22 22:47:15 1992 Chip Salzenberg (chip@tct.com) + + * cp-type2.c (readonly_warning_or_error): Eliminate arbitrary + limit of 80 characters per warning message. + + Thu Apr 23 04:14:59 1992 Mike Stump (mrs at rtl.cygnus.com) + + * cp-decl.c (grokdeclarator): Handle const and volatile + member functions properly. + + Tue Apr 28 22:05:05 1992 Niklas Hallqvist (niklas@appli.se) + + * tower-as.h (svr3 support): Generic svr3.h included. + (SELECT_RTX_SECTION): m68k.h's version #undef'd in favour of svr3.h's. + (CPP_PREDEFINES): Overriding svr3.h version. + (STARTFILE_SPEC): Added crtbegin.o. + (ASM_OUTPUT_SOURCE_FILENAME): Added ugly section directives to get + rid of NCR assembler bug. + (ASM_OUTPUT_IDENT): #undef'd svr3.h version. + (NO_{DOLLAR,DOT}_IN_LABEL): Defined. + (ASM_LONG): Defined. + ({INIT,FINI,CONST}_SECTION_ASM_OP): Overrides svr3.h versions. + (CTOR_LIST_{BEGIN,END}): New macros. + (BSS_SECTION_ASM_OP): New macro. + (ASM_OUTPUT_CONSTRUCTOR): New macro. + (ASM_OUTPUT_LABELREF): Redefined svr3.h version. + + * tower.h (LIB_SPEC): Added -shlib support plus crtend.o. + + * configure (m68k-ncr-sysv): Defined xmake_file and tmake_file. + + Tue Apr 28 21:27:10 1992 Michael Meissner (meissner@osf.org) + + * mips.md (floatsidf2, floatsisf2): Fix typo in last change. + + Tue Apr 28 18:21:02 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * objc-actions.c: Include obstack.h, etc. + (util_obstack, util_firstobj): New obstack, and 1st object in it. + (init_objc): Init those two. + (encode_*): Rewrite to use util_obstack, Callers changed. + (handle_class_ref, handle_impent): New subroutines, broken out + from finish_objc so each can use alloca (instead of utlbuf). + (utlbuf): Variable deleted. + + * c-decl.c (init_decl_processing): Treat abort and exit as ANSI. + -traditional no longer affects ANSI builtins; use -fno-builtin. + + * configure: Insert assignment of INSTALL where old one was. + + Tue Apr 28 17:14:57 1992 John F Carr (jfc at Achates.mit.edu) + + * vax.md (cmpdf, cmpsf): Use tstf/tstd if second argument is zero. + (movsi, movhi, movqi): Patterns changed to reflect different + space/time tradeoffs for modern VAXes. + (movstricthi, movstrictqi): New patterns. + (extv, extzv): Use rotl/bicl sequence when possible. + + Tue Apr 28 10:00:25 1992 Michael Meissner (meissner@osf.org) + + * mips-tfile.c (read_line): Make read_line act like the assembler, + and use ';' to separate multiple logical lines. + + * mips.h (MIPS_VERSION): Set Meissner version # to 17. + (MASK_DEBUG_C): Swap meaning of -mdebugc. + (ADDITIONAL_REGISTER_NAMES): Use 'cc' for the floating point status + register, so user asm's can clobber it. Allow $fp for the frame + pointer in addition to fp and $30, and also $sp for the stack + pointer in addition to sp and $29. + + * mips.c (gen_int_relational): Emit faster sequence for NE. + (mips_asm_file_start): Don't call data_section for gcc2_compiled. + + * mips.md (branch define_delay): Specify all of the preconditions + correctly for branch likely (mips2) support. + (floatsidf2): Update dslots_load_total. Support getting the + integer value from memory as well as from an integer register. + Fix the length attribute. + (floatsisf2): Ditto. + (All set from condition code patterns): Swap meaning of -mdebugc, + so that if used, it means support all of the set condition code + patterns as if the machine can do them equally well. If not + -mdebugc, call gen_int_relational to generate an appropriate set + of INSNs. + + * decrose.h (ASM_IDENTIFY_GCC): Define as null on OSF/1. + * encrose.h (ASM_IDENTIFY_GCC): Define as null on OSF/1. + * i386rose.h (ASM_IDENTIFY_GCC): Define as null on OSF/1. + + * decrose.h (CPP_SPEC): If .S files, add an explicit + -ULANGUAGE_C to mimic the OSF GCC 1.39 behavior. + + Mon Apr 27 16:44:30 1992 Tom Wood (wood at dg-rtp.dg.com) + + * dwarf.h (AT_... values): Correct typos present in version 1.0.1 + of the DWARF spec. The values should be unchanged. + + * dwarfout.c (data_member_location_attribute): Use INTEGER_CST. + + * dwarfout.c (data_member_location_attribute): Use TYPE_MODE. + (bit_offset_attribute): Ditto. + + * dwarfout.c (name_attribute): Add the tests back. + + * m88k.h (WEAK_ASM_OP): Override svr4.h. + + Mon Apr 27 15:48:36 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * limits.h: Use _LIMITS_H___, not _LIMITS_H_, to protect contents. + + Mon Apr 27 15:15:25 1992 Michael Meissner (meissner@osf.org) + + * mips.h (MIPS_VERSION): Set Meissner version # to 16. + (delay_type enum): Add DELAY_FCMP for specifing the + c.{eq,lt,le}.{d,s} delay. + (fpsw_register_operand): New declaration. + (gen_int_relational): New declaration. + (pc_or_label_operand): New declaration. + (MASK_DEBUG_C): Use -mdebugc for new relational code. + (REG_CLASS_FROM_LETTER): Use 'z' for fpsw register, not 's' which + is already used. + (EXTRA_CC_MODES): Add CC_REV_FPmode to handle fp comparisons, + which need to be reversed (!=). + (EXTRA_CC_NAMES): Add CC_REV_FP. + (SELECT_CC_MODE): Use SImode for all integer comparisons, + CC_REV_FP for floating point != comparisons. + + * mips.c (internal_test enum): Move and rename the enumeration + used in gen_conditional to make the comparison RTL codes to + something that can be indexed out to top level. + (fpsw_register_operand): New function to return true if the + operand is the FP status register. + (pc_or_label_operand): New function to return true if the operand + is either a label_ref or the pc for if_then_else tests. + (mips_fill_delay_slot): Add support for DELAY_FCMP, the delay + after a floating point comparison is done and it can be tested. + (map_test_to_internal_test): New function to take a RTL code of a + comparison operator, and return the internal_test enumeration. + (gen_int_relational): New function to generate the appropriate + INSNS for comparing two integers for either branches, or the set + from condition code insns. + (gen_conditional_branch): Rewrite to not use the CISC condition + code register CC0, but instead generate the appropriate INSNs so + that the test can be scheduled independely of the branch. + (override_options): Use 'z' for the fpsw register, not 's'. Only + allow the fp comparison condition codes in the fpsw register. Do + not allow non float or int things in FP registers, even if + -mdebugh. Don't allow ints in the fpsw. + + * mips.md (various): Rewrite comparisons and branches so that we + do not use CC0, but instead put the comparison in a pseudo and + generate the appropriate branch instructions directly. This + eliminates calls to the various b macros provided by the + assembler. Change the type of integer comparisons from the + various CCxx modes used to SImode. Make fp != use CC_REV_FPmode. + (mode attribute): Add FPSW mode for floating compare. + (fp_comp): New functional unit for comparing fp values. + (divmodsi4): No longer use -mdebugc to turn off divmodsi4. + (divsi3): Ditto. + (modsi3): Ditto. + (udivmodsi4): No longer use -mdebugc to turn off udivmodsi4. + (udivsi3): Ditto. + (umodsi3): Ditto. + + * mips-gn5.h: Rename from mips-gnews5.h for MSDOS. + * mips-n5.h: Rename from mips-news5.h. + * xm-mipsbsdnews.h: Rename from xm-mipsnbsd.h. + + * configure (mips-sony*): Handle the above changes. + + * README-mips (whole file): Remove bogus patches, and update with + some common warnings about the MIPS. + + Mon Apr 27 12:41:21 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * unroll.c (find_splittable_givs): Don't split a giv combined with + a giv that was not reduced. + + * c-parse.y (primary): Clear the TREE_USED flag of a block tree + put in a BIND_EXPR. + * print-tree.c (print_node): Print the block operand of a BIND_EXPR. + + * flow.c (find_basic_blocks): Assume MEM source in jump insn makes + it an indirect jump. + + * collect2.c (strip_flag, strip_file_name): New variables. + (main): Don't pass -s to the first ld call. Pass it to the second + ld call, or else run strip. + + * Makefile.in (bootstrap): Only build C compiler for stage1. + + * sparc.h (GO_IF_LEGITIMATE_ADDRESS): Rewrite to accept SUBREGs. + + * combine.c (force_to_mode): Correctly form mask from BITS. + + * Makefile.in (bootstrap): Fix a typo (\n between b and ootstrap). + + Sun Apr 26 14:14:23 1992 Ron Guilmette (rfg at ncd.com) + + * getattr.c, genattrtab.c, gencodes.c, genconfig.c, genemit.c, + genextract.c, genflags.c, genoutput.c, genpeep.c, genrecog.c (main): + Move nested extern declaration of `read_rtx' out to file-scope. + + Sun Apr 26 21:41:33 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * Makefile.in (varasm.o): Includes defaults.h. + + Sun Apr 26 21:15:30 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * enquire.c (f_rep, f_define): Handle NO_LONG_DOUBLE_IO. + (f_define): Print defn of union __convert_long_double, just once, + with #ifndef to protect it. + (fake_f_define): New function. + + Sat Apr 25 15:04:49 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * stmt.c (expand_end_case): Test DI index against range before casesi. + Don't truncate before calling do_tablejump. + Use expand_expr to turn RANGE into rtl. + * expr.c (do_tablejump): Convert to Pmode after testing vs range. + + * stmt.c (expand_end_case): Delete test default_label != 0; always is. + + * configure (i386-ibm-aix): Set install_with_cp. + + Fri Apr 24 21:32:38 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * xm-spcv4.h: Renamrd from xm-sparcv4.h. + * configure: Changed accordingly. + + * Makefile.in (unprotoize.o): Leave unprotoize.c around. + + * c-common.c (decl_attributes): Change warnings to errors. + + Fri Apr 24 11:17:53 1992 Ron Guilmette (rfg at ncd.com) + + * dwarf.h: Added copyleft. + Revised to use enumerators instead of #defines. + Updated to conform to version 1.0.1 of the DWARF spec. + Added implementation-defined fundamental type codes for GCC + mode-specific types. + + * dwarfout.c: Include defaults.h. + (getpwd): Declare as `extern'. + (BITFIELD_OFFSET_BITS, BITFIELD_OFFSET_UNITS, + BITFIELD_OFFSET_WORDS_IN_UNITS): Unnecessary definitions deleted. + (ASM_BYTE_OP, PUSHSECTION_ASM_OP, POPSECTION_ASM_OP): Delete + leading tabs from definitions. + (PUSHSECTION_FORMAT): Add leading tab to definition. + (*_LABEL): Changed to all start with `.L' to internalize these + symbols for *all* svr4 assmeblers (including sparc). + (ASM_OUTPUT_POP_SECTION): Add leading tab. + (ASM_OUTPUT_DWARF_TAG, ASM_OUTPUT_DWARF_ATTRIBUTE, + ASM_OUTPUT_DWARF_STACK_OP, ASM_OUTPUT_DWARF_FUND_TYPE, + ASM_OUTPUT_DWARF_FMT_BYTE, ASM_OUTPUT_DWARF_TYPE_MODIFIER): Print + DWARF comments only if flag_verbose_asm set. + (ASM_OUTPUT_ASCII): Moved to defaults.h + (tag_name): Renamed `dwarf_tag_name' to avoid possible conflicts. + (dwarf_tag_name): Updated for version 1.0.1 DWARF spec. + (attribute_name): Renamed `dwarf_attr_name' to avert conflicts. + (dwarf_attr_name): Updated for version 1.0.1 DWARF spec. + (stack_op_name): Renamed `dwarf_stack_op_name' to avert conflicts. + (format_byte_name): Renamed `dwarf_fmt_byte_name' to avert conflicts. + (fundamental_type_name): Renamed `dwarf_fund_type_name' to avoid + possible conflicts. + (dwarf_fund_type_name): Added support for implementation-defined + GCC mode specific fundamental types codes (to support new `mode' + attribute). + (data_member_location_attribute): Rewritten to avoid major lossage + primarily for little-endian targets. + (location_or_const_value_attribute): Fixed comments and removed + spurious code. + (name_attribute): Removed test for NULL name (now done in + `name_and_src_coords_attributes'). + (byte_size_attribute): Fixed to get size from DECL_BIT_FIELD_TYPE + for bit-fields. + (bit_offset_attribute): Rewritten to avoid major lossage primarily + for little-endian targets. + (src_coords_attribute): GNU-specific extension added. + (name_and_src_coords_attributes): New function. + (output_entry_point_die, output_formal_parameter_die, + output_global_subroutine_die, output_global_variable_die, + output_inline_subroutine_die, output_label_die, + output_local_variable_die, output_member_die, + output_local_subroutine_die, output_typedef_die): Call + `name_and_src_coords_attributes' rather than `name_attribute' for + all potentially-named declarations. + (output_global_subroutine_die, output_inline_subroutine_die, + output_local_subroutine_die, dwarfout_file_scope_decl): Use + DECL_ASSEMBLER_NAME rather than DECL_NAME when referencing + assembly level names (e.g. in AT_low_pc attributes). + (output_type): Revised to produce DWARF info for C++ member functions + even for classes with no constructors & destructors. + + * flags.h (flag_verbose_asm): Option flag added. + * toplev.c (flag_verbose_asm): Option flag added. + + * defaults.h: New file. + * varasm.c: Include defaults.h. + (ASM_OUTPUT_ASCII): Deleted. + + * c-common.c (decl_attributes): Call `type_for_mode' rather than + `type_for_size'. Also, `break' after a matching mode is found. + + * 3b1.h (ASM_OUTPUT_ASCII): Tab before ASCII_DATA_ASM_OP. + * amix.h (ASM_OUTPUT_CASE_END): Tab before SET_ASM_OP. + (ASM_OUTPUT_ASCII) Tab before BYTE_ASM_OP. + * i860b.h (ASM_OUTPUT_ASCII): Tab before ASCII_DATA_ASM_OP. + * i860v3.h (ASM_OUTPUT_ASCII): Tab before BYTE_ASM_OP. + * sparcv4.h (*_ASM_OP): Delete the initial tabs. + + * assert.h: Modified to treat source line numbers as `unsigned'. + + * Makefile.in (test-protoize): New target. + + * svr4.h (WEAK_ASM_OP): Default svr4 definition added. + (ASM_DECLARE_FUNCTION_SIZE): Use `assemble_name' to output + generated internal label. + + Thu Apr 23 11:31:58 1992 Jim Wilson (wilson@sphagnum.cygnus.com) + + * optabs.c (emit_libcall_block): Correct code which determines + whether it is safe to emit an insn setting a pseudo before the block. + + Thu Apr 23 18:13:08 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * i386.md (sleu): Finish Apr 21 change. + + Thu Apr 23 14:15:05 1992 Michael Meissner (meissner@osf.org) + + * Makefile.in (enquire.o): Delete enquire.c from the current + directory before moving it in from the source directory, unless + the current directory is the same as the source directory. This + occurs if the user keeps GCC under source control, like RCS. + (install-common-headers): Ditto for byteorder.h. + + Thu Apr 23 12:39:36 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * amix.h (ASM_OUTPUT_CASE_END): Add missing \. + + Thu Apr 23 07:14:38 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * cse.c (simplify_binary_operation, case MINUS): Don't do any + of the simplifications for IEEE floating-point. + + Wed Apr 22 23:20:59 1992 Mike Stump (mrs@albert.gnu.ai.mit.edu) + + Tue Apr 21 02:21:42 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-method.c (build_overload_value): Handle function names as + constant expressions for template arguments. Also, make double + values work again as template arguments. + + Mon Apr 20 17:08:17 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-call.c (ideal_candidate): remove incorrect error message about + ``ambiguous request for function from distinct base classes of + type'' when base and parent are switched. + + Mon Apr 20 14:14:35 1992 Mike Stump (mrs@rtl.cygnus.com) + + * Makefile.in: Now expect 15 reduce/reduce conflicts, instead of 14. + + Mon Mar 16 14:02:09 1992 Chip Salzenberg (chip at tct.com) + + * cp-parse.y (maybe_attributes, attribute_list): clone + from c-parse.y. + cp-parse.y: call decl_attributes between start_decl and + finish_decl, and after grokfield. + + Mon Apr 20 09:21:00 1992 Jim Wilson (wilson@sphagnum.cygnus.com) + + * cp-tree.h (break_out_calls): Declare. + + Mon Apr 20 08:29:16 1992 Michael Tiemann (tiemann@cygnus.com) + + * cp-tree.c (break_out_calls): New function. + (break_out_cleanups): Added comment. + + * cp-typeck.c (build_modify_expr): Call `break_out_calls' instead of + `copy_to_permanent'. + + Mon Apr 20 06:29:16 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-type2.c (my_friendly_abort): New function, please see + Rational there. + + * cp-*.[chy]: Change all calls from abort to my_friendly_abort. + + Mon Apr 20 05:45:08 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-cvt.c (build_up_reference): Fix a latent const problem. + + Mon Apr 20 03:08:12 1992 Michael Tiemann (tiemann@cygnus.com) + + * cp-decl.c (pop_from_top_level): Deleted duplicate code in C_C_D + restoration. + + * cp-call.c (build_method_call): Call `error_with_aggr_type' with + correct number of arguments. + + Sun Apr 19 18:39:25 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-class.c (finish_struct): Only provide a warning about + non-virtual destructors if the user asks for -Wall. + + Sun Apr 19 17:36:16 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-typeck.c (build_modify_expr): Make a deep copy of lhs, as + expr.c expects to be able to preexpand_calls on the conditional + parts without insuring that it would even be legal to do so. + + * cp-tree.c (make_deep_copy): Fix comment. + + Fri Apr 17 04:55:18 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-cvt.c (convert_pointer_to): Provide the user with a meaningful + error message instead of a core dump when dealing with bad syntax. + + * cp-typeck.c (build_binary_op): Make error message on undefined + operator call more readable. + + * cp-decl.c (grok_reference_init): Handle T& = const T& + error messages. + + Thu Apr 16 18:59:15 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-typeck.c (convert_arguments): Disable code that auto converted + functions and methods to pointers and left them that way without error. + + Thu Apr 16 17:35:13 1992 Mike Stump (mrs@rtl.cygnus.com) + + Sat Apr 4 22:28:23 1992 Gerald Baumgartner (gb at cs.purdue.edu) + + * cp-decl.c (finish_decl): Call `abstract_virtuals_error' + when the return type of a method is an abstract class. + + * cp-type2.c (abstract_virtuals_error): Print error message + for an invalid method declaration. + + Thu Apr 16 16:18:35 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-decl2.c (lang_decode_option): Handle import by ignoring it. + + Wed Apr 22 19:46:44 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * objc-actions.c (synth_id_with_class_suffix, finish_class): + Don't use utlbuf; alloca a buffer. + (forward_declare_categories): Use build_decl directly since + create_builtin_decl wants a string, not an id. + + * Makefile.in (STAGESTUFF): Add USE_COLLECT2. + + * dbxout.c (dbxout_symbol): Clean up last change. + + Wed Apr 22 17:06:16 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * rs6000.c (gpc_reg_operand): Renamed from gen_reg_operand. + * rs6000.h (PREDICATE_CODES): Likewise. + * rs6000.md: Likewise. + + * a29k.c (gpc_reg*_operand): Renamed from gen_reg*_operand. + * a29k.h (PREDICATE_CODES): Likewise. + * a29k.md: Likewise. + + * romp.c (output_fpop): Extend workaround for RT FP codegen bug. + + Wed Apr 22 06:20:09 1992 Tom Wood (wood at dg-rtp.dg.com) + + * fold-const.c (fold, comparison cases): Use omit_one_operand to + yield a simplified result to avoid loosing a side-effect. + + Tue Apr 21 13:19:42 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * dbxout.c (dbxout_symbol): For TYPE_DECL, always make requisite tag + one way or another even if !have_used_extensions. + + * configure: Specifically detect unrecognized options. + + Tue Apr 21 08:16:05 1992 Tom Wood (wood at dg-rtp.dg.com) + + * c-convert.c (convert_to_integer): Don't distribute a truncation + down past an ABS_EXPR. + + * m88k.md (bxx insn): Choose bb0 over bb1 if the branch is likely + to fall-through (m88110 optimization). + * m88k.c (mostly_false_jump): New function. + + * m88k.h (INIT_SECTION_ASM_OP): Define only for svr3 and svr4 targets. + + * m88k.c (output_call): Use the insn address of the sequence. + * m88k.h (ADJUST_INSN_LENGTH): Account for space added at barriers + due to ASM_OUTPUT_ALIGN_CODE. + + Tue Apr 21 07:30:46 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * jump.c (mark_jump_label, case MEM): New case to look for label + in a constant-pool entry. + + Tue Apr 21 00:41:39 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * reg-stack.c (compare_for_stack_reg): link cc0 user and setter + before separating them. + + * reorg.c (link_cc0_insns): Move function from here - + * emit-rtl.c (link_cc0_insns): to here. + + * i386.h (TARGET_IEEE_FP): New macro. + (TARGET_SWITCHES): Add switches for ieee floating point support. + (EXTRA_CC_MODES,EXTRA_CC_NAMES): Add CCFPEQmode. + (SELECT_CC_MODE): Select CCFPEQmode for FP equality comparisons. + (i386_compare_gen*,i386_compare_op*): Declare new variables to + generate comparisons from within branch and sCC insns. + (RTX_COSTS): Fix argument name typo. + + * i386.c (i386_compare_gen*,i386_compare_op*): Define variables here. + (notice_update_cc): Notice if a comparison involves FP values. + (output_float_compare): Add support for "unordered" compare. + Use output_fp_cc0_set to set flags after a compare. + (output_fp_cc0_set): New function. + + * i386.md (tstM,cmpM): New expanders. Don't generate RTL; just + save data for when cc0 user is generated. + (bCOND,sCOND): New expanders. Generate the compare/test as well + as the bCOND or sCOND. + + (tstsf,tstdf): Disable patterns if generating ieee compliant code. + (tstsf,tstdf,cmpsf,cmpdf): Use output_fp_cc0_set to set flags + after test. + Don't change cc_status here: that won't work with REG_CC_SETTER + and REG_CC_USER. + + (all COMPAREs): Use CCmode as mode of a COMPARE. + + Mon Apr 20 11:17:51 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * limits.h (LONG_LONG_MIN, LONG_LONG_MAX, ULONG_LONG_MAX): New macros. + + * configure: Clear out_file before the big case, like tm_file, etc. + + * expr.c (expand_expr, case LABEL_DECL): Handle label from outer fcn. + + Mon Apr 20 10:17:49 1992 Tom Wood (wood at dg-rtp.dg.com) + + * x-m88kluna: Delete. + * x-m88kv3: Renamed from x-m88k. + * configure (m88k-*): Rearrange. + + Mon Apr 20 21:29:00 1992 (Eric Youngdale at youngdale@v6550c.nrl.navy.mil) + + * config-gcc.com: Generate libgcc2.list from Makefile.in + * make-l2.com: Use libgcc2.list; supply gcc version number to gas. + + * config-gacc.com: Generate linker options files from Makefile.in + + * make-cc1.com: Use said linker options files instead of static + list of files. + * make-cc1.com: Handle errors better. + + Mon Apr 20 10:05:34 1992 Michael Meissner (meissner@osf.org) + + * mips.md (divmodsi4, udivmodsi4): Remove unneeded PARALLEL. Patch + from Richard Kenner. + + Mon Apr 20 08:38:26 1992 Tom Wood (wood at dg-rtp.dg.com) + + * expr.c (expand_expr, case CONSTRUCTOR): For static CONSTRUCTOR, + require a valid memory address only if modifier does. + + Sun Apr 19 15:09:01 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * genemit.c (gen_insn): Mode of SCRATCH must match in clobber lists. + + * sched.c (add_dependence, remove_dependence): Moved from rtl.c. + * rtl.c: Functions deleted here. + + * Make installation of collect2 automatic. + * configure: Define use_collect2 for all BSD and Mach and HP/UX + configurations, plus the ones below, and a few others. + * t-decrose, t-decstatn, t-encrose, t-i386rose, t-mips, t-next: + (EXTRA_PROGRAMS): Deleted. + * t-apollo68, t-convex, t-dpx2, t-rs6000: Files deleted. + + * libgcc1.c (nongcc_SI_type): Renamed from SItype. + + * recog.c (constrain_operands): Check only earlyclobbers that are REGs. + + * m68k.h (TRANSFER_FROM_TRAMPOLINE): Delete comma in globalize cmd. + + * m68k.md (movhi): Don't use switch_table_difference_label_flag + except in ports that need it. (Again!) + + Sun Apr 19 14:06:59 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * sched.c (sched_analyze_2): Add missing comment close. + + * rtl.c (add_dependence): Make next point to last insn with + SCHED_GROUP_P set, not after the last insn with the bit set. + + Sun Apr 19 06:06:03 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * genextract.c (walk_rtx): Fix typo in vector case. + + * hppa.h (RTX_COSTS): Add new argument OUTER_CODE. + + * Makefile.in (compare, compare3): Change $file to $$file. + + * romp.h (CONST_CONSTS): Clean up formatting of definition. + + * rs6000.md (extzv): Correct when we can use andi[lu]. + + Sat Apr 18 21:56:20 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * sparc.md (ashldi3): Compact operand numbers. + + From Jeffrey Law: + * sparc.md (ldd, std peepholes): New peepholes to recognize cases + where two ld (or st) insns could be replaced by a single ldd or std. + * sparc.c (registers_ok_for_ldd): New function. Return true if the + given register pair is suitable for an ldd or std instruction. + (memory_ok_for_ldd): Likewise, but for memory locations. + + Sat Apr 18 17:22:32 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * c-lex.c (skip_white_space): Warn only for first carriage return. + + Sat Apr 18 10:08:45 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * genemit.c (struct clobber_ent): New structure. + (gen_insn): See if the clobbers required to be added were seen + for another insn. + (output_add_clobbers): Write case statements for all insn codes + using a particular clobber pattern. + + * cse.c (mention_regs): Always retun a value. + + * rs6000.md (call): Compact operand numbers. + + * genextract.c: Now includes insn-config.h. + (struct extraction, struct code_ptr): New structures. + (gen_insn): Record what extractions are needed and compare with + those for previous insns. + (mark_operand_seen): Function deleted. + (walk_rtx): Use strings as path and just record; don't write. + (print_path): Use strings for paths. + (copystr): New function. + (main): Write out all extractions here. + * Makefile.in (genextract.o): Includes insn-config.h. + + * hppa*.h: Change references from hp800* files to hppa*. + + * rs6000.md (lshrdi3, ashrdi3): Fix typos. + + * rs6000.md (extzv): Correctly install last change. + + Sat Apr 18 12:37:54 1992 John F Carr (jfc at Achates.mit.edu) + + * expmed.c (store_bit_field): Storing into a bitfield in memory + which is the size of a standard machine mode can be done with a + simple move instruction. + + * c-lex.c (skip_white_space): carriage return (^M) is whitespace, + but warn about ^M if pedantic. + + * cse.c (rtx_cost): New argument OUTER_CODE, the rtx code of the + expression in which the rtx argument is contained. + * expmed.c (init_expmed): Pass second argument to rtx_cost. + * optabs.c (expand_binop, expand_twoval_binop, emit_cmp_insn): Likewise. + * loop.c (init_loop, general_induction_var): Likewise. + * vax.c (vax_rtx_cost, vax_address_cost): New functions. + * vax.h (CONST_COSTS, RTX_COSTS, ADDRESS_COST): Call these + functions. + * romp.h (CONST_COSTS): Give constants different costs depending + on whether they can fit into a 2 byte instruction, a 4 byte + instruction, or would require insn splitting to use. + * i386.h (CONST_COSTS, RTX_COSTS): Move PLUS case to RTX_COSTS. + * m68k.h (CONST_COSTS): Constant in range -254..-136 is only cheap + in a move insn, not as an operand to some other instruction. + * config/*.h: Update machine descriptions to define CONST_COSTS + and RTX_COSTS macros with 3 arguments. + + Fri Apr 17 11:14:02 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * reload.c (safe_from_earlyclobber): New function. + * recog.c (constrain_operands): Verify that earlyclobber + operands don't conflict with inputs. + + * combine.c (subst, case SUBREG): Don't fold paradoxical SUBREGs + of constants. + + * cse.c (fold_rtx, case SUBREG): Extend previous change so it + folds widened operations with one operand a constant. + + * expr.c (safe_from_p, case BIND_EXPR): Only look at operand 1. + + * cse.c (fold_rtx, case SUBREG): Don't fold paradoxical SUBREGs. + Instead, when we have a narrowing SUBREG, see if it is narrowing + the result of a widened arithmetic operation. + + Fri Apr 17 09:16:56 1992 Charles Hannum (mycroft@hal.gnu.ai.mit.edu) + + * Makefile.in (install-dir): Don't use '-' prefix on continuation line. + + Fri Apr 17 06:52:00 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * toplev.c (rest_of_compilation): + If -Wreturn-type, don't stop before jump.c. + + * calls.c (expand_call): Delete unused arg MODIFIER. + * expr.c: Arg deleted from calls (those which had it). + + * ns32k.c (print_operand_address): Handle UTEK_ASM. + (print_operand): Handle NO_IMMEDIATE_PREFIX_IF_SYMBOLIC. + Abort if must get fp number as bits but cannot do so. + * ns32k.h (TRAMPOLINE_TEMPLATE): Use PUT_ABSOLUTE_PREFIX. + * ns32k.md (call, call_value): Handle ENCORE_ASM. + * encore.h (PRINT_OPERAND): Just call print_operand. + (CALL_MEMREF_IMPLICIT): Defined. + + * config.sub: encore implies bsd, not sysv. + + * stmt.c (expand_expr_stmt): Handle reference of volatile BLKmode. + + * vax.md (indirect_jump): Delete the extra condition. + + * configure (...-hpux): Set install_with_cp. + + * jump.c (delete_insn): After a label, go past other deleted labels. + + * m68k.md (movhi): Don't use switch_table_difference_label_flag + except in ports that need it. + + * stmt.c (warn_if_unused_value): Don't warn for constant after comma. + Don't warn for volatile decl or ref. + + * c-typeck.c (build_unary_op): ++ on void * warns if -Wpointer-arith. + + Thu Apr 16 22:56:20 1992 Michael Meissner (meissner@osf.org) + + * mips.h (enum block_move_type): New enumeration for classing what + type of block move is used when splitting the last store off. + (RTX_COSTS): Don't use -mdebugd to set multiply costs to 2. + + * mips.c (output_movstrsi): Take an additional argument to determine + whether this block move is a normal block move, or one that has been + split. For the split block moves, there are two parts -- the first + part is everything but the last store, and the second part is the + last store, suitable to fill a delay slot. + + * mips.md (all define_splits): Don't do any define_split if + -mdebugd. + (movstrsi_internal*): Add support to split block moves into two + pieces, one that is everything except for the last store, and the + second piece, which is the last store that can fill a delay slot. + + Thu Apr 16 21:52:59 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * x-rs6k-mach: New file. + * configure (rs6000-*-mach): Use it. + + Thu Apr 16 21:52:17 1992 John F Carr (jfc at Achates.mit.edu) + + * cse.c (cse_end_of_basic_block): Fix test for infinite loop. + + Thu Apr 16 21:50:38 1992 Jim Wilson (wilson@sphagnum.cygnus.com) + + * rs6000.h (bss_section): Delete. No longer needed. + + * a29k.c (print_operand, case 'F'): Always emit insn to fill empty + delay slot. + + Thu Apr 16 18:45:41 1992 Tom Wood (wood at dg-rtp.dg.com) + + * cse.c (simplify_ternary_operation): Correctly sign-extend result. + + Thu Apr 16 18:43:55 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * objc-actions.c: Rename OBJC_NONUNIQUE_SELECTORS to + OBJC_SELECTORS_WITHOUT_LABELS. + + * c-decl.c (duplicate_decls): Allow extern vs extern inline. + + * c-parse.y (parmlist_or_identifiers_1): Use parmlist_1. + * c-decl.c (get_parm_info): Treat forward parm decls like nonparm + decls. + + * m68k.md (movhi before dispatch table): + Set switch_table_difference_label_flag. + * 3b1.h, amix.h, m68ksgs.h (ASM_OUTPUT_CASE_END): Test that flag. + Declare the flag. + + * m68k.c (output_function_prologue, print_operand_address): Add + HPUX_ASM conds. + + * mips.c (output_block_move): If we get a case we can't handle, + don't print anything--just abort, because that implies a bug. + + * c-decl.c (c_decode_option): -ansi sets flag_no_nonansi_builtin, + not flag_no_builtin. + (init_decl_processing): Check flag_no_nonansi_builtin for alloca, etc. + + * dbxout.c (dbxout_symbol): Make pointer, not reference, + when variable's address is in a register. + + * c-decl.c (c_decode_option): Ignore -Wimport, -Wno-import. + + Thu Apr 16 16:17:13 1992 Mike Stump (mrs@mole.gnu.ai.mit.edu) + + * merge in Cygnus changes... + + Thu Apr 16 12:23:06 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-call.c (build_method_call): propagate const around to avoid an + incorrect error message. This type of fix may now be necessary in + other parts of the compiler. This solves all but one known const + problems. + + Wed Apr 15 14:18:27 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-type2.c (readonly_warning_or_error): because the compiler + is now warning about const alot more, for a release or two, + lets just warn about const problems, just in case it is a compiler + problem and not a user problem. + + * cp-cvt.c (build_up_reference): Lets get tougher on const problems + on COMPONENT_REFs. + + Wed Apr 15 11:59:42 1992 Jim Wilson (wilson@sphagnum.cygnus.com) + + * cp-decl.c (finish_function): Check for any debug info enabled, + not just DBX_DEBUG. + + Wed Apr 15 10:03:36 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-cvt.c (build_up_reference): Propagate const and volatile + down into the type so error checking works better. + + Tue Apr 14 11:44:32 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-decl.c (start_decl): Shouldn't use flag_this_is_variable + to make what this points to const, but I don't have the heart + to do it right now. + + * cp-decl2.c (grokclassfn): Don't use flag_this_is_variable + to make what this points to const. + + * cp-typeck.c (convert_arguments): Let build_up_reference handle + const errors correctly. Removes April 10 change. + + * cp-cvt.c (build_up_reference): Don't let people subvert const + when passing const argements to non-const functions. + + * cp-tree.c (build_cplus_method_type): Don't use + flag_this_is_variable to make what this points to const. + + From Wed Apr 1 12:00:59 1992 Chip Salzenberg (chip at tct.com) + + * cp-class.c (import_export_vtable): New function to set + TREE_PUBLIC and/or TREE_EXTERNAL on vtables. + (build_vtable): Use it. + (prepare_fresh_vtable): Use it. + + * cp-decl.c (finish_decl): Don't assume that TREE_PUBLIC means + "exported"; it can mean "imported". Decide with TREE_EXTERNAL. + (finish_function): Ditto. + * cp-decl2.c (write_vtable_entries): Ditto. + (finish_vtable_typedecl): Ditto. + (finish_vtable_vardecl): Ditto. + (finish_file): Ditto. + + * cp-lex.c (set_vardecl_interface_info): Public objects always + have TREE_PUBLIC, whether exported or imported. + * cp-pt.c (instantiate_member_templates): Ditto. + + + Fri Apr 10 21:44:15 1992 Per Bothner (bothner@cygnus.com) + + * cp-method.c (build_overload_name): Mangle 'signed char' + as 'Sc' (i.e. differently from 'char'!). + + Fri Apr 10 17:38:04 1992 Mike Stump (mrs@cygnus.com) + + * cp-typeck.c (convert_arguments): don't allow people to wipe const. + + Thu Apr 9 18:28:36 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-tree.h: Add entry for $vb and $vf so that NO_DOLLAR_IN_LABEL + works. + * cp-class.c (finish_struct): Use the new macros from cp-tree.h. + * cp-tree.c (layout_basetypes): Use the new macros from cp-tree.h. + + Thu Apr 9 02:11:01 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-typeck.c (build_function_call_real): Merge in a change made to + the C front end into the C++ front end to handle volatile functions. + + Thu Apr 9 03:45:03 1992 Mark Eichin (eichin at cygnus.com) + + * cp-class.c (finish_struct): sanity check before calling popclass. + If we're already hosed due to previous parse errors (specifically, + we're not inside a class anymore) just report an error rather than + crashing in popclass (if there wasn't a previous parse error, as the + message suggests, we should get reports; this closes gcc/p0000525.) + + Wed Apr 8 08:56:49 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-decl.c (grokdeclarator): Fix an eichin bug introduced seconds + ago. Shame, he didn't put: + + Workaround for p869: + 1) grokdeclarator (around cp-decl.c:7462) is using popclass(1) + uses popclass(1) to close the pushclass(3) done by + build_push_scope; however, it's coming around another time and + popping all the way out, which leads to the core dump when + do_friend is called from global scope (do_friend uses + current_class_name to figure out whose friendship it is + bestowing.) Current workaround: if (friendp) don't allow + popping all the way out. We still need to figure out how to + make sure it only gets called the *right* time; we also need + to figure out if the correct scope is being used, but that's a + matter of regression testing. + + into a ChangeLog entry. + + Wed Apr 8 01:10:44 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-decl.c: Cleanup binding_levels_sane related code. Deleted + argument, and changed to void type. Removed extraneous asserts. + + * cp-parse.y: Add fourth parameter to all finish_decl calls. + Defaulted the guess to 0. + * cp-decl.c: consistently use #if on all PARANOIDs. + + Wed Apr 15 14:00:14 1992 Michael Meissner (meissner@osf.org) + + * mips.md (movstrsi_internal): Add '&' constraint on clobbers. + + * mips.c (output_movstrsi): If one of our temporary registers is + used as an address register, don't use it and emit a warning. This + is a temporary measure. + + Wed Apr 15 09:04:22 1992 Richard M. Stallman (rms at lyssenko) + + * xm-ns32k.h (memcpy, memcmp, memset): New macro definitions. + * rtl.c (gcc_memset): New function. + + Wed Apr 15 09:03:28 1992 Tom Wood (wood at dg-rtp.dg.com) + + * m88k.md (umulsidi3): Define for m88110. + (unit attribute): Define. + + * x-m88kdgux (INSTALL_HEADERS): Define as empty. + + Tue Apr 14 13:28:11 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * c-lex.c (yylex): When warn_traditional, don't abort for harmless + type differences. Instead warn of possible problems on other systems. + + * rtl.c (add_dependence): Skip notes when HAVE_cc0. + * sched.c (sched_analyze_2): Likewise. + + * sparc.md (movdf-1): Delete special case for moving 0.0 to integer + registers; it resulted in poor code. + (fix_truncdfsi2+1): Add patterns to optimize float->fix and + float->fix->float conversions. + * sparc.c (output_move_double): Clean up ldd/std code. Don't emit + ldd/std for obviously unaligned address even when TARGET_HOPE_ALIGN. + (output_fp_move_double): Call output_move_double for MEM cases. + It is not safe to assume double reg addresses are always aligned. + + Tue Apr 14 07:55:47 1992 Torbjorn Granlund (tege@hal.gnu.ai.mit.edu) + + * *hp800*, *hp700*: Rename to *hppa* and *hppa1.1*, respectively. + * config.sub: Recognize PA model numbers for PA 1.0 and 1.1. + Disable "hppa" with no model number. + * configure: Update for new PA file names and basic_machine names. + * README-PA-HPUX: New name for README-PA-RISC, with some corrections. + + Tue Apr 14 05:46:37 1992 Tom Wood (wood at dg-rtp.dg.com) + + * Makefile.in ("if" and "["): Romp, 4.3 BSD, and Ultirx systems + fail when the condition is false. Change troublesome instances to + either use "case" or use '-' as a prefix to the compilation rule. + + Mon Apr 13 18:20:56 1992 Mike Stump (mrs@cygnus.com) + + * dwarfout.c: Add default definition for ASM_OUTPUT_ASCII + as that is what varasm.c does now. This really maybe should go + into a file like tree.h or some machine independant file, for + maintainability. + + Mon Apr 13 18:16:32 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * sun3.h, sparc.h (LINK_SPEC): Change nostdlib to !nostdlib. + + Mon Apr 13 07:17:36 1992 John F Carr (jfc at Achates.mit.edu) + + * rs6000.md (extzv): Generate andi[ul] when practical. + + Mon Apr 13 07:17:36 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * cse.c (rtx_cost, case SUBREG): If modes can't be tied, make + expensive. + (cse_insn): Make extra entries when DEST is a multi-word SUBREG + as long as it is the same number of words as its inner REG. + + * emit-rtl.c (gen_lowpart_common): Handle casting integer to + float and vice versa. + + * emit-rtl.c (gen_lowpart_common): Rework code to truncate a + constant so we don't convert negative values into positive values; + use same code as in simplify_binary_operation in cse. + + Mon Apr 13 07:16:56 1992 Richard M. Stallman (rms at mole.gnu.ai.mit.edu) + + * cccp.c (handle_directive): When find quote during copying, + give bp as limit arg in skip_quoted_string. + When find \ while copying, copy next char without special handling. + + Mon Apr 13 06:57:18 1992 Tom Wood (wood at dg-rtp.dg.com) + + * m88kv3.h (CTOR_LIST_BEGIN): Avoid complex #if. + + * tree.h (saved_insns): Make this a union holding an rtx or an int. + (DECL_FIELD_SIZE): New macro for overloaded uses of DECL_FRAME_SIZE. + * c-decl.c (finish_struct): Use DECL_FIELD_SIZE for bitfields. + * cp-class.c (finish_struct): Ditto. + * objc-actions.c (objc_copy_list, encode_field_decl): Ditto. + * stor-layout.c (layout_decl): Ditto. + + Sun Apr 12 17:46:30 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * expr.c (expand_builtin, case SQRT): Don't defer popping args on + function calls, as the call might be deleted. + + * i386.c (print_operand): Delete references to unused codes. + Abort if an unrecognized code is seen. + + * i386.md (bit opcode recognizers): Accept starting bit numbers + that are constants but not CONST_INT. + (QI/HI register bit test): Delete. + (SImode bit test): Don't accept CONST_INT starting bit number. + + Sun Apr 12 17:05:25 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * rs6000.h (ADDITIONAL_REGISTER_NAMES): Add "cc" as alias for cr0. + + * cse.c (equiv_constant): See if a MEM is foldable or has a + constant equivalent. + + * expr.c (store_constructor): If building a static constructor + into a register, start out by zeroing the register so we can + constant-fold the constructor to a single constant. + (expand_expr, case CONSTRUCTOR): Don't write constant objects + into memory if the target is a register. + (expand_expr, case *_REF): Simplify getting field or array + entry from a CONSTRUCTOR. + Don't use value of const array unless -O. + + Sun Apr 12 14:15:33 1992 Richard Stallman (rms at mole.gnu.ai.mit.edu) + + * Makefile.in (compare, compare3): New targets. + (mostlyclean): Delete temporary files made by those targets. + + * stmt.c (expand_asm_operands): Ignore `cc' as clobbered reg if name + not known. + * varasm.c (decode_reg_name): Ret -3 if `cc' not recognized. + (make_decl_rtl): Understand -3 as value. + + * configure (i386-sequent-bsd*): Use collect2. + + Sun Apr 12 13:28:00 1992 Niklas Hallqvist (niklas@appli.se) + + * configure: Correctly interpret use_collect2. + + Sun Apr 12 10:34:58 1992 Tom Wood (wood at dg-rtp.dg.com) + + * c-typeck.c (digest_init): Use INIT to pass to convert_for_assignment + for a raw constructor. + + * fold-const.c (fold, case COND_EXPR): Get the type right when + the test is folded away. + + * loop.c (strength_reduce): Correct off-by-one error in INSN_LUID + safety check. + + * stor-layout (layout_record, layout_union): When limiting the + effect of PCC_BITFIELD_TYPE_MATTERS to bitfields, use + DECL_BIT_FIELD_TYPE to determine if it was a bitfield. + + Sat Apr 11 19:54:00 1992 Per Bothner (bothner@wombat.gnu.ai.mit.edu) + + * config.sub: Don't "standardize" an os of newsos* to bsd + (it breaks gdb/readline/configure.in, which checks for newsos*). + + Sat Apr 11 16:32:21 1992 Torbjorn Granlund (tege@hal.gnu.ai.mit.edu) + + * Makefile.in: Remove spaces after reg-stack.o deps. + + Sat Apr 11 16:32:15 1992 Michael Meissner (meissner@osf.org) + + * c-decl.c (init_decl_processing): Make -fno-builtin supress all + builtin functions in the user's name space like memcpy, strlen, + etc. + + Sat Apr 11 14:00:53 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * rs6000.h (LEGITIMIZE_ADDRESS): Add missing force_reg call. + Jump to WIN when we do something. + + * rs6000.c (non_{short,add,logical,and}_cint_operand): New functions. + * rs6000.h (PREDICATE_CODES): Add these predicates. + * rs6000.md (addsi3, andsi3, iorsi3, xorsi3, cmpsi3): Remove + define_expands; instead, add define_split for long constants. + + * combine.c (try_combine): Try to split the pattern using + split_insns before trying find_split_point. + (find_split_point, case MEM): Try to split an invalid address that + is a PLUS with a CONST_INT. + + * combine.c (try_combine): Correctly check if an auto-inc + side-effect has been duplicated. + + * expr.c (expand_expr, case PARM_DECL): Return zero of proper mode + if no DECL_RTL. + + * tree.c (save_expr): Must do something with read-only tree that + has side-effects. + (stabilize_reference_1): Don't ignore read-only trees. + + * reload.c (find_replacement): New function. + * reload.h (find_replacement): Declare it. + * reload1.c (gen_input_reload): Use it to ensure substitutions + get done if we need to recreate a PLUS. + + Sat Apr 11 14:00:02 1992 John F Carr (jfc at Achates.mit.edu) + + * cse.c (cse_end_of_basic_block): Don't stop scanning insns if a + jump is found that can't be followed. + + * genextract.c: Make insn_extract copy the address of + recog_operand and recog_operand_loc into register variables. + + Sat Apr 11 13:59:17 1992 Richard Stallman (rms at mole.gnu.ai.mit.edu) + + * c-parse.y (stmt): Parse entire parens of `for' + before actually starting the loop. + + Sat Apr 11 10:35:06 1992 Jeffrey A. Law (law@mole.gnu.ai.mit.edu) + + * caller-save.c (restore_referenced_regs): Do not call XEXP on + reg_equiv_address since reg_equiv_address is already an address. + + * expr.c (expand_builtin, case SQRT): Note the dangers involved in + changing the argument test condition. + + * m68k.md (sqrtdf2): New pattern to take advantage of the 68881 + sqrt function. + + Fri Apr 10 18:37:08 1992 Torbjorn Granlund (tege@hal.gnu.ai.mit.edu) + + * hp800.c (output_function_epilogue): Output code to restore gr2 in + non-frame-pointer case correctly. + + Fri Apr 10 15:24:57 1992 Michael Meissner (meissner@osf.org) + + * decrose.h (TARGET_MEM_FUNCTIONS): Define, memcpy/memset are + provided. + + * i386rose.h (TARGET_MEM_FUNCTIONS): Define, memcpy/memset are + provided. + + * encrose.h (TARGET_MEM_FUNCTION): Define, memcpy/memset are + provided. + + * mips-tfile.c (copy_object): Omit the test for zero flags, since + MIPS vendors are now putting bits in there. + + * mips-svr4.h (HAVE_ATEXIT): Define, atexit is provided. + (TARGET_MEM_FUNCTIONS): Define, memcpy/memset are provided. + + * mips-sysv.h (TARGET_MEM_FUNCTIONS): Define, memcpy/memset are + provided. + + * mips-news5.h (TARGET_MEM_FUNCTIONS): Define, memcpy/memset are + provided. + (getpagesize): Define a getpagesize that uses sysconf, just like the + MIPS V.4 port. + + * mips.c (output_block_move): Don't emit ulw/usw if GAS is the + assembler, use the lwl/lwr/swl/swr building blocks instead, since + GAS doesn't yet support the ulw/usw macro instructions. + + * configure (mips-sgi-irix4): Use config/iris4.h instead of + config/iris.h. + + * iris4.h (new file): Just like iris.h, atexit is provided (unlike + IRIX revision 3). + + * iris.h (TARGET_MEM_FUNCTIONS): Define, memcpy/memset are provided. + + Fri Apr 10 11:59:02 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * i386.md (cmpstr patterns): Correctly handle zero length + compares. Rewrite to avoid needing scratch register. + + Thu Apr 9 14:05:04 1992 Michael Collison (collison at osf.org) + + * i386rose.h (ASM_OUTPUT_FLOAT, ASM_OUTPUT_DOUBLE): Fix these to + avoid printing NaNs, and infinity. + + Thu Apr 9 11:34:31 1992 Tom Wood (wood at dg-rtp.dg.com) + + * m88kluna.h (DEFAULT_GDB_EXTENSIONS): Define as 0. + + Wed Apr 8 20:21:59 1992 Michael Meissner (meissner@osf.org) + + * halfpic.c (all functions): Add a hash table for the lookup instead + of linear search. Don't use bits in the IDENTIFIER node, store the + information in the hash table. Always rebuild the SYMBOL_REF + returned by half_pic_ptr, instead of storing it away, since the RTL + gets reused at the end of the function. + (half_pic_declare): New function, called when a label is laid down + to say that it is no longer half-pic. + + * halfpic.h (half_pic_declare, HALF_PIC_DECLARE): Add function + defintion, and accessor macro. + + * mips.h (HALF_PIC_DECLARE): Add dummy macro if not OSF/rose. + (ASM_DECLARE_OBJECT_NAME): Invoke HALF_PIC_DECLARE on name. + (ASM_DECLARE_FUNCTION_NAME): Ditto. + (*_SECTION_ASM_OP): Put the leading tab back in. + + * mips.md (dslot attribute): 'pic' type requires a delay slot, since + it is really a load. + (movsi): Make movsi a define_expand, and if it's moving the address + of a half-pic item into a register, convert it into a load. + (movsi_internal): The old movsi define_insn renamed. + (movstrsi_internal): Add '=' constraint on all stores and clobbers. + + * decrose.h (LINK_SPEC): If not -noshrlib or -pic-none, pass + -warn_nopic. Allow user to pass -noshrlib directly. + + Wed Apr 8 00:11:56 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * sparc.h (MOVE_MAX): Set to 8 instead of 4. + + * sched.c (sched_analyze_2): Don't abort if find note before a CC0 + using insn. + + * sparc.h (ADDITIONAL_REGISTERS_NAMES): Add. Define fake reg name + ccr, for use in asm clobbers. + + * sparc.h (TARGET_FORCE_ALIGN): Add comment explaining that it + is for experimental purposes only. + (FIRST_PARM_OFFSET): Add 4 when TARGET_FORCE_ALIGN to ensure that + stack is double-word aligned. + (FIRST_PARM_CALLER_OFFSET): Delete obsolete macro. + + From Tom Wood: + * unroll.c (final_giv_value): Put the subtracts in the right place. + + * sparc.c (compute_last_arg_offset): Delete, no longer needed. + (FRAME_POINTER_REQUIRED): Do not depend on frame size. + + Tue Apr 7 22:36:33 1992 Michael Meissner (meissner@osf.org) + + * halfpic.c (whole file): Flesh out initial half-pic implementation + for the OSF/1 reference ports. This is still a work in progress. + + * halfpic.h (toplevel): Add declarations for half_pic_finish and + half_pic_ptr. Add macros HALF_PIC_FINISH, HALF_PIC_PTR, and + HALF_PIC_PREFIX. + + * mips.h (call_memory_operand): Delete call_memory_operand + function declaration. + (PREDICATE_CODES): Ditto. + (CONSTANT_ADDRESS_P): Correctly reject half-pic addresses. + + * mips.c (call_memory_operand): Delete function. + + * mips.md (call* patterns): Use memory_operand instead of + call_memory_operand for predicates. Use the test not register and + not CONSTANT_ADDRESS_P instead of call_memory_operand in the + define_expand body to test whether the function address needs to be + forced to a register. + + * decrose.h (HALF_PIC_DEBUG): Define as true if -mdebugb, to debug + the half-pic code, just like debugging normal addressing. + (CPP_SPEC): Use the ____ form of the language macros instead + of __. + (LINK_SPEC): If -pic-lib and not -noshrlib, pass -warn_nopic. + (LIB_SPEC): Don't pass -L/usr/ccs/lib. + + * x-decrose (CCLIBFLAGS): Pass -pic-extern when building libgcc1.a. + (LIBGCC2_CFLAGS): Pass -pic-extern when building libgcc2.a. + + Tue Apr 7 19:00:56 1992 Tom Wood (wood at dg-rtp.dg.com) + + * xm-m88k.h (NO_SYS_SIGLIST): Not provided by the 88open standards. + + * m88k.c (output_ascii): Generalize to support ident + * m88k.h (ASM_OUTPUT_IDENT, ASM_OUTPUT_ASCII): Use output_ascii. + + * m88k.c, m88k.md, m88k.h: Integrate all changes to support the m88110. + + Mon Apr 6 22:51:02 1992 John Wroclawski (jtw@lcs.mit.edu) + + * mips-tfile.c (read_seek): Fix argument order in calls to + fatal. + + Mon Apr 6 21:17:38 1992 Mike Stump (mrs@albert.gnu.ai.mit.edu) + + * merged in Cygnus sources. + + Mon Apr 6 15:26:09 1992 Mike Stump (mrs@cygnus.com) + + * cp-spew.c (hack_more_ids): Reimplement. Change from Niklas + Hallqvist. + + Thu Apr 2 02:36:36 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-*: Simplify DECL_NAME (TYPE_NAME into TYPE_IDENTIFIER. + + * cp-call.c (build_method_call): Fix an error message. + + * cp-parse.y (LC): Renamed to left_curly. + (TYPENAME_SCOPE): Renamed to typename_scope. + + Mon Apr 6 14:04:49 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * sparc.h (TARGET_HOPE_ALIGN): Fix typo, `-fast' -> `-dalign'. + + * expr.c (expand_expr, INDIRECT_REF case): Set MEM_IN_STRUCT_P if + this is an indirect of the address of an array, struct, or union. + + * jump.c: Delete declaration of squeeze_notes. + (jump_optimize): Use new return value from squeeze_notes. + (squeeze_notes): Handle the case where START may be a note that + must be moved outside the range. Now returns the new start value. + * loop.c (find_and_verify_loops): Use squeeze_notes return value. + * stmt.c (expand_end_case): Call squeeze_notes before reorder_insns. + * rtl.h: Declare squeeze_notes. + + * rs6000.h (PTRDIFF_TYPE): Define to int. + + Mostly from tege@sics.se: + * sparc.c (eligible_for_epilogue_delay): Clarify comment. Delete + unreachable test of leaf_function. + (singlemove_string): Correct test for when can use sethi alone. + (output_function_prologue): Declare leaf_function. More + efficiently frame sizes greater than 4095. Correctly handle leaf + functions with frame greater than 4095. + (output_function_epilogue): Likewise. + (output_return): Likewise. + + Mon Apr 6 10:11:08 1992 Tim Moore (moore@defmacro.cs.utah.edu) + + * config.sub : Add hp700 cpu type. + * configure : Make hp700-bsd and hp700-hpux cases, with use of gas + an option. + * hp700hpuxg.h, hp800hpuxg.h : New files for using gas under hpux. + * hp800.h (REGISTER_NAMES): Change to use %r style register names; + required to name PA-RISC 1.1 fp registers. + * x-hp800hpux : Don't invoke the assembler to compile alloca.c. + * README-PA-RISC: New file. + + Mon Apr 6 08:00:06 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * reorg.c (relax_delay_slots): Don't get confused when a label + becomes zero (meaning end of function). + + Sun Apr 5 13:45:37 1992 Ron Guilmette (rfg at ncd.com) + + * i860.md (floatsidf3): Fixed to expand to a correct insn sequence. + + Sun Apr 5 12:33:02 1992 John F Carr (jfc at Achates.mit.edu) + + * rs6000.h (EXTRA_CC_MODES, EXTRA_CC_NAMES): Add CCEQmode. + (SELECT_CC_MODE): Select it for equality comparison of comparison. + * rs6000.c (scc_comparison_operator): Reject improper use of + CCEQmode. + (ccr_bit): Handle CCEQmode, where bit is always third in field. + (print_operand, case 'E'): New case. + * rs6000.md: New pattern to compare two comparisons with + creqv/crxor. + Add peephole for two consecutive scc insns. + + * combine.c (subst, case FFS): (ffs (*_extend X)) -> (ffs X) + (make_compound_operation): Handle (and (rotate X C) M). + + * flags.h (flag_cse_skip_blocks): New variable. + * toplev.c (flag_cse_skip_blocks): Define it here. + (f_options): Add it to table. + (main): -O2 turns it on. + * cse.c (invalidated_skipped_{set,block}): New functions. + (enum taken): New value, AROUND. + (cse_end_of_basic_block): New argument SKIP_BLOCKS. If it is + nonzero, follow a branch around a block of code which contains + no labels and set status = AROUND for the jump. + (cse_main): Pass FLAG_CSE_SKIP_BLOCKS argument to + cse_end_of_basic_block. + (cse_basic_block): If jump status is AROUND, call scan_skipped_block + before following jump. + + Sun Apr 5 04:16:46 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * optabs.c (emit_cmp_insn): Add missing parameter type declaration. + + * expr.c (expand_builtin, case SQRT): Fix typo emitting insns. + Reformat to look like the rest of gcc. Use accessor macros to + access fields of an RTX. Make comments match code. + + * i386.md (cmpstr patterns): Handle zero length compares. + + Sat Apr 4 04:40:58 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * reload.c (find_equiv_reg): Avoid passing zero to true_regnum. + + * expr.c (expand_expr, case COMPONENT_REF): Handle case where we + are extracting a field of a constant. + + * a29k.h ({TEXT,READONLY_DATA,DATA}_SECTION_ASM_OP): Put tab back. + + * rs6000.c (output_epilog): Reduce number of lines generated to + write traceback table. + + * combine.c (move_deaths): A destination is used in this insn + unless is it completely overwritten. + + Sat Apr 4 04:39:16 1992 John Carr (jfc at ATHENA.MIT.EDU) + + * expmed.c (store_bit_field, extract_bit_field): Remove redundant + tests for MEM. + + * c-common.c (binary_op_error): Handle FLOOR_DIV_EXPR, FLOOR_MOD_EXPR, + *ROTATE_EXPR. + * c-typeck.c (build_binary_op): Handle FLOOR_MOD_EXPR. + + Sat Apr 4 00:29:40 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * c-decl.c (c_decode_option): `-' was missing in -Wno-redundant-decs. + + * Makefile.in (USE_COLLECT2, MAYBE_USE_COLLECT2): New variables. + (GCC_PARTS, native, install-common): Use USE_COLLECT2. + (toplev.o): Use MAYBE_USE_COLLECT2. + * configure: Let particular cases set use_collect2 + and have that control use of collect2 through editing Makefile. + Handle --with-gnu-as and --with-gnu-ld options. Ignore --with-*. + --with-gnu-ld turns off use_collect2. + * i386rose.h (CC1PLUS_SPEC): Deleted. + + * gcc.c (do_spec_1): In case 'D', strip final / from prefixes. + + * c-decl.c (push_c_function_context): Add pedantic warning. + + * collect2.c (main): Figure STANDARD_EXEC_PREFIX into clen. + + * c-typeck.c (get_spelling): Move alloca outside fn call. + + Fri Apr 3 16:36:54 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * varasm.c (output_constant_def): Set MEM_IN_STRUCT_P if nec. + + Fri Apr 3 05:32:39 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * m88k.md (call_block_move{,_loop}): Don't write USE for regs + we don't set; remove unneeded CLOBBERs for call-used registers. + + * caller-save.c (insert_save_restore): Abort rather than writing + out an insn having a null source or destination. + + * explow.c (allocate_dynamic_stack_space): Don't reference + STACK_BOUNDARY if it isn't defined. + + * explow.c (allocate_dynamic_stack_space): Don't use TARGET if it + isn't a pseudo reg. + + Fri Apr 3 01:50:57 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * fixinc.svr4: Don't reconvert __i386 if have _ after. + + * c-decl.c (grokdeclarator): Use size_binop to get array hbound - 1. + + * enquire.c: Include sys/types.h. + + * c-typeck.c (check_format): Don't use type name for integer types + or pointers to them. + + * explow.c (allocate_dynamic_stack_space): New arg KNOWN_ALIGN. + All callers changed. + + Thu Apr 2 15:24:38 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * dbxout.c (dbxout_type): Output just xref for var-size struct/union. + + * reload.c (find_equiv_reg): In previous change, verify valtry != 0. + + Thu Apr 2 08:34:38 1992 Michael Meissner (meissner@osf.org) + + * iris.h (SIZE_TYPE): Make type unsigned int, not unsigned long. + (PTRDIFF_TYPE): Define to be 'int', not 'long int'. + (WCHAR_TYPE): Define to be 'unsigned char', not 'int'. + (WCHAR_TYPE_SIZE): Define to be 8, not 32. + + Thu Apr 2 06:01:07 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * fold-const.c (fold, case COND_EXPR): Add missing test for zero. + + * expr.c (expand_expr, case ARRAY_REF): Handle case of constant + array whose initializer is a string. + + * optabs.c (emit_libcall_block): Don't move up insns that set + pseudos whose old values are used in previous insns. + + * genattrtab.c (attr_rtx): Add some casts to int from enum rtx_code. + + Thu Apr 2 04:20:30 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * xm-mipsnbsd.h: New file. + * configure (mips-sony-bsd*): Use that. + + * stmt.c (expand_end_case): Move the convert_to_mode after emit_queue. + + Thu Apr 2 00:49:18 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * stmt.c (expand_end_case): Fix typo. + + Wed Apr 1 19:01:00 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * fold-const.c (size_int): Always switch to permanent_obstack + to make a node that will be saved + + Wed Apr 1 15:36:19 1992 Michael Meissner (meissner@osf.org) + + * xm-irix4.h (alloca.h): Don't include if not using the + GNU compiler, since the Silicon Graphics compiler's alloca complains + if the result of alloca is stored in something that is not a simple + variable. Just use the C version of alloca.c. + + Wed Apr 1 14:42:24 1992 Torbjorn Granlund (tege@mole.gnu.ai.mit.edu) + + * pyr.md (HImode compare recognizers): Don't match if subsequent + branch has unsigned predicate. + + Wed Apr 1 14:20:13 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * sparc.c (output_function_epilogue): Drop unused true_epilogue + parameter. Delete obsolete tail-call support code, which worked + by passing -1 for leaf_function. + (tail_call_valid_p): Delete obsolete function. + (output_tail_call): Likewise. + * sparc.h (TARGET_TAIL_CALL): Delete obsolete option. + (FUNCTION_EPILOGUE): Fix call to output_function_epilogue. + * sparc.md (tail_call): Delete obsolete pattern. + + * rs6000.c (output_epilogue): Output a traceback table. + + Wed Apr 1 06:42:54 1992 Tom Wood (wood at dg-rtp.dg.com) + + * m88k.h: Override ASM_OPs added to svr4.h. + + Wed Apr 1 03:12:44 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * emit-rtl.c (operand_subword): Swap words from const_double if nec + + * ns32k.h (GO_IF_INDEXING): New arg MODE; caller changed. + Pass to INDEX_TERM_P. + + Tue Mar 31 18:10:10 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * genattrtab.c (check_attr_value): Fix some backwards tests. + + * expr.c (move_by_pieces{,_ninsns}): Only look at MODE_INT modes. + + * fold-const.c (fold, case COND_EXPR): Fix typo in last change. + + * stor-layout.c (layout_record): Add missing call to size_int. + + * expr.c (do_store_flag): Handle case where EXP is a TRUTH_NOT_EXPR. + + Tue Mar 31 17:18:20 1992 Jeffrey A. Law (law@mole.gnu.ai.mit.edu) + + * c-decl.c (init_decl_processing): Enable `sqrt'. + * expr.c (expand_builtin, case SQRT): By default check that the + argument to sqrt is in sqrt's domain. If the argument is not in the + domain, then call the library function. Skip argument checking if + -ffast-math is in use. + + * flags.h (flag_fast_math): Declare new variable. + * toplev.c (f_options): Add flag_fast_math to table. + + Tue Mar 31 17:11:09 1992 Per Bothner (bothner@wombat.gnu.ai.mit.edu) + + * cccp.c: Add new flag -nostdinc++ to disable searching + standard C++-specific include directories. This is useful + for building libg++. + * gcc.c: Pass -nostdinc* to cpp, not just -nostdinc. + * cpp.texi: Document -nostdinc++. + + Tue Mar 31 15:32:34 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * gcc.c (link_command_spec): Use %l before %X. + + * svr4.h (MULTIBYTE_CHARS): Turned off. + + * sun3.h, sparc.h (LINK_SPEC): Inhibit -e if -nostdlib. + + * collect2.c (my_strerror): Renamed from strerror. + + * reload.c (find_equiv_reg): Find constants in REG_EQUIV notes. + + * m68k.h (PRINT_OPERAND_PRINT_FLOAT): Fix typo in #ifdef. + + * Makefile.in (install-dir): Create include subdir. + + Tue Mar 31 18:03:21 1992 Thorsten Ohl (ohl@apollo.desy.de) + + * x-apollo68 (CFLAGS, LIBGCC2_CFLAGS): Defined. + * t-apollo68: new file, use collect2. + * configure: use `t-apollo68'. + + * apollo68.h (ASM_SPEC): Delete -C. + (STRUCT_VALUE_INCOMING): Now 0. + (HAVE_ATEXIT): Defined. + (PROMOTE_PROTOTYPES): Delete #undef. + (USER_LABEL_PREFIX): Undef. + (LOCAL_LABEL_PREFIX, REGISTER_PREFIX, REGISTER_PREFIX_MD): Override. + (ASM_RETURN_CASE_JUMP): Defined. + (REGISTER_NAMES): Override. + + Tue Mar 31 14:59:53 1992 Tim Moore (moore@defmacro.cs.utah.edu) + + * hp800.md (movsi+4, call_value+1): Add x,y constraints for Snake + fp registers. + * hp800.h (INITIAL_FRAME_POINTER_OFFSET): Fix for Snake stack + alignment. + (REGNO_OK_FOR_INDEX_P, REGNO_OK_FOR_BASE_P): Fix for Snake fp + registers. + * hp800.c (output_function_prologue): Align stack for Snakes. + (output_arg_descriptor): Fix Snake typos. + + * hp700.h, hp700hpux.h : New files + (TARGET_DEFAULT): Emit Snake code by default. + * hp700hpux.h (HP_FP_ARG_DESCRIPTOR_REVERSED): Define to work + around assembler syntax difference between 700 and 800 series HPUX. + * hp800.h (ASM_DOUBLE_ARG_DESCRIPTORS): Conditionalize on the + above symbol. + + Tue Mar 31 09:58:52 1992 Michael Meissner (meissner@osf.org) + + * mips-sysv.h (getpagesize): When compiling the trampoline code, + define a macro getpagesize which uses the POSIX sysconf function. + + * mips-svr4.h (getpagesize): When compiling the trampoline code, + define a macro getpagesize which uses the POSIX sysconf function. + + Mon Mar 30 19:25:48 1992 Jim Wilson (wilson@wookumz.gnu.ai.mit.edu) + + * loop.c (strength_reduce): In recent maybe_multiple code, only + apply INSN_LUID to insn when safe. + + Mon Mar 30 17:24:33 1992 Michael Meissner (meissner@osf.org) + + * mips.c (output_block_move): Fix typos that would generate + incorrect code if either the source or destination is a global or + static memory address. Increment appropriate -mstats counters. + + * x-iris (INSTALL): Use cp to install stuff, not install -c. + + Mon Mar 30 16:39:28 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * m68k.md: Use `\;', not `;', to separate insns. + + * toplev.c (main): Add cast when setting debug_info_level. + + * m68k.h (GLOBAL_ASM_OP): New macro. + (ASM_GLOBALIZE_LABEL): Use that. + * hp320.h, m68ksgs.h, mot3300.h (GLOBAL_ASM_OP): Override this. + (ASM_GLOBALIZE_LABEL): Not this. + + * libgcc2.c (__builtin_saveregs) [sparc]: Define both assembler labels + __builtin_saveregs and ___builtin_saveregs, to handle all systems. + + * m68k.h (TRANSFER_FROM_TRAMPOLINE): Add a globalize command. + (TRAMPOLINE_TEMPLATE): Make the JSRs really JSRs. + Always use precisely ___trampoline. + + Mon Mar 30 07:17:50 1992 Richard Kenner (kenner@vlsi1.ultra.nyu.edu) + + * reload1.c (inc_for_reload): Declare CODE consistently. + (constraint_accepts_reg_p): Add missing cast. + + * fold-const.c (fold, case TRUTH_ANDIF_EXPR): Fix typo in last change. + + Mon Mar 30 01:07:33 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * rtl.h: Don't continue #if lines. + + Mon Mar 30 03:30:54 1992 Mike Stump (mrs@cygnus.com) + + * Merge in Cygnus cp-* sources, below are the ChangeLog entries from + the Cygnus ChangeLog file. Note, I am experimenting with a slightly + different format, as Tiemann would like the dates to remain intact, + but Stallman does not want the dates out of order and would rather + have the entries altogether anyway. + + Sun Mar 29 16:57:31 1992 Mike Stump (mrs@rtl.cygnus.com) + + * cp-decl.c (grokdeclarator): Handle typedef before other + specifiers, as typedef is now more complex in c++ than in c. + + Sun Mar 29 12:00:03 1992 Michael Tiemann (tiemann@cygnus.com) + + * cp-decl.c (start_function): Always set TREE_PUBLIC if DECL1 is + part of any interface. + + * cp-cvt.c (convert_to_reference): Don't type to convert a type to + itself. + (build_type_conversion): Don't look for alternatives to default + type conversion except to integral and real types. Fixes bug + exposed in 19 March change. + + Tue Mar 24 07:53:46 1992 Michael Tiemann (tiemann@cygnus.com) + + * cp-tree.c (lvalue_p): POST{INC,DEC}REMENT_EXPR is not an lvalue. + * cp-typeck.c (build_modify_expr): Ditto. + + * cp-init.c (emit_base_init): If debugging, force out a line note so + we can step into ctors for base initializers. + (build_virtual_init): Note that we need to do some more work to + handle replicated base classes in multiple inheritance lattices. + + Mon Mar 23 00:33:35 1992 Michael Tiemann (tiemann@cygnus.com) + + * cp-init.c (expand_aggr_init_1): Finish Mar 15 change concerning + INDIRECT_REFs that have TREE_HAS_CONSTRUCTOR set. + + * cp-call.c (build_overload_call_real): Ensure FINAL_CP->EVIL is set + when FINAL_CP is non-NULL and we encounter an ERROR_MARK_NODE in the + operands we are processing. + + * cp-cvt.c (convert_to_reference): Propagate ERROR_MARK_NODE from + failed type conversions. + + Sun Mar 22 20:01:51 1992 Michael Tiemann (tiemann@cygnus.com) + + * cp-init.c (is_aggr_typedef): Don't give an error message if NAME + is ERROR_MARK_NODE. + + Sun Mar 29 09:29:10 1992 (Eric Youngdale at youngdale@v6550c.nrl.navy.mil) + + * make-gcc.com: Remove patch from March 7. + + * make-l2.com: Use compiler that was just built, if available, + otherwise use system compiler if it is version 2. + + Sun Mar 29 19:53:33 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * fold-const.c ({invert,swap}_tree_comparison): New functions. + (comparison_equiv_p): Deleted. + (operand_equal_for_comparison_p): New function. + (invert_truthvalue): Use invert_tree_comparison. + (fold): Use variables T1 and TEM consistently. + Don't mix arg[01] and TREE_OPERAND (t, [01]); they aren't + identical. + (fold, comparison cases): Use new functions to adjust comparison + codes; add var INVERT. + Convert f >= f to f == f for FP and similar. + Correctly compute FP <= and >= when one arg is a NaN. + Clean up handling of constant results. + (fold, case COND_EXPR): Rework considerably to catch more forms + of abs, min, max, and -abs and also clean up; use new function + operand_equal_for_comparison_p. + + Sun Mar 29 00:00:35 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * cse.c (simplify_relational_operation): Arg ptr reg may be 0. + + * gcc.c: Always define R_OK, etc. if system headers don't. + + * c-parse.y (maybe_attribute): Accept `mode (m)' attribute. + * c-common.c (decl_attributes): Handle that attribute. + + * tower.h (REGISTER_NAMES): Discard the fpa regs. + * tower-as.h (FUNCTION_PROLOGUE, FUNCTION_EPILOGUE): + Don't handle fpa regs. + (PUT_SDB_START_DIM, PUT_SDB_NEXT_DIM, PUT_SDB_LAST_DIM): + New macros. + (PUT_SDB_DIM): Deleted. + + * m68k.h (RTX_COSTS): Smaller multiply costs on 68040. + + * stmt.c (expand_end_case): Reduce amount of specific modes + used in handling casesi. + + * collect2.c (savestring): Copy only SIZE bytes of string. + + * gstddef.h: Handle __need_size_t, __need_wchar_t, __need_ptrdiff_t, + and _need_null. + + * c-typeck.c (digest_init): Save INIT with nops not stripped + to pass to convert_for_assignment. + + Sun Mar 29 12:27:01 1992 (Eric Youngdale at youngdale@v6550c.nrl.navy.mil) + + * vms.h (FUNCTION_PROLOGUE): Redefine to add 4 bytes to local + storage on the stack. + (STARTING_FRAME_OFFSET): Redefine as -4. + + Sun Mar 29 19:58:57 1992 Paul Eggert (eggert@twinsun.com) + + * c-decl.c (store_parm_decls): Function prototypes now override + old-style definitions if argument types disagree only because of + promotions. + + Sun Mar 29 17:40:56 1992 Fred Fish (fnf at fishpond) + + * fixincludes (stdlib.h): Fix free/calloc/malloc/realloc return types. + + Sun Mar 29 15:12:39 1992 Ron Guilmette (rfg at ncd.com) + + * sparc.c (sparc_type_code): Added this new routine. + (tree.h): Included to support `sparc_type_code'. + (output_block_move): Cleaned up code to handle assembler-specific + aspects of internal labels. + + * sparc.h: (REG_ALLOC_ORDER, REG_LEAF_ALLOC_ORDER, LEAF_REGISTERS): + Deleted spurious semicolons. + (ASM_DECLARE_RESULT): New macro to generate the .proc directive. + (ASM_DECLARE_FUNCTION_NAME): Changed to use ASM_DECLARE_RESULT. + (ASM_OUTPUT_ADDR_VEC_ELT, ASM_OUTPUT_ADDR_DIFF_ELT): Changed to use + ASM_GENERATE_INTERNAL_LABEL when generating jump table elements. + + * svr4.h (SVR4): Don't define this symbol here. (It was never + needed, and it will be used to indicate an SVR4 *host* from now on.) + (SKIP_ASM_OP): Define this new macro. + (ASM_OUTPUT_SKIP): Use SKIP_ASM_OP. + (ASM_OUTPUT_INTERNAL_LABEL, ASM_GENERATE_INTERNAL_LABEL): Added + new definitions appropriate for most SVR4 assemblers. + (COMMON_ASM_OP, LOCAL_ASM_OP): Define these new macros. + (ASM_OUTPUT_ALIGNED_COMMON, ASM_OUTPUT_ALIGNED_LOCAL): Use them. + (ASM_OUTPUT_ALIGNED_LOCAL): Allocate things in common rather than + trying for the .bss section (which may not work). + (ASM_DECLARE_RESULT): Define this to do nothing (if not already + defained for target machine). + (ASM_DECLARE_FUNCTION_NAME): Add invocation of ASM_DECLARE_RESULT. + + * dwarfout.c (ASM_DWARF_POP_SECTION): Renamed ASM_OUTPUT_POP_SECTION. + (PUSHSECTION_ASM_OP, POPSECTION_ASM_OP): New macro definitions. + (SECTION_ASM_OP): Deleted. Replaced by PUSHSECTION_ASM_OP. + (ASM_OUTPUT_PUSH_SECTION, PUSHSECTION_FORMAT): New macro definitions. + (*_SECTION): New macro definitions for important section name strings. + (ASM_DWARF_*_SECTION): Deleted all macros to change to specific + sections and replaced them globally with calls to the new parameterized + ASM_OUTPUT_PUSH_SECTION macro. + + Sat Mar 28 17:28:17 1992 Michael Meissner (meissner@osf.org) + + * mips.h (MIPS_VERSION): Bump Meissner version # to 15. + (output_block_move): Add function defintion. + (HALF_PIC_PTR, HALF_PIC_FINISH): Provide dummy definitions. + (OPTIMIZATION_OPTIONS): Set flag_gnu_linker to FALSE, and + flag_no_cse_function to TRUE. + (CC1PLUS_SPEC): Delete -- it just passed -fno-gnu-binutils to + cc1plus. + + * mips.c (block_move function): Use movstri_internal, instead of + emitting the moves directly. + (output_block_move): New function to emit the correct code for block + moving a constant amount of data. + (siginfo): Change options to ps. + + * mips.md (movstrsi_internal): New block move pattern. + (movsi_ulw): Add an appropriate REG_EQUIV regnote. + (movsi_usw): Type attribute is store, not load. + + * mips-gbsd.h (toplevel): Include mips-bsd.h, not mips-gbsd.h. + + * mips-bsd.h (MD_STARTFILE_PREFIX, MD_EXEC_PREFIX): Use explicit + BSD43 prefixes. + + * mips-sysv.h (MD_STARTFILE_PREFIX, MD_EXEC_PREFIX): Use explicit + System V prefixes. + + * mips-svr4.h (MD_STARTFILE_PREFIX, MD_EXEC_PREFIX): Use explicit + System V.4 prefixes. + + * decstatn.h (TARGET_MEM_FUNCTIONS): Define. + + Sat Mar 28 15:12:39 1992 Ron Guilmette (rfg at ncd.com) + + * libgcc2.c (eprintf): Make argument types comsistant with assert.h. + (__builtin_new, __builtin_vec_new): Declare all external functions. + (default_new_handler): Use a macro for the "memory exausted" message. + + * sparcv4.h: File completely replaced (with one that works). + + Sat Mar 28 15:09:46 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * toplev.c (flag_gnu_linker): Default to 0 if USE_COLLECT2. + + * i386.h (TARGET_SWITCHES): Add svr3-shlib. + (TARGET_SVR3_SHLIB): New macro. + * i386v.h (ASM_OUTPUT_LOCAL): Override definition here. + + * Makefile.in (gcc.xtar): Update version in README. + + * libgcc2.c [sparc] (__builtin_saveregs): Add optional .proc, + .type and .size assembler commands. + + * dbxout.c (dbxout_type): New arg SHOW_ARG_TYPES. All calls changed. + (dbxout_type_methods): Mostly rewritten, with Tiemann's help. + + * Eliminate limit on alignment value of a variable or field. + * tree.h (DECL_ALIGN): Use frame_size slot. + (struct tree_decl): `align' slot deleted. + * print-tree.c (print_node): Print `align' or `frame_size', not both. + * expr.c (get_pointer_alignment): Don't use DECL_ALIGN of function. + * c-decl.c (duplicate_decls, finish_enum): Likewise. + * tree.c (make_node): Likewise. + * c-common.c (decl_attributes): Eliminate limit of 255 on alignment. + + * collect2.c: Don't include gstdarg.h or gvarargs.h. + Make error messages follow standards. + (error, fatal, fatal_perror): Don't use varargs. + Accept as many args as anyone tries to use. + + * cp-decl2.c: Get rid of -fgnu-binutils. + + * ns32k.h (INDIRECTABLE_ADDRESS_P): Deleted. + (GO_IF_NONINDEXED_ADDRESS): Delete dupllicate test for reg+offset. + (MEM_REG): Don't accept constant here. + (INDIRECTABLE_2_ADDRESS_P): Adapt usage of MEM_REG. + (GO_IF_INDEXING, GO_IF_INDEXABLE_ADDRESS): New macros. + (GO_IF_LEGITIMATE_ADDRESS): Use them. + + Sat Mar 28 20:48:20 1992 Chip Salzenberg (chip at tct.com) + + * stor-layout.c (layout_record, layout_union): + Limit effect of PCC_BITFIELD_TYPE_MATTERS to actual bitfields. + (layout_decl): Do not override a packed decl's alignment. + + * c-common.c (decl_attributes): Don't expect a simple + attribute like "packed" to be in a LIST_NODE. + + * c-decl.c (finish_struct): If a field has the "packed" + attribute, don't override it with type's normal alignment. + + Sat Mar 28 06:51:12 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * integrate.c (initialize_for_inline): Replace DECL_INCOMING_RTL + if it has an address shared with DECL_RTL, not just when the entire + value is shared. + + * rs6000.c (input_operand): Clean up and make comments agree with + code; no changes to what is matched. + + * loop.c (add_label_notes): Handle operands of type 'E'. + + * rs6000.c (print_operand, case 'A'): Fix typo. + + Sat Mar 28 01:29:06 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * output.h (current_function_uses_const_pool): New declaration. + + * i386.c (function_{prologue,epilogue}, simple_386_epilogue): + If the constant pool is used, the PIC reg will be used. + + * expr.c (expand_builtin): Add support for named pattern strlenM. + * expr.h (strlen_optab): New declaration. + * optabs.c (init_optabs): Initialize strlen_optabs. + * i386.md (strlensi): New pattern. + + Fri Mar 27 12:11:03 1992 Fred Fish (fnf at fishpond) + + * fixinc.svr4 (dbm.h): Fix unconditional redefinition of NULL + + * config.sub: Add i486 as a distinct CPU type. Recognize i486v4 + as distinct from i386v4. Change ncr3000 to i486. + * configure: Add i486-ncr-sysv4. + * config/x-ncr3000: New file. + + Fri Mar 27 18:44:45 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * fold-const.c (twoval_comparison_p, eval_subst): New functions. + (fold): If an operand of a comparison is a COMPOUND_EXPR, move + it outside the comparison. + (case GT_EXPR, ...): Replace old code to fold comparisons + of comparisons with new code using new functions above. + When changing code of unsigned comparisons, set variable CODE. + + * expr.c (get_inner_reference): Return BLKmode and -1 size for a + variable-sized object instead of aborting. + (do_jump, case COMPONENT_REF): If get_inner_reference returns a + size of -1, don't do anything special. + * fold-const.c (optimize_bit_field_compare, decode_field_reference): + Likewise. + + * combine.c (reg_bitfield_target_p): Replace test with one that + compares the register number of X with that of a register which + is the target of the assignment. + + * loop.h (struct_induction): New field maybe_multiple. + * loop.c (strength_reduce): Track when code may be executed more + than once per iteration; pass to record_biv. + Call update_giv_derive on every JUMP_INSN. + (record_biv): Copy new maybe_multiple arg to struct induction. + (record_giv): Clear maybe_multiple. + (update_giv_derive): If passing JUMP_INSN, look at maybe_multiple + in biv update. + + * expr.c (expand_expr, case MODIFY_EXPR): Add missing call to + do_pending_stack_adjust. + + * rs6000.h (OBJECT_FORMAT_COFF): Add definition. + + Fri Mar 27 15:58:42 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * c-typeck.c (check_format): If arg wants void *, accept any ptr. + + * ns32k.md (CALL_MEMREF_IMPLICIT, MOVD_FLOAT_OK): + New parameters replace GAS_SYNTAX. + * pc532.h (CALL_MEMREF_IMPLICIT, MOVD_FLOAT_OK): Define both. + * sequent.h (CALL_MEMREF_IMPLICIT): Defined. + + * sequent.h (INDEX_RATHER_THAN_BASE): Defined. + * ns32k.c (print_operand_address): Check it here. + + * ns32k.c (print_operand_address): Treat all non-ints as symbolic. + (print_operand): Likewise. Also fix typo, use PUT_ABSOLUTE_PREFIX, + and test NO_ABSOLUTE_PREFIX_IF_SYMBOLIC. + + * svr4.h (ASM_OUTPUT_CONSTRUCTOR, ASM_OUTPUT_DESTRUCTOR): + Output newline after section op. + * i860v3.h (DTORS_SECTION_ASM_OP, CTORS_SECTION_ASM_OP): + Delete newlines. + + * Makefile.in (clean): Don't delete stage*. + (distclean): Do it here. + (extraclean): Delete config/patch*. + + * Makefile.in (SYSCALLS.c): Target deleted. + (SYSCALLS.c.X): Create SYSCALLS.c and use it in one rule. Delete also. + + * Makefile.in (ld): New target. + * t-* (ld, collect2*): Targets deleted. + (EXTRA_PROGRAMS): Moved ld here if it was in EXTRA_PASSES. + (EXTRA_PASSES): Delete ld. + + * gcc.c, cccp.c: Don't include sys/file.h. + + * fold-const.c (operand_equal_p): Floats must match bit for bit. + + * gcc.c (link_command_spec): Put back -u*. + + Fri Mar 27 11:33:46 1992 Simon J. Gerraty (sjg@melb.bull.oz.au) + + * configure (m68k-bull-sysv*): Added config for Bull DPX/2 + * dpx2.h, dpx2g.h: New files. + * x-dpx2200, x-dpx2300, t-dpx2: New files. + * gstddef.h: Added _SIZET_ to the list of protection for size_t + + Fri Mar 27 14:47:47 1992 Paul Eggert (eggert@twinsun.com) + + * c-typeck.c (convert_arguments): -Wconversion wrongly warned when + passing enums, and didn't warn about int precision mismatches. + + * fold-const.c (fold): If IEEE, 0-x is not x. + + * cse.c (simplify_unary_operation): fabs(-0.0) is 0.0, not -0.0. + * fold-const.c: Replace target_minus_zero with target_negative. + (fold_convert): Warn when converting NaN constants to integer. + (fold): fabs(-0.0) is 0.0, not -0.0. 0-x may not equal -x. + Do not optimize X++ == C to ++X == C+1 if C is floating point, + because it runs afoul of rounding error. + * real.h (REAL_VALUE_NEGATIVE): Add. + + Fri Mar 27 09:19:11 1992 Tom Wood (wood@dg-rtp.dg.com) + + * m88k.c (emit_move_sequence): Check the size required for a zero + constant. + + * varasm.c (const_hash, compare_constant_1, record_constant_1): + For constructor of an array, include the size of the array in bytes. + + Fri Mar 27 09:09:53 1992 Michael Meissner (meissner@osf.org) + + * t-decstatn (ALL): Remove variable. + * t-decrose (ALL): Ditto. + * t-i386rose (ALL): Ditto. + * t-encrose (ALL): Ditto. + + Fri Mar 27 17:51:32 1992 Jim Wilson (wilson@sphagnum.cygnus.com) + + * rs6000.c (first_reg_to_save): When profiling, save space for the + argument registers, which need to be saved around the mcount call. + (output_prolog): Mark the link register as live when profiling. + (output_function_profiler): New function. Output code to call + mcount. + * rs6000.h (LIB_SPEC): Replace incorrect definition. Add + -L/lib/profiled and -L/usr/lib/profiled when profiling, -lg when + debugging, and -lc always. + (OVERRIDE_OPTIONS): No longer zero profile_flag. + (FUNCTION_PROFILER): Call output_function_profiler. + + * .gdbinit (complaints): Set to 20. + (pbs): New command to call the cc1plus print_binding_stack function. + + * calls.c (expand_call): Delete obsolete references to is_builtin_new. + + * Makefile.in (Makefile): Add dependence on version.c. + + Thu Mar 26 19:21:00 1992 James Van Artsdalen (james at bigtex.cactus.org) + + * i386.md (fixuns_truncMN2,fix_truncMdf2): Make a copy of the input + operand and clobber that, rather than clobbering the operand itself. + + Thu Mar 26 18:06:32 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * protoize.c (shortpath): Add early check of size of shortname. + + * expr.c (do_jump): Adjust stack after any code that might be skipped. + + Thu Mar 26 06:37:35 1992 Michael Meissner (meissner@osf.org) + + * mips.c (toplevel): If NO_STAB_H is defined, include gstab.h + instead of stab.h. + + Thu Mar 26 02:21:50 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * Makefile.in (STAGESTUFF): Add EXTRA_PROGRAMS. + + * configure: Reorder mips alternatives; put mips-mips-* at end. + + * sparc.h (FRAME_POINTER_REQUIRED): 0 if frame is too big. + * sparc.c (compute_last_frame_offset): New function. + + Wed Mar 25 21:17:36 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) + + * genattrtab.c (check_attr_test): Use XSTR instead of XEXP in one + place. + + * genextract.c (mark_operand_seen): Call xrealloc properly. + + Wed Mar 25 17:05:56 1992 Torbjorn Granlund (tege at zevs.sics.se) + + * hp800.c (srcsi_operand): New function. + * hp800.md (mulsi, divsi, udivsi, modsi, umodsi): Use srcsi_operand + for inputs. + (mulsi): Use general_operand for output. + (one_cmplsi2): Use register_operand for output. + + Wed Mar 25 15:50:12 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * m68k.md (fsgldiv pattern): If FSGLDIV_USE_S, opcode has .s, not .x. + * amix.h (FSGLDIV_USE_S): Defined. + + * xm-rs6000.h (REAL_NM_FILE_NAME): Defined. + + * x-i386sco (CCLIBFLAGS): Define as empty. + + Wed Mar 25 16:52:53 1992 Michael Meissner (meissner at osf.org) + + * collect2.c (OSF/rose scan_prog_file): If we are building a + program instead of a shared library, don't create an initializer + function entry. + Tue Mar 24 04:00:00 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) *************** *** 18,23 **** (SYSCALLS.c, SYSCALLS.c.X): Copy from Makefile.in. - * x-i386sco (CCLIBFLAGS): Define as empty. - Tue Mar 24 06:26:26 1992 Richard Kenner (kenner at vlsi1.ultra.nyu.edu) --- 4005,4008 ---- *************** *** 242,247 **** * cp-hash.h: Rebuilt. - * cp-type2.c (build_functional_cast): remove incorrect error message. - Sat Mar 21 15:43:04 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) --- 4227,4230 ---- *************** *** 807,812 **** * crtstuff.c: If defined, invoke INIT_SECTION_PREAMBLE. - Sun Mar 15 15:12:39 1992 Ron Guilmette (rfg at ncd.com) - * xm-sparcv4.h, x-sparcv4: New files. * configure (sparc-*-sysv4*): Use them. --- 4790,4793 ---- *************** *** 853,883 **** Sat Mar 14 10:12:39 1992 Michael Tiemann (tiemann@cygnus.com) - * cp-decl2.c (flag_this_is_variable): Define the value -2 to mean an - object of known type is being constructed. - * cp-decl.c (resolves_to_fixed_type_p): Test FLAG_THIS_IS_VARIABLE - for the value -2 instead of testing DECL_CONSTRUCTOR_P in case we - are looking at `current_class_decl'. - * cp-search.c (init_vbase_pointers): Set FLAG_THIS_IS_VARIABLE to -2 - instead of 0. - (build_vbase_vtables_init): Ditto. - * cp-*.c: All tests of FLAG_THIS_IS_VARIABLE changed to reflect the - new semantics. - - * cp-type2.c (build_functional_cast): remove incorrect error message. - - * cp-typeck.c (comptypes): Don't use IS_AGGR_TYPE_2; test explicitly - that both are RECORD_TYPE. - (build_binary_op_nodefault): Ditto. - (convert_for_assignment): Ditto. - * cp-cvt.c (convert_to_pointer): Ditto. - (convert_to_pointer_force): Ditto. - * cp-call.c (convert_harshness): Ditto. - - * cp-search.c (get_first_matching_virtual): Fix typo. - - * cp-tree.c (layout_basetypes): When warning about certain - inheritance relationships, only print "virtual" when the - inheritance is virtual. - * cp-spew.c (yylex): Fix some fencepost errors found by Chip Salzenberg. --- 4834,4837 ---- *************** *** 908,911 **** --- 4862,4869 ---- Merged in updated cp-* files for gcc-2.1. + Thu Mar 12 02:29:26 1992 Mike Stump (mrs@cygnus.com) + + * cp-type2.c (build_functional_cast): remove incorrect error message. + Fri Mar 13 14:54:23 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) *************** *** 2459,2462 **** --- 6417,6429 ---- whcih incurs warning message. + Sat Feb 22 20:49:45 1992 Michael Tiemann (tiemann at cygnus.com) + + * cp-decl.c (init_decl_processing,auto_function): New approach to + defining the default functions `operator new' and `operator delete'. + * cp-init.c (init_init_processing): Rest of changes here. + * libgcc2.c (_builtin_{new,delete,New}): Gone. + * libgcc2.c (_new_handler): New name for section that defines the + default new handler. + Sat Feb 22 02:09:55 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) *************** *** 2525,2528 **** --- 6492,6500 ---- functions. + Fri Feb 21 16:07:02 1992 Michael Tiemann (tiemann at cygnus.com) + + * cp-parse.y (get_current_declspecs): New function + (needed for naming sections). + Fri Feb 21 01:34:08 1992 Richard Stallman (rms@mole.gnu.ai.mit.edu) *************** *** 2652,2659 **** implicitly declaring ID. ! * cp-parse.y (primary): Simplify rules for calling assemble_external. * cp-decl.c (finish_function): For destructors, don't call expand_expr_stmt if EXPRSTMT is VOID_ZERO_NODE. Sun Dec 16 23:31:54 1992 Ron Guilmette (rfg at ncd.com) --- 6624,6635 ---- implicitly declaring ID. ! * cp-parse.y (primary): Simplify the rules for calling ! `assemble_external'. * cp-decl.c (finish_function): For destructors, don't call expand_expr_stmt if EXPRSTMT is VOID_ZERO_NODE. + + * cp-typeck.c (default_conversion): Parallel Jan 21 change in + c-typeck.c. Sun Dec 16 23:31:54 1992 Ron Guilmette (rfg at ncd.com) diff -rc2N gcc-2.1/Makefile.in gcc-2.2.1/Makefile.in *** gcc-2.1/Makefile.in Mon Mar 23 15:15:55 1992 --- gcc-2.2.1/Makefile.in Tue Jun 9 23:10:55 1992 *************** *** 26,32 **** .y.c: - .NOEXPORT: # This tells GNU Make version 3 - # not to put all the variables in the environment. - # Variables that exist for you to override. # See below for how to change them for certain systems. --- 26,29 ---- *************** *** 115,118 **** --- 112,122 ---- CROSS_TOOLS = + # There may be a premade insn-attrtab.c for this machine. + # (You could rebuild it with genattrtab as usual, but it takes a long time.) + # PREMADE_ATTRTAB is the file name of the file to use. + # PREMADE_ATTRTAB_MD is the md file it corresponds to. + PREMADE_ATTRTAB_MD = Makefile # Guaranteed not to cmp equal to md. + PREMADE_ATTRTAB = + target= ... `configure' substitutes actual target name here. xmake_file= ... `configure' substitutes actual x- file name here. *************** *** 178,181 **** --- 182,194 ---- EXTRA_OBJS = + # List of additional header files to install. + # Often this is edited directly by `configure'. + EXTRA_HEADERS = + + # Set this to `ld' to enable use of collect2. + # USE_COLLECT2 = + # It is convenient for configure to add the assignment at the beginning, + # so don't override it here. + # List of extra C and assembler files to add to libgcc1.a. # Assembler files should have names ending in `.asm'. *************** *** 203,207 **** # List of things which should already be built whenever we try to use gcc # to link anything. ! GCC_PARTS=$(GCC_PASSES) libgcc.a $(EXTRA_PROGRAMS) $(EXTRA_PARTS) # Change this to empty to prevent installing limits.h. --- 216,220 ---- # List of things which should already be built whenever we try to use gcc # to link anything. ! GCC_PARTS=$(GCC_PASSES) libgcc.a $(EXTRA_PROGRAMS) $(USE_COLLECT2) $(EXTRA_PARTS) # Change this to empty to prevent installing limits.h. *************** *** 247,250 **** --- 260,266 ---- all: all.indirect + # This tells GNU Make version 3 not to put all variables in the environment. + .NOEXPORT: + # sed inserts variable overrides after the following line. #### *************** *** 289,292 **** --- 305,309 ---- HOST_RTL = $(HOST_PREFIX)rtl.o HOST_RTLANAL = $(HOST_PREFIX)rtlanal.o + HOST_PRINT = $(HOST_PREFIX)print-rtl.o # Specify the directories to be searched for header files. *************** *** 348,356 **** stamp-flags stamp-config stamp-codes \ stamp-output stamp-recog stamp-emit stamp-extract stamp-peep \ ! stamp-attr stamp-attrtab \ genemit genoutput genrecog genextract genflags gencodes genconfig genpeep \ genattrtab genattr \ ! $(GCC_PASSES) $(EXTRA_PARTS) gcc-cross cccp cc1plus cc1obj enquire \ ! protoize unprotoize specs collect2 # Members of libgcc1.a. --- 365,373 ---- stamp-flags stamp-config stamp-codes \ stamp-output stamp-recog stamp-emit stamp-extract stamp-peep \ ! stamp-attr stamp-attrtab stamp-proto \ genemit genoutput genrecog genextract genflags gencodes genconfig genpeep \ genattrtab genattr \ ! $(GCC_PASSES) $(EXTRA_PARTS) $(EXTRA_PROGRAMS) gcc-cross cccp \ ! cc1plus cc1obj enquire protoize unprotoize specs collect2 $(USE_COLLECT2) # Members of libgcc1.a. *************** *** 374,378 **** # to programs compiled with gcc. USER_H = assert.h va-hp800.h va-i860.h va-mips.h va-pyr.h va-sparc.h \ ! va-spur.h va-m88k.h proto.h # All the header files that are installed for users from GCC itself. --- 391,395 ---- # to programs compiled with gcc. USER_H = assert.h va-hp800.h va-i860.h va-mips.h va-pyr.h va-sparc.h \ ! va-spur.h va-m88k.h va-i960.h proto.h $(EXTRA_HEADERS) # All the header files that are installed for users from GCC itself. *************** *** 394,398 **** .SUFFIXES: .in .def ! Makefile: $(srcdir)/Makefile.in $(srcdir)/configure \ $(srcdir)/config/$(xmake_file) $(srcdir)/config/$(tmake_file) sh config.status --- 411,415 ---- .SUFFIXES: .in .def ! Makefile: $(srcdir)/Makefile.in $(srcdir)/configure $(srcdir)/version.c \ $(srcdir)/config/$(xmake_file) $(srcdir)/config/$(tmake_file) sh config.status *************** *** 400,406 **** all.internal: start.encap rest.encap # This is what to compile if making a cross-compiler. ! all.cross: native gcc-cross # This is what must be made before installing GCC and converting libraries. ! start.encap: native gcc $(LIBGCC1_TARGET) # Use this to make a GCC that will be used only to recompile GCC. for-bootstrap: start.encap libgcc.a --- 417,423 ---- all.internal: start.encap rest.encap # This is what to compile if making a cross-compiler. ! all.cross: native gcc-cross cross-test $(EXTRA_PARTS) # This is what must be made before installing GCC and converting libraries. ! start.encap: native gcc specs $(LIBGCC1_TARGET) # Use this to make a GCC that will be used only to recompile GCC. for-bootstrap: start.encap libgcc.a *************** *** 409,413 **** # This is what is made with the host's compiler # whether making a cross compiler or not. ! native: config.status cpp $(LANGUAGES) $(EXTRA_PASSES) $(EXTRA_PROGRAMS) # Define the names for selecting languages in LANGUAGES. --- 426,430 ---- # This is what is made with the host's compiler # whether making a cross compiler or not. ! native: config.status cpp $(LANGUAGES) $(EXTRA_PASSES) $(EXTRA_PROGRAMS) $(USE_COLLECT2) # Define the names for selecting languages in LANGUAGES. *************** *** 429,432 **** --- 446,462 ---- fi + # On the target machine, finish building a cross compiler. + # This does the things that can't be done on the host machine. + rest.cross: libgcc.a float.h specs + + # Verify that it works to compile and link cross-test. + # If it does, then there are sufficient replacements for libgcc1.a. + cross-test: cross-test.o native gcc-cross + $(GCC_FOR_TARGET) $(GCC_CFLAGS) cross-test.o -o $@ + cross-test.o: cross-test.c native gcc-cross + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(ALL_CPPFLAGS) -c $(srcdir)/cross-test.c + + # Recompile all the language-independent object files. + # This is used only if the user explicitly asks for it. compilations: ${OBJS} *************** *** 435,439 **** # Go via `gccnew' to avoid `file busy' if $(CC) is `gcc'. mv -f gccnew gcc ! # Dump a specs file to make -B./ read these specs over installed ones ./gcc -dumpspecs > specs --- 465,471 ---- # Go via `gccnew' to avoid `file busy' if $(CC) is `gcc'. mv -f gccnew gcc ! ! # Dump a specs file to make -B./ read these specs over installed ones. ! specs: gcc ./gcc -dumpspecs > specs *************** *** 462,465 **** --- 494,498 ---- $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(ENQUIRE_LDFLAGS) enquire.o -o $@ enquire.o: $(srcdir)/enquire.c $(GCC_PASSES) + -if [ "$(srcdir)" != "." ]; then rm -f enquire.c; else true; fi -cp $(srcdir)/enquire.c . > /dev/null 2>&1 # Breaking this line caused a problem with one version of GNU make. *************** *** 626,630 **** # C language specific files. ! c-parse.o : $(srcdir)/c-parse.c $(CONFIG_H) $(TREE_H) c-lex.h c-tree.h input.h flags.h $(CC) $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) -c $(srcdir)/c-parse.c $(srcdir)/c-parse.c $(srcdir)/c-parse.h: $(srcdir)/c-parse.y --- 659,664 ---- # C language specific files. ! c-parse.o : $(srcdir)/c-parse.c $(CONFIG_H) $(TREE_H) c-lex.h c-parse.h \ ! c-tree.h input.h flags.h $(CC) $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) -c $(srcdir)/c-parse.c $(srcdir)/c-parse.c $(srcdir)/c-parse.h: $(srcdir)/c-parse.y *************** *** 677,680 **** --- 711,719 ---- cp-pt.o : cp-pt.c $(CONFIG_H) $(CPLUS_TREE_H) cp-decl.h cp-parse.h + # To make a configuration always use collect2, set USE_COLLECT2 to ld. + ld: collect2 + rm -f ld + ln collect2 ld + collect2 : collect2.o version.o $(LIBDEPS) $(CC) $(ALL_CFLAGS) $(LDFLAGS) -o collect2 collect2.o version.o $(LIBS) *************** *** 723,726 **** --- 762,767 ---- toplev.o : toplev.c $(CONFIG_H) $(TREE_H) $(RTL_H) flags.h input.h \ insn-attr.h xcoffout.h + $(CC) $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(MAYBE_USE_COLLECT2) -c `echo $(srcdir)/toplev.c | sed 's,^\./,,'` rtl.o : rtl.c $(CONFIG_H) $(RTL_H) *************** *** 729,733 **** rtlanal.o : rtlanal.c $(CONFIG_H) $(RTL_H) ! varasm.o : varasm.c $(CONFIG_H) $(TREE_H) $(RTL_H) flags.h \ insn-codes.h expr.h hard-reg-set.h regs.h xcoffout.h function.o : function.c $(CONFIG_H) $(RTL_H) $(TREE_H) flags.h function.h \ --- 770,774 ---- rtlanal.o : rtlanal.c $(CONFIG_H) $(RTL_H) ! varasm.o : varasm.c $(CONFIG_H) $(TREE_H) $(RTL_H) flags.h defaults.h \ insn-codes.h expr.h hard-reg-set.h regs.h xcoffout.h function.o : function.c $(CONFIG_H) $(RTL_H) $(TREE_H) flags.h function.h \ *************** *** 802,806 **** reg-stack.o : reg-stack.c $(CONFIG_H) $(RTL_H) $(TREE_H) \ regs.h hard-reg-set.h flags.h insn-config.h ! aux-output.o : aux-output.c $(CONFIG_H) \ $(RTL_H) regs.h hard-reg-set.h real.h insn-config.h conditions.h \ --- 843,847 ---- reg-stack.o : reg-stack.c $(CONFIG_H) $(RTL_H) $(TREE_H) \ regs.h hard-reg-set.h flags.h insn-config.h ! aux-output.o : aux-output.c $(CONFIG_H) \ $(RTL_H) regs.h hard-reg-set.h real.h insn-config.h conditions.h \ *************** *** 903,907 **** insn-attrtab.c: stamp-attrtab ; stamp-attrtab : md genattrtab $(srcdir)/move-if-change ! ./genattrtab md > tmp-attrtab.c $(srcdir)/move-if-change tmp-attrtab.c insn-attrtab.c touch stamp-attrtab --- 944,954 ---- insn-attrtab.c: stamp-attrtab ; stamp-attrtab : md genattrtab $(srcdir)/move-if-change ! if cmp -s $(PREMADE_ATTRTAB_MD) md; \ ! then \ ! echo Using $(PREMADE_ATTRTAB); \ ! cp $(PREMADE_ATTRTAB) tmp-attrtab.c; \ ! else \ ! ./genattrtab md > tmp-attrtab.c; \ ! fi $(srcdir)/move-if-change tmp-attrtab.c insn-attrtab.c touch stamp-attrtab *************** *** 967,971 **** genextract.o $(HOST_RTL) $(HOST_LIBS) ! genextract.o : genextract.c $(RTL_H) config.h $(HOST_CC) -c $(HOST_CFLAGS) $(HOST_CPPFLAGS) $(INCLUDES) $(srcdir)/genextract.c --- 1014,1018 ---- genextract.o $(HOST_RTL) $(HOST_LIBS) ! genextract.o : genextract.c $(RTL_H) config.h insn-config.h $(HOST_CC) -c $(HOST_CFLAGS) $(HOST_CPPFLAGS) $(INCLUDES) $(srcdir)/genextract.c *************** *** 984,990 **** $(HOST_CC) -c $(HOST_CFLAGS) $(HOST_CPPFLAGS) $(INCLUDES) $(srcdir)/genattr.c ! genattrtab : genattrtab.o $(HOST_RTL) $(HOST_RTLANAL) $(HOST_LIBDEPS) $(HOST_CC) $(HOST_CFLAGS) $(HOST_LDFLAGS) -o genattrtab \ ! genattrtab.o $(HOST_RTL) $(HOST_RTLANAL) $(HOST_LIBS) genattrtab.o : genattrtab.c $(RTL_H) config.h insn-config.h --- 1031,1037 ---- $(HOST_CC) -c $(HOST_CFLAGS) $(HOST_CPPFLAGS) $(INCLUDES) $(srcdir)/genattr.c ! genattrtab : genattrtab.o $(HOST_RTL) $(HOST_PRINT) $(HOST_RTLANAL) $(HOST_LIBDEPS) $(HOST_CC) $(HOST_CFLAGS) $(HOST_LDFLAGS) -o genattrtab \ ! genattrtab.o $(HOST_RTL) $(HOST_PRINT) $(HOST_RTLANAL) $(HOST_LIBS) genattrtab.o : genattrtab.c $(RTL_H) config.h insn-config.h *************** *** 1007,1010 **** --- 1054,1062 ---- $(HOST_CC) -c $(HOST_CFLAGS) $(HOST_CPPFLAGS) $(INCLUDES) $(HOST_PREFIX)rtl.c + $(HOST_PREFIX_1)print-rtl.o: $(srcdir)/print-rtl.c $(CONFIG_H) $(RTL_H) + rm -f $(HOST_PREFIX)print-rtl.c + cp $(srcdir)/print-rtl.c $(HOST_PREFIX)print-rtl.c + $(HOST_CC) -c $(HOST_CFLAGS) $(HOST_CPPFLAGS) $(INCLUDES) $(HOST_PREFIX)print-rtl.c + $(HOST_PREFIX_1)rtlanal.o: $(srcdir)/rtlanal.c $(CONFIG_H) $(RTL_H) rm -f $(HOST_PREFIX)rtlanal.c *************** *** 1059,1063 **** $(CC) $(ALL_CFLAGS) $(LDFLAGS) \ protoize.o getopt.o getopt1.o getpwd.o version.o $(LIBS) -o $@ ! protoize.o: $(srcdir)/protoize.c getopt.h $(CONFIG_H) $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ -DGCC_INCLUDE_DIR=\"$(libsubdir)/include\" \ --- 1111,1123 ---- $(CC) $(ALL_CFLAGS) $(LDFLAGS) \ protoize.o getopt.o getopt1.o getpwd.o version.o $(LIBS) -o $@ ! protoize.o: stamp-proto ; ! ! unprotoize: unprotoize.o getopt.o getopt1.o getpwd.o version.o $(LIBDEPS) ! $(CC) $(ALL_CFLAGS) $(LDFLAGS) \ ! unprotoize.o getopt.o getopt1.o getpwd.o version.o $(LIBS) -o $@ ! unprotoize.o: stamp-proto ; ! ! stamp-proto: $(srcdir)/protoize.c getopt.h $(CONFIG_H) ! touch stamp-proto $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ -DGCC_INCLUDE_DIR=\"$(libsubdir)/include\" \ *************** *** 1066,1076 **** -DLOCAL_INCLUDE_DIR=\"$(prefix)/include\" \ -DSTD_PROTO_DIR=\"$(libsubdir)\" \ ! $(srcdir)/protoize.c ! ! unprotoize: unprotoize.o getopt.o getopt1.o getpwd.o version.o $(LIBDEPS) ! $(CC) $(ALL_CFLAGS) $(LDFLAGS) \ ! unprotoize.o getopt.o getopt1.o getpwd.o version.o $(LIBS) -o $@ ! unprotoize.o: $(srcdir)/protoize.c getopt.h $(CONFIG_H) ! cp $(srcdir)/protoize.c unprotoize.c $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ -DGCC_INCLUDE_DIR=\"$(libsubdir)/include\" \ --- 1126,1131 ---- -DLOCAL_INCLUDE_DIR=\"$(prefix)/include\" \ -DSTD_PROTO_DIR=\"$(libsubdir)\" \ ! -DUNPROTOIZE $(srcdir)/protoize.c ! mv protoize.o unprotoize.o $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ -DGCC_INCLUDE_DIR=\"$(libsubdir)/include\" \ *************** *** 1079,1084 **** -DLOCAL_INCLUDE_DIR=\"$(prefix)/include\" \ -DSTD_PROTO_DIR=\"$(libsubdir)\" \ ! -DUNPROTOIZE unprotoize.c ! rm -f unprotoize.c getopt.o: $(srcdir)/getopt.c getopt.h --- 1134,1138 ---- -DLOCAL_INCLUDE_DIR=\"$(prefix)/include\" \ -DSTD_PROTO_DIR=\"$(libsubdir)\" \ ! $(srcdir)/protoize.c getopt.o: $(srcdir)/getopt.c getopt.h *************** *** 1091,1094 **** --- 1145,1149 ---- | grep -v '^#' \ | awk 'NF > 0 {print}' > tmp-proto.1 + -rm -f protoize.1 mv tmp-proto.1 protoize.1 *************** *** 1097,1126 **** | grep -v '^#' \ | awk 'NF > 0 {print}' > tmp-unproto.1 mv tmp-unproto.1 unprotoize.1 - SYSCALLS.c : $(srcdir)/sys-types.h $(srcdir)/sys-protos.h - cat $(srcdir)/sys-types.h $(srcdir)/sys-protos.h >$@ - # This info describes the target machine, so compile with GCC just built. ! SYSCALLS.c.X: SYSCALLS.c $(GCC_PASSES) $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ ! -aux-info $@ -S -o /dev/null SYSCALLS.c # Remake the info files. ! doc: $(srcdir)/cpp.info $(srcdir)/gcc.info ! $(srcdir)/cpp.info: $(srcdir)/cpp.texi makeinfo `echo $(srcdir)/cpp.texi | sed 's,^\./,,'` ! #$(srcdir)/gplus.info: $(srcdir)/gplus.texi # makeinfo `echo $(srcdir)/gplus.texi | sed 's,^\./,,'` ! $(srcdir)/gcc.info: $(srcdir)/gcc.texi makeinfo `echo $(srcdir)/gcc.texi | sed 's,^\./,,'` # Deletion of files made during compilation. # There are four levels of this: ! # `mostlyclean', `clean', `cleanconfig' and `realclean'. # `mostlyclean' is useful while working on a particular type of machine. # It deletes most, but not all, of the files made by compilation. --- 1152,1209 ---- | grep -v '^#' \ | awk 'NF > 0 {print}' > tmp-unproto.1 + -rm -f unprotoize.1 mv tmp-unproto.1 unprotoize.1 # This info describes the target machine, so compile with GCC just built. ! SYSCALLS.c.X: $(srcdir)/sys-types.h $(srcdir)/sys-protos.h $(GCC_PASSES) ! -rm -f SYSCALLS.c tmp-SYSCALLS.s ! cat $(srcdir)/sys-types.h $(srcdir)/sys-protos.h > SYSCALLS.c $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ ! -aux-info $@ -S -o tmp-SYSCALLS.s SYSCALLS.c ! -rm -f SYSCALLS.c tmp-SYSCALLS.s ! ! test-protoize-simple: ./protoize ./unprotoize $(GCC_PASSES) ! -rm -f tmp-proto.[cso] ! cp $(srcdir)/protoize.c tmp-proto.c ! chmod u+w tmp-proto.c ! ./protoize -N -B ./ -x getopt.h -c "-B./ -Wall -Wwrite-strings \ ! $(CFLAGS) $(INCLUDES) \ ! -DGCC_INCLUDE_DIR=0 \ ! -DGPLUSPLUS_INCLUDE_DIR=0 \ ! -DCROSS_INCLUDE_DIR=0 \ ! -DSTD_PROTO_DIR=0" tmp-proto.c ! @echo '**********' Expect 402 lines of differences. ! -diff $(srcdir)/protoize.c tmp-proto.c > tmp-proto.diff ! -wc -l tmp-proto.diff ! ./unprotoize -N -x getopt.h -c "-B./ -Wall -Wwrite-strings \ ! $(CFLAGS) $(INCLUDES) \ ! -DGCC_INCLUDE_DIR=0 \ ! -DGPLUSPLUS_INCLUDE_DIR=0 \ ! -DCROSS_INCLUDE_DIR=0 \ ! -DSTD_PROTO_DIR=0" tmp-proto.c ! @echo Expect zero differences. ! diff $(srcdir)/protoize.c tmp-proto.c | cat ! -rm -f tmp-proto.[cso] # Remake the info files. ! doc: $(srcdir)/cpp.info $(srcdir)/gcc.info $(srcdir)/INSTALL ! $(srcdir)/cpp.info: cpp.texi makeinfo `echo $(srcdir)/cpp.texi | sed 's,^\./,,'` ! #$(srcdir)/gplus.info: gplus.texi # makeinfo `echo $(srcdir)/gplus.texi | sed 's,^\./,,'` ! $(srcdir)/gcc.info: gcc.texi extend.texi install.texi invoke.texi \ ! md.texi rtl.texi tm.texi makeinfo `echo $(srcdir)/gcc.texi | sed 's,^\./,,'` + + $(srcdir)/INSTALL: install1.texi install.texi + makeinfo --no-header `echo $(srcdir)/install1.texi | sed 's,^\./,,'` # Deletion of files made during compilation. # There are four levels of this: ! # `mostlyclean', `clean', `distclean' and `realclean'. # `mostlyclean' is useful while working on a particular type of machine. # It deletes most, but not all, of the files made by compilation. *************** *** 1127,1133 **** # It does not delete libgcc.a or its parts, so it won't have to be recompiled. # `clean' deletes everything made by running `make all'. ! # `cleanconfig' also deletes the files made by config. # `realclean' also deletes everything that could be regenerated automatically. mostlyclean: -rm -f $(STAGESTUFF) --- 1210,1217 ---- # It does not delete libgcc.a or its parts, so it won't have to be recompiled. # `clean' deletes everything made by running `make all'. ! # `distclean' also deletes the files made by config. # `realclean' also deletes everything that could be regenerated automatically. + mostlyclean: -rm -f $(STAGESTUFF) *************** *** 1140,1144 **** for name in $(LIB1FUNCS); do rm -f $${name}.c; done # Delete other temporary files. ! -rm -f tmp-float.h tmp-*proto.1 tmp-gcc.xtar.Z tmp-limits.h gccnew # Delete the stamp files. -rm -f stamp-* tmp-* --- 1224,1229 ---- for name in $(LIB1FUNCS); do rm -f $${name}.c; done # Delete other temporary files. ! -rm -f tmp-float.h tmp-gcc.xtar.Z tmp-limits.h gccnew ! -rm -f tmp-foo1 tmp-foo2 tmp-proto.* tmp-unproto.1 tmp-SYSCALLS.s # Delete the stamp files. -rm -f stamp-* tmp-* *************** *** 1147,1151 **** -rm -f *.dbr *.jump2 *.sched *.cse2 *.sched2 *.stack # Delete some files made during installation. ! -rm -f specs float.h enquire SYSCALLS.c SYSCALLS.c.X -rm -f collect collect2 ld mips-tfile mips-tdump alloca.s # Delete unwanted output files from TeX. --- 1232,1236 ---- -rm -f *.dbr *.jump2 *.sched *.cse2 *.sched2 *.stack # Delete some files made during installation. ! -rm -f specs float.h enquire SYSCALLS.c.X SYSCALLS.c -rm -f collect collect2 ld mips-tfile mips-tdump alloca.s # Delete unwanted output files from TeX. *************** *** 1156,1169 **** -rm -f core ! # delete all files made by compilation. clean: mostlyclean ! -rm -f libgcc.a libgcc1.a libgcc2.a libgcc2.ready ! -rm -fr stage1 stage2 stage3 stage4 ! # This is used to get rid of everything found in the source dir ! # that shouldn't be in the distribution. distclean: clean -rm -f tm.h aux-output.c config.h md config.status tconfig.h ! -rm -f Makefile *.dvi *.oaux # Delete anything likely to be found in the source directory --- 1241,1260 ---- -rm -f core ! # Delete all files made by compilation ! # that don't exist in the distribution. clean: mostlyclean ! # It may not be quite desirable to delete unprotoize.c here, ! # but the spec for `make clean' requires it. ! # Using unprotoize.c is not quite right in the first place, ! # but what better way is there? ! -rm -f libgcc.a libgcc1.a libgcc2.a libgcc2.ready libgcc1.null ! -rm -f *.dvi ! # Delete all files that users would normally create ! # while building and installing GCC. distclean: clean -rm -f tm.h aux-output.c config.h md config.status tconfig.h ! -rm -f Makefile *.oaux ! -rm -fr stage1 stage2 stage3 stage4 # Delete anything likely to be found in the source directory *************** *** 1171,1176 **** extraclean: distclean -rm -rf =* #* *~* config/=* config/#* config/*~* ! -rm -f *.dvi *.oaux patch* *.orig *.rej *.d *.Z *.tar ! -rm -f *.s *.s[0-9] *.i # Get rid of every file that's generated from some other file. --- 1262,1268 ---- extraclean: distclean -rm -rf =* #* *~* config/=* config/#* config/*~* ! -rm -f patch* *.orig *.rej config/patch* config/*.orig config/*.rej ! -rm -f *.dvi *.oaux *.d *.Z *.tar *.xtar ! -rm -f *.s *.s[0-9] *.i install1.texi # Get rid of every file that's generated from some other file. *************** *** 1259,1271 **** # Create the installation directory. install-dir: ! if [ -d $(libdir) ] ; then true ; else mkdir $(libdir) ; fi ! if [ -d $(libdir)/gcc-lib ] ; then true ; else mkdir $(libdir)/gcc-lib ; fi ! if [ -d $(libdir)/gcc-lib/$(target) ] ; then true ; else mkdir $(libdir)/gcc-lib/$(target) ; fi ! if [ -d $(libdir)/gcc-lib/$(target)/$(version) ] ; then true ; else mkdir $(libdir)/gcc-lib/$(target)/$(version) ; fi ! if [ -d $(bindir) ] ; then true ; else mkdir $(bindir) ; fi # We don't use mkdir -p to create the parents of mandir, # because some systems don't support it. # Instead, we use this technique to create the immediate parent of mandir. ! parent=`echo $(mandir)|sed -e 's@/[^/]*$$@@'`; \ if [ -d $$parent ] ; then true ; else mkdir $$parent ; fi -if [ -d $(mandir) ] ; then true ; else mkdir $(mandir) ; fi --- 1351,1365 ---- # Create the installation directory. install-dir: ! -if [ -d $(libdir) ] ; then true ; else mkdir $(libdir) ; fi ! -if [ -d $(libdir)/gcc-lib ] ; then true ; else mkdir $(libdir)/gcc-lib ; fi ! -if [ -d $(libdir)/gcc-lib/include ] ; then true ; else mkdir $(libdir)/gcc-lib/include ; fi ! -if [ -d $(libdir)/gcc-lib/$(target) ] ; then true ; else mkdir $(libdir)/gcc-lib/$(target) ; fi ! -if [ -d $(libdir)/gcc-lib/$(target)/$(version) ] ; then true ; else mkdir $(libdir)/gcc-lib/$(target)/$(version) ; fi ! -if [ -d $(libdir)/gcc-lib/$(target)/$(version)/include ] ; then true ; else mkdir $(libdir)/gcc-lib/$(target)/$(version)/include ; fi ! -if [ -d $(bindir) ] ; then true ; else mkdir $(bindir) ; fi # We don't use mkdir -p to create the parents of mandir, # because some systems don't support it. # Instead, we use this technique to create the immediate parent of mandir. ! -parent=`echo $(mandir)|sed -e 's@/[^/]*$$@@'`; \ if [ -d $$parent ] ; then true ; else mkdir $$parent ; fi -if [ -d $(mandir) ] ; then true ; else mkdir $(mandir) ; fi *************** *** 1280,1284 **** fi; \ done ! for file in $(EXTRA_PASSES) $(EXTRA_PARTS) $(EXTRA_PROGRAMS) ..; do \ if [ x"$$file" != x.. ]; then \ rm -f $(libsubdir)/$$file; \ --- 1374,1378 ---- fi; \ done ! for file in $(EXTRA_PASSES) $(EXTRA_PARTS) $(EXTRA_PROGRAMS) $(USE_COLLECT2) ..; do \ if [ x"$$file" != x.. ]; then \ rm -f $(libsubdir)/$$file; \ *************** *** 1303,1307 **** --- 1397,1403 ---- mv $(bindir)/gcc-$(target)-1 $(bindir)/gcc-$(target); \ fi + -rm -f $(bindir)/c++ $(INSTALL_PROGRAM) $(srcdir)/c++ $(bindir)/c++ + -rm -f $(bindir)/g++ $(INSTALL_PROGRAM) $(srcdir)/g++ $(bindir)/g++ -rm -f $(libsubdir)/cpp *************** *** 1322,1342 **** protoize.1 unprotoize.1 $(srcdir)/g++.1 -rm -f $(mandir)/gcc$(manext) ! $(INSTALL_DATA) $(srcdir)/gcc.1 $(mandir)/gcc$(manext) ! chmod a-x $(mandir)/gcc$(manext) -rm -f $(mandir)/cccp$(manext) ! $(INSTALL_DATA) $(srcdir)/cccp.1 $(mandir)/cccp$(manext) ! chmod a-x $(mandir)/cccp$(manext) -rm -f $(mandir)/protoize$(manext) ! $(INSTALL_DATA) protoize.1 $(mandir)/protoize$(manext) ! chmod a-x $(mandir)/protoize$(manext) -rm -f $(mandir)/unprotoize$(manext) ! $(INSTALL_DATA) unprotoize.1 $(mandir)/unprotoize$(manext) ! chmod a-x $(mandir)/unprotoize$(manext) -rm -f $(mandir)/g++$(manext) ! $(INSTALL_DATA) $(srcdir)/g++.1 $(mandir)/g++$(manext) ! chmod a-x $(mandir)/g++$(manext) # Install the library. ! install-libgcc: libgcc.a -if [ -f libgcc.a ] ; then \ rm -f $(libsubdir)/libgcc.a; \ --- 1418,1438 ---- protoize.1 unprotoize.1 $(srcdir)/g++.1 -rm -f $(mandir)/gcc$(manext) ! -$(INSTALL_DATA) $(srcdir)/gcc.1 $(mandir)/gcc$(manext) ! -chmod a-x $(mandir)/gcc$(manext) -rm -f $(mandir)/cccp$(manext) ! -$(INSTALL_DATA) $(srcdir)/cccp.1 $(mandir)/cccp$(manext) ! -chmod a-x $(mandir)/cccp$(manext) -rm -f $(mandir)/protoize$(manext) ! -$(INSTALL_DATA) protoize.1 $(mandir)/protoize$(manext) ! -chmod a-x $(mandir)/protoize$(manext) -rm -f $(mandir)/unprotoize$(manext) ! -$(INSTALL_DATA) unprotoize.1 $(mandir)/unprotoize$(manext) ! -chmod a-x $(mandir)/unprotoize$(manext) -rm -f $(mandir)/g++$(manext) ! -$(INSTALL_DATA) $(srcdir)/g++.1 $(mandir)/g++$(manext) ! -chmod a-x $(mandir)/g++$(manext) # Install the library. ! install-libgcc: libgcc.a install-dir -if [ -f libgcc.a ] ; then \ rm -f $(libsubdir)/libgcc.a; \ *************** *** 1351,1355 **** # Install float.h for native compiler. ! install-float-h: float.h -rm -f $(libsubdir)/include/float.h $(INSTALL_DATA) float.h $(libsubdir)/include/float.h --- 1447,1451 ---- # Install float.h for native compiler. ! install-float-h: float.h install-dir -rm -f $(libsubdir)/include/float.h $(INSTALL_DATA) float.h $(libsubdir)/include/float.h *************** *** 1357,1361 **** # Install limits.h, optionally inheriting from the standard system version. ! install-limits-h: limits.h limitx.h -rm -f $(libsubdir)/include/limits.h tmp-limits.h if [ -f /usr/include/limits.h ] ; then \ --- 1453,1457 ---- # Install limits.h, optionally inheriting from the standard system version. ! install-limits-h: limits.h limitx.h install-dir -rm -f $(libsubdir)/include/limits.h tmp-limits.h if [ -f /usr/include/limits.h ] ; then \ *************** *** 1370,1374 **** # Install the fixed headers that are the same for all machines. install-common-headers: install-dir $(USER_H) gvarargs.h gstdarg.h gstddef.h ! if [ -d $(libsubdir)/include ] ; then true ; else mkdir $(libsubdir)/include ; fi -chmod ugo+rx $(libsubdir)/include # Must compute $(libsubdir) before the cd; the awk script won't work after. --- 1466,1470 ---- # Install the fixed headers that are the same for all machines. install-common-headers: install-dir $(USER_H) gvarargs.h gstdarg.h gstddef.h ! -if [ -d $(libsubdir)/include ] ; then true ; else mkdir $(libsubdir)/include ; fi -chmod ugo+rx $(libsubdir)/include # Must compute $(libsubdir) before the cd; the awk script won't work after. *************** *** 1392,1399 **** # so that fixinc.svr4 can get at it if necessary. # If the dirs are the same, this won't do anything. ! -cp $(srcdir)/byteorder.h . # $(libsubdir)/include: ! # if [ -d $(libsubdir)/include ] ; then true ; else mkdir $(libsubdir)/include ; fi # -chmod ugo+rx $(libsubdir)/include --- 1488,1497 ---- # so that fixinc.svr4 can get at it if necessary. # If the dirs are the same, this won't do anything. ! # Delete file first in case it is read-only ! -if [ "$(srcdir)" != "." ]; then rm -f byteorder.h; else true; fi ! -cp $(srcdir)/byteorder.h . > /dev/null 2>&1 # $(libsubdir)/include: ! # -if [ -d $(libsubdir)/include ] ; then true ; else mkdir $(libsubdir)/include ; fi # -chmod ugo+rx $(libsubdir)/include *************** *** 1470,1474 **** #gcc-$(version).tar: ! gcc.xtar: -rm -rf gcc-$(version) tmp # Put all the files in a temporary subdirectory --- 1568,1582 ---- #gcc-$(version).tar: ! gcc.xtar: doc ! if grep -s "for version ${version}" gcc.texi; \ ! then true; \ ! else echo "You must update the version number in \`gcc.texi'"; exit 1;\ ! fi ! # Update the version number in README ! awk '$$1 " " $$2 " " $$3 == "This directory contains" \ ! { $$6 = version; print $$0 } \ ! $$1 " " $$2 " " $$3 != "This directory contains"' \ ! version=$(version) README > tmp.README ! mv tmp.README README -rm -rf gcc-$(version) tmp # Put all the files in a temporary subdirectory *************** *** 1477,1485 **** mkdir tmp/config for file in *[0-9a-zA-Z+]; do \ ! ln $$file tmp || cp $$file tmp; \ done cd config; \ for file in *[0-9a-zA-Z+]; do \ ! ln $$file ../tmp/config || cp $$file ../tmp/config; \ done ln .gdbinit tmp --- 1585,1593 ---- mkdir tmp/config for file in *[0-9a-zA-Z+]; do \ ! ln $$file tmp > /dev/null 2>&1 || cp $$file tmp; \ done cd config; \ for file in *[0-9a-zA-Z+]; do \ ! ln $$file ../tmp/config >/dev/null 2>&1 || cp $$file ../tmp/config; \ done ln .gdbinit tmp *************** *** 1510,1515 **** make clean # You must then run config to set up for compilation. ! ! bootstrap: all force $(MAKE) stage1 # This used to define ALLOCA as empty, but that would lead to bad results --- 1618,1626 ---- make clean # You must then run config to set up for compilation. ! bootstrap: force ! # Only build the C compiler for stage1, because that is the only one that ! # we can guarantee will build with the native compiler, and also it is the ! # only thing useful for building stage2. ! $(MAKE) LANGUAGES=c $(MAKE) stage1 # This used to define ALLOCA as empty, but that would lead to bad results *************** *** 1530,1533 **** --- 1641,1664 ---- $(MAKE) CC="stage2/gcc -Bstage2/" CFLAGS="$(BOOT_CFLAGS)" libdir=$(libdir) LANGUAGES="$(LANGUAGES)" + # Compare the object files in the current directory with those in the + # stage2 directory. + + compare: force + for file in *.o; do \ + tail +10c $$file > tmp-foo1; \ + tail +10c stage2/$$file > tmp-foo2; \ + cmp tmp-foo1 tmp-foo2 || echo $$file differs; \ + done + -rm -f tmp-foo* + + # Similar, but compare with stage3 directory + compare3: force + for file in *.o; do \ + tail +10c $$file > tmp-foo1; \ + tail +10c stage3/$$file > tmp-foo2; \ + cmp tmp-foo1 tmp-foo2 || echo $$file differs; \ + done + -rm -f tmp-foo* + # Copy the object files from a particular stage into a subdirectory. stage1: force *************** *** 1546,1550 **** stage3: force ! if [ -d stage3 ] ; then true ; else mkdir stage3 ; fi -mv $(STAGESTUFF) stage3 -rm -f stage3/libgcc.a --- 1677,1681 ---- stage3: force ! -if [ -d stage3 ] ; then true ; else mkdir stage3 ; fi -mv $(STAGESTUFF) stage3 -rm -f stage3/libgcc.a *************** *** 1553,1557 **** stage4: force ! if [ -d stage4 ] ; then true ; else mkdir stage4 ; fi -mv $(STAGESTUFF) stage4 -rm -f stage4/libgcc.a --- 1684,1688 ---- stage4: force ! -if [ -d stage4 ] ; then true ; else mkdir stage4 ; fi -mv $(STAGESTUFF) stage4 -rm -f stage4/libgcc.a *************** *** 1563,1567 **** # that is pretty sure to work, and you are short of disk space. risky-stage1: force ! if [ -d stage1 ] ; then true ; else mkdir stage1 ; fi -mv cc1 cpp cccp gcc stage1 -rm -f stage1/libgcc.a --- 1694,1698 ---- # that is pretty sure to work, and you are short of disk space. risky-stage1: force ! -if [ -d stage1 ] ; then true ; else mkdir stage1 ; fi -mv cc1 cpp cccp gcc stage1 -rm -f stage1/libgcc.a *************** *** 1570,1574 **** risky-stage2: force ! if [ -d stage2 ] ; then true ; else mkdir stage2 ; fi -mv cc1 cpp cccp gcc stage2 -rm -f stage2/libgcc.a --- 1701,1705 ---- risky-stage2: force ! -if [ -d stage2 ] ; then true ; else mkdir stage2 ; fi -mv cc1 cpp cccp gcc stage2 -rm -f stage2/libgcc.a *************** *** 1577,1581 **** risky-stage3: force ! if [ -d stage3 ] ; then true ; else mkdir stage3 ; fi -mv cc1 cpp cccp gcc stage3 -rm -f stage3/libgcc.a --- 1708,1712 ---- risky-stage3: force ! -if [ -d stage3 ] ; then true ; else mkdir stage3 ; fi -mv cc1 cpp cccp gcc stage3 -rm -f stage3/libgcc.a *************** *** 1584,1588 **** risky-stage4: force ! if [ -d stage4 ] ; then true ; else mkdir stage4 ; fi -mv cc1 cpp cccp gcc stage4 -rm -f stage4/libgcc.a --- 1715,1719 ---- risky-stage4: force ! -if [ -d stage4 ] ; then true ; else mkdir stage4 ; fi -mv cc1 cpp cccp gcc stage4 -rm -f stage4/libgcc.a diff -rc2N gcc-2.1/README gcc-2.2.1/README *** gcc-2.1/README Mon Mar 23 01:00:40 1992 --- gcc-2.2.1/README Tue Jun 9 22:40:14 1992 *************** *** 1,4 **** ! This directory contains the version 2.1 release of the GNU C compiler. ! This is the second test release of GCC version 2. See the file gcc.texi (together with other files that it includes) for --- 1,4 ---- ! This directory contains the version 2.2.1 release of the GNU C compiler. ! This is a beta test release and we expect it to have a number of bugs. See the file gcc.texi (together with other files that it includes) for *************** *** 14,19 **** permission. ! The files print-self.c and print-self1.c are not part of GCC. They are programs that print themselves on standard output. They were written by Dario Dariol and Giovanni Cozzi, and are ! included for your hacking pleasure. --- 14,25 ---- permission. ! See the Bugs chapter of the GCC Manual for how to report bugs ! usefully. An online readable version of the manual is in the files ! gcc.info*. ! ! The files pself.c and pself1.c are not part of GCC. They are programs that print themselves on standard output. They were written by Dario Dariol and Giovanni Cozzi, and are ! included for your hacking pleasure. Likewise pself2.c ! (Who is the author of that?) and pself3.c (by Vlad Taeerov and Rashit ! Fakhreyev). diff -rc2N gcc-2.1/README.APOLLO gcc-2.2.1/README.APOLLO *** gcc-2.1/README.APOLLO --- gcc-2.2.1/README.APOLLO Tue Mar 31 17:48:23 1992 *************** *** 0 **** --- 1,112 ---- + README.apollo + + Building GCC 2.0 for 680x0 based Apollo systems requires the GNU + assembler (GAS) version 1.38.1, with John Vasta's patches applied. + + If you haven't done so yet, get `gas-1.38.1.tar.Z' from your favourite + GNU distribution site. Furthermore, get `apollo-gas-1.38.1.diffs' + from `labrea.stanford.edu:/pub/gnu', apply the patches, compile and + install gas (under the name as). This should go through without any + problems. + + After switching into the BSD environment, you can configure GCC 2.0 + with the command + + % ./configure m68k-apollo-bsd + + The Apollo's `/usr/include/setjmp.h' uses a nonstandard `#options()' + construct. You should create a local copy of this file and remove + these constructs from the declarations of SIGSETJMP and SIGLONGJMP. + + The Apollo's `/usr/include/sys/types.h' (BSD Version) doesn't allow + to test for the definition of `size_t'. This should be fixed by + + #ifndef _SIZE_T + #define _SIZE_T + typedef long size_t; + #endif + + The script `patch-apollo-includes' fixes these two problems, but does + _not_ pretend to be a full fledged `fixincludes' for this system. + + If you now follow the standard GCC installation instructions, building + GCC 2.0 (including G++ 2.0) should proceed without any problems. + + NB: Debugging is not yet supported for the Apollo. If someone wants + to do a _big_ favour to the Apollo users, he/she should consider + porting the Binary File Description library (BFD) to the Apollo. + This library can be found in the gdb-4.x distributions or in the + binutils-1.9x distributions. + + + + + #!/bin/sh + # patch-apollo-includes -- fix some (but not all!) Apollo brain damage. + + FILES_TO_PATCH='sys/types.h setjmp.h' + + mkdir sys + + for i in $FILES_TO_PATCH; + do + cp /bsd4.3/usr/include/$i ./$i + done + + patch -b -apollo <<'EOP' + *** /bsd4.3/usr/include/sys/types.h Fri Apr 8 20:29:06 1988 + --- sys/types.h Wed Feb 26 21:17:57 1992 + *************** + *** 38,44 **** + --- 38,47 ---- + typedef char * caddr_t; + typedef u_long ino_t; + typedef long swblk_t; + + #ifndef _SIZE_T + + #define _SIZE_T + typedef long size_t; + + #endif + typedef long time_t; + typedef long dev_t; + typedef long off_t; + *** /bsd4.3/usr/include/setjmp.h Fri Feb 3 21:40:21 1989 + --- setjmp.h Sun Feb 23 19:06:55 1992 + *************** + *** 24,30 **** + --- 24,39 ---- + #endif + + + + #ifdef __GNUC__ + #ifdef _PROTOTYPES + + extern int sigsetjmp (sigjmp_buf env, int savemask); + + extern void siglongjmp (sigjmp_buf env, int val); + + #else + + extern int sigsetjmp(); + + extern void siglongjmp(); + + #endif /* _PROTOTYPES */ + + #else /* not __GNUC__ */ + + #ifdef _PROTOTYPES + extern int sigsetjmp( + sigjmp_buf env, + int savemask + *************** + *** 37,43 **** + extern int sigsetjmp() #options(abnormal); + extern void siglongjmp() #options(noreturn); + #endif /* _PROTOTYPES */ + ! + #undef _PROTOTYPES + + #ifdef __cplusplus + --- 46,52 ---- + extern int sigsetjmp() #options(abnormal); + extern void siglongjmp() #options(noreturn); + #endif /* _PROTOTYPES */ + ! #endif /* not __GNUC__ */ + #undef _PROTOTYPES + + #ifdef __cplusplus + EOP + + exit 0 diff -rc2N gcc-2.1/README.DWARF gcc-2.2.1/README.DWARF *** gcc-2.1/README.DWARF Fri Mar 13 23:58:09 1992 --- gcc-2.2.1/README.DWARF Wed Jun 3 15:03:26 1992 *************** *** 1,39 **** ! Notes on the GNU Implementation of Dwarf Debugging Information -------------------------------------------------------------- ! Last Updated: Sun Feb 16 21:31:53 1991 by rfg@ncd.com ----------------------------------------------------- This file describes special and unique aspects of the GNU implementation ! of the Dwarf debugging information language in the GCC Version 2 compiler. ! For general information about the Dwarf debugging information language, ! you should obtain the latest Dwarf draft specification document developed ! by the UNIX(tm) International Programming Languages Special Interest Group. A copy of the this document (in PostScript form) may be obtained either ! from me or from the UI/PLSIG draft specification editor, ! Joel Silverstein . This file describes only known deviations ! from the current UI/PLSIG Dwarf specification document together with ! those things which are allowed by the current Dwarf specification but ! which are known to cause interoperability problems (e.g. with svr4 SDB). ! ! The generation of Dwarf debugging information in GCC2 has now been tested ! lightly (C language front end only) for m88k, i386, and i860 targets. ! Significant interoperability problems may still exist (e.g. with the ! USL svr4 version of the SDB debugger) due to a lack of accepted ! standards for numbering registers for various target architectures. ! (That is only one of the potential interoperability problems. See below ! for notes on other known interoperability problems applicable to the ! combination of GCC and svr4 SDB.) Note however that it is currently ! believed that the register numbering conventions used by GCC (in Dwarf ! output) are consistent with those used by the svr4 SDB debuggers provided ! with the System V Release 4 reference ports for the m88k, i386, and i860 ! processors. ! ! The Dwarf generation enhancement for GCC has been generously donated ! by Network Computing Devices to the Free Software Foundation. The ! additional code involved is covered under the GNU General Public License (aka `copyleft') just as the rest of GCC is. ! If you have questions or comments about the Dwarf generation feature of GCC, please send mail to me . I will be happy to investigate any bugs reported and I may even provide fixes (but of --- 1,56 ---- ! Notes on the GNU Implementation of DWARF Debugging Information -------------------------------------------------------------- ! Last Updated: Sun Jun 3 09:56:42 1992 by rfg@ncd.com ----------------------------------------------------- This file describes special and unique aspects of the GNU implementation ! of the DWARF debugging information language, as provided in the GCC Version ! 2 compiler. ! For general information about the DWARF debugging information language, ! you should obtain the latest DWARF draft specification document developed ! by the UNIX International Programming Languages Special Interest Group. A copy of the this document (in PostScript form) may be obtained either ! from me or from UNIX International. (See below.) The file ! you are looking at now only describes known deviations from the current ! UI/PLSIG DWARF specification document (1.0.1) together with those things ! which are allowed by the current DWARF specification but which are known ! to cause interoperability problems (e.g. with svr4 SDB). ! ! To obtain a copy of the latest DWARF specification document from UNIX ! International, use the following procedure: ! ! --------------------------------------------------------------------------- ! Send mail to archive@ui.org containing the following: ! ! path yourname@your.site ! send PUBLIC/dwarf.v1.mm ! ! for the troff source, or ! ! send PUBLIC/dwarf.v1.ps ! ! for the postscript. If you system supports uncompress and uudecode, ! you can request that the data be compressed by placing the command ! 'compress' in the message. ! ! If you have any questions about the archive service, please contact ! Shane P. McCarron, UI Project Manager, . ! --------------------------------------------------------------------------- ! ! The generation of DWARF debugging information in GCC v2.x has now been ! tested rather extensively (in conjunction with the C language front end ! only) for m88k, i386, i860, and Sparc targets. GCC's DWARF output (for C) ! appears to interoperate well with the standard svr4 SDB debugger on these ! kinds of target systems (but of course, there are no guarrantees). ! ! The DWARF generation enhancement for GCC was initially donated to the ! Free Software Foundation by Network Computing Devices. (Thanks NCD!) ! Additional development and maintenance of dwarfout.c has been largely ! supported (i.e. funded) by Intel Corporation. (Thanks Intel!) The code ! in dwarfout.c is (of course) covered under the GNU General Public License (aka `copyleft') just as the rest of GCC is. ! If you have questions or comments about the DWARF generation feature of GCC, please send mail to me . I will be happy to investigate any bugs reported and I may even provide fixes (but of *************** *** 40,55 **** course, I can make no promises). ! The Dwarf debugging information produced by GCC may deviate in a few minor ! (but perhaps significant) respects from the Dwarf debugging information ! currently produced by other C compilers. A serious attempt has been ! made however to conform to existing practice and generally accepted ! standards in the GNU implementation of Dwarf. ! If you are interested in obtaining more information about Dwarf or in ! participating in the continuing evolution of Dwarf within the UI/PLSIG group, please contact either myself or the UI/PLSIG chairman, Dan Oldman . The UI/PLSIG welcomes and encourages the participation of new members who might be interested in discussing debugging ! issues in general, and Dwarf in particular. There are no dues and you DO NOT have to be a UI member in order to join the UI/PLSIG. The UI/PLSIG operates an E-mail mailing list and holds regular meeting in various cities. --- 57,72 ---- course, I can make no promises). ! The DWARF debugging information produced by GCC may deviate in a few minor ! (but perhaps significant) respects from the DWARF debugging information ! currently produced by other C compilers. A serious attempt has been made ! however to conform to the published specifications, to existing practice, ! and to generally accepted norms in the GNU implementation of DWARF. ! If you are interested in obtaining more information about DWARF or in ! participating in the continuing evolution of DWARF within the UI/PLSIG group, please contact either myself or the UI/PLSIG chairman, Dan Oldman . The UI/PLSIG welcomes and encourages the participation of new members who might be interested in discussing debugging ! issues in general, and DWARF in particular. There are no dues and you DO NOT have to be a UI member in order to join the UI/PLSIG. The UI/PLSIG operates an E-mail mailing list and holds regular meeting in various cities. *************** *** 65,68 **** --- 82,102 ---- ------------------------------- + The AT_bit_offset value for bit-fields whose high-order bit lies smack up + against an "alignment unit" boundary will probably be incorrect. For + example, compiling: + + struct S { + int foo:9; + short bar:7; + int last:16; + }; + + ... for an x86 target yields a situation where `bar' lies smack up against + the high-order end of the hypothetical type `short' object which contains it. + In such cases, the AT_bit_offset should be zero, but it may instead be equal + to the size of the containing object (which, for this example, is 16 bits). + + -------------------------------- + At this time, GCC does not know how to handle the GNU C "nested functions" extension. (See the GCC manual for more info on this extension to ANSI C.) *************** *** 71,77 **** At this time, GCC does not represent inlined instances of inline functions ! as called for by the current Dwarf draft specification. Support for inlined instances of inline functions is still "under construction". -------------------------------- --- 105,118 ---- At this time, GCC does not represent inlined instances of inline functions ! as called for by the current DWARF draft specification. Support for inlined instances of inline functions is still "under construction". + Recently, a new approach to the representation of inlined functions (within + DWARF) has been proposed (by me) to the UI/PLSIG. This proposal was well + received, but has not yet been formally approved. It is hoped that this + proposal will be approved by the UI/PLSIG sometime in the future. A future + release of GCC may incorporate the new approach for representing inlined + functions (which I have already implemented). Contact me for further details. + -------------------------------- *************** *** 78,84 **** At this time, GCC does not generate the kind of really precise information about the exact declared types of entities with signed integral types which ! is required by the current Dwarf draft specification. ! Specifically, the current Dwarf draft specification seems to require that the type of an non-unsigned integral bit-field member of a struct or union type be represented as either a "signed" type or as a "plain" type, --- 119,125 ---- At this time, GCC does not generate the kind of really precise information about the exact declared types of entities with signed integral types which ! is required by the current DWARF draft specification. ! Specifically, the current DWARF draft specification seems to require that the type of an non-unsigned integral bit-field member of a struct or union type be represented as either a "signed" type or as a "plain" type, *************** *** 89,93 **** does not constrain the signedness of a plain bit-field, whereas it does constrain the signedness of an explicitly "signed" bit-field. For this ! reason, the current Dwarf specification calls for compilers to produce type information (for *all* integral typed entities... not just bit-fields) which explicitly indicates the signedness of the relevant type to be --- 130,134 ---- does not constrain the signedness of a plain bit-field, whereas it does constrain the signedness of an explicitly "signed" bit-field. For this ! reason, the current DWARF specification calls for compilers to produce type information (for *all* integral typed entities... not just bit-fields) which explicitly indicates the signedness of the relevant type to be *************** *** 94,98 **** "signed" or "plain" or "unsigned". ! Unfortunately, the GNU Dwarf implementation is currently incapable of making such distinctions. --- 135,139 ---- "signed" or "plain" or "unsigned". ! Unfortunately, the GNU DWARF implementation is currently incapable of making such distinctions. *************** *** 99,103 **** -------------------------------- ! Full Dwarf support for the GNU C++ language/front-end (aka g++) is not implemented at this time. --- 140,144 ---- -------------------------------- ! Full DWARF support for the GNU C++ language/front-end (aka g++) is not implemented at this time. *************** *** 108,114 **** ------------------------------- ! Although the GNU implementation of Dwarf conforms (for the most part) with ! the current UI/PLSIG Dwarf draft specification, there are a few known cases ! where GCC's Dwarf output causes confusion in System V Release 4 SDB debuggers anyway. There cases are described in this section. --- 149,155 ---- ------------------------------- ! Although the GNU implementation of DWARF conforms (for the most part) with ! the current UI/PLSIG DWARF draft specification, there are a few known cases ! where GCC's DWARF output causes confusion in System V Release 4 SDB debuggers anyway. There cases are described in this section. *************** *** 115,119 **** -------------------------------- ! The current Dwarf draft specification includes the fundamental type codes FT_ext_prec_float, FT_complex, FT_dbl_prec_complex, and FT_ext_prec_complex. Since GNU C is only a C compiler (and since C doesn't provide any "complex" --- 156,160 ---- -------------------------------- ! The current DWARF draft specification includes the fundamental type codes FT_ext_prec_float, FT_complex, FT_dbl_prec_complex, and FT_ext_prec_complex. Since GNU C is only a C compiler (and since C doesn't provide any "complex" *************** *** 141,148 **** ! General GNU Dwarf extensions ---------------------------- ! In the current Dwarf draft specification, no provision is made for providing accurate information about executable lines which came into the current compilation unit by way of an include file. --- 182,189 ---- ! General GNU DWARF extensions ---------------------------- ! In the current DWARF draft specification, no provision is made for providing accurate information about executable lines which came into the current compilation unit by way of an include file. *************** *** 150,157 **** Recently, a scheme for providing accurate information about code in include files was proposed (by me) to the UI/PLSIG. This scheme was rejected by the ! UI/PLSIG for inclusion into the Dwarf Version 1 specification, but GNU Dwarf implements this extension anyway. ! To understand this GNU Dwarf extension, imagine that the sequence of entries in the .lines section is broken up into several subsections. Each contiguous sequence of .line entries which relates to a sequence of lines (or statements) --- 191,198 ---- Recently, a scheme for providing accurate information about code in include files was proposed (by me) to the UI/PLSIG. This scheme was rejected by the ! UI/PLSIG for inclusion into the DWARF Version 1 specification, but GNU DWARF implements this extension anyway. ! To understand this GNU DWARF extension, imagine that the sequence of entries in the .lines section is broken up into several subsections. Each contiguous sequence of .line entries which relates to a sequence of lines (or statements) *************** *** 280,284 **** -------------------------------- ! In the current Dwarf draft specification, no provision is made for recording any information about macro definitions and un-definitions. --- 321,325 ---- -------------------------------- ! In the current DWARF draft specification, no provision is made for recording any information about macro definitions and un-definitions. *************** *** 285,290 **** Recently, a scheme for providing accurate information about macro definitions an un-definitions was proposed (by me) to the UI/PLSIG. This scheme was ! rejected by the UI/PLSIG for inclusion into the Dwarf Version 1 specification, ! but GNU Dwarf implements this extension anyway (when the -g3 option is used). GCC records information about macro definitions and undefinitions primarily --- 326,331 ---- Recently, a scheme for providing accurate information about macro definitions an un-definitions was proposed (by me) to the UI/PLSIG. This scheme was ! rejected by the UI/PLSIG for inclusion into the DWARF Version 1 specification, ! but GNU DWARF implements this extension anyway (when the -g3 option is used). GCC records information about macro definitions and undefinitions primarily *************** *** 342,346 **** -------------------------------- ! In the current Dwarf draft specification, no provision is made for providing a separate level of (limited) debugging information necessary to support tracebacks (only) through fully-debugged code (e.g. code in system libraries). --- 383,387 ---- -------------------------------- ! In the current DWARF draft specification, no provision is made for providing a separate level of (limited) debugging information necessary to support tracebacks (only) through fully-debugged code (e.g. code in system libraries). *************** *** 348,354 **** Recently, a proposal to define such a level was submitted (by me) to the UI/PLSIG. This proposal was rejected by the UI/PLSIG for inclusion into ! the Dwarf Version 1 specification because it was felt that the issues involved in supporting a "traceback only" subset of dwarf were not yet ! well understood. Nonetheless, the GNU implementation of Dwarf provides this extension anyway (when the -g1 option is used). --- 389,395 ---- Recently, a proposal to define such a level was submitted (by me) to the UI/PLSIG. This proposal was rejected by the UI/PLSIG for inclusion into ! the DWARF Version 1 specification because it was felt that the issues involved in supporting a "traceback only" subset of dwarf were not yet ! well understood. Nonetheless, the GNU implementation of DWARF provides this extension anyway (when the -g1 option is used). *************** *** 356,368 **** ! GNU Dwarf Representation of GNU C Extensions to ANSI C ------------------------------------------------------ The file dwarfout.c has been designed and implemented so as to provide ! some reasonable Dwarf representation for each and every declarative construct which is accepted by the GNU C compiler. Since the GNU C compiler accepts a superset of ANSI C, this means that there are some ! cases in which the Dwarf information produced by GCC must take some ! liberties in improvising Dwarf representations for declarations which are only valid in (extended) GNU C. --- 397,409 ---- ! GNU DWARF Representation of GNU C Extensions to ANSI C ------------------------------------------------------ The file dwarfout.c has been designed and implemented so as to provide ! some reasonable DWARF representation for each and every declarative construct which is accepted by the GNU C compiler. Since the GNU C compiler accepts a superset of ANSI C, this means that there are some ! cases in which the DWARF information produced by GCC must take some ! liberties in improvising DWARF representations for declarations which are only valid in (extended) GNU C. *************** *** 371,379 **** and (2) dynamic arrays, and (3) incomplete enum types. (See the GCC manual for more information on these GNU extensions to ANSI C.) When ! used, these GNU C extensions are represented (in the generated Dwarf output of GCC) in the most natural and intuitively obvious ways. ! In the case of inline functions, the Dwarf representation is exactly as ! called for (in the current UI/PLSIG Dwarf draft specification) for an identical function written in C++; i.e. we "reuse" the representation of inline functions defined for C++ to support this GNU C extension. --- 412,420 ---- and (2) dynamic arrays, and (3) incomplete enum types. (See the GCC manual for more information on these GNU extensions to ANSI C.) When ! used, these GNU C extensions are represented (in the generated DWARF output of GCC) in the most natural and intuitively obvious ways. ! In the case of inline functions, the DWARF representation is exactly as ! called for (in the current UI/PLSIG DWARF draft specification) for an identical function written in C++; i.e. we "reuse" the representation of inline functions defined for C++ to support this GNU C extension. *************** *** 382,386 **** mechanism available; i.e. an array type in which the upper bound of some dimension (usually the first and only dimension) is a variable ! rather than a constant. See the UI/PLSIG Dwarf draft specification for more details. --- 423,427 ---- mechanism available; i.e. an array type in which the upper bound of some dimension (usually the first and only dimension) is a variable ! rather than a constant. See the UI/PLSIG DWARF draft specification for more details. *************** *** 402,419 **** Likewise, the UI/PLSIG has defined what is believed to be a complete and sufficient set of codes and rules for adequately representing all of ! FORTRAN 77, and most of Fortran 90 in Dwarf. While some support for this has been implemented in dwarfout.c, further implementation and testing will have to await the arrival of the GNU Fortran front-end. ! Dwarf support for other languages (i.e. Pascal and Modula) currently has ! a number of known problems as far as the current UI/PLSIG Dwarf draft ! specification is concerned. Hopefully, A more complete form of Dwarf which can handle *all* of the symbolic debugging requirements for Pascal, Modula, and Ada will evolve in the future. Efforts are currently underway ! to develop Dwarf more fully for these and other languages under the auspices of the UI/PLSIG. Contact the Chairman, Dan Oldman for further information. ! As currently defined, Dwarf only describes a (binary) language which can be used to communicate symbolic debugging information from a compiler through an assembler and a linker, to a debugger. There is no clear --- 443,460 ---- Likewise, the UI/PLSIG has defined what is believed to be a complete and sufficient set of codes and rules for adequately representing all of ! FORTRAN 77, and most of Fortran 90 in DWARF. While some support for this has been implemented in dwarfout.c, further implementation and testing will have to await the arrival of the GNU Fortran front-end. ! DWARF support for other languages (i.e. Pascal and Modula) currently has ! a number of known problems as far as the current UI/PLSIG DWARF draft ! specification is concerned. Hopefully, A more complete form of DWARF which can handle *all* of the symbolic debugging requirements for Pascal, Modula, and Ada will evolve in the future. Efforts are currently underway ! to develop DWARF more fully for these and other languages under the auspices of the UI/PLSIG. Contact the Chairman, Dan Oldman for further information. ! As currently defined, DWARF only describes a (binary) language which can be used to communicate symbolic debugging information from a compiler through an assembler and a linker, to a debugger. There is no clear *************** *** 421,433 **** assembler and/or the linker. Fortunately, the role of the assembler is easily inferred (by anyone knowledgeable about assemblers) just by ! looking at examples of assembly-level Dwarf code. Sadly though, the allowable (or required) processing steps performed by a linker are harder to infer and (perhaps) even harder to agree upon. There are several forms of very useful `post-processing' steps which intelligent ! linkers *could* (in theory) perform on object files containing Dwarf, but any and all such link-time transformations are currently both disallowed and unspecified. ! In particular, possible link-time transformations of Dwarf code which could provide significant benefits include (but are not limited to): --- 462,474 ---- assembler and/or the linker. Fortunately, the role of the assembler is easily inferred (by anyone knowledgeable about assemblers) just by ! looking at examples of assembly-level DWARF code. Sadly though, the allowable (or required) processing steps performed by a linker are harder to infer and (perhaps) even harder to agree upon. There are several forms of very useful `post-processing' steps which intelligent ! linkers *could* (in theory) perform on object files containing DWARF, but any and all such link-time transformations are currently both disallowed and unspecified. ! In particular, possible link-time transformations of DWARF code which could provide significant benefits include (but are not limited to): *************** *** 435,439 **** (object) files. ! Cross-compilation type checking based upon Dwarf type information for objects and functions. --- 476,480 ---- (object) files. ! Cross-compilation type checking based upon DWARF type information for objects and functions. diff -rc2N gcc-2.1/README.MIPS gcc-2.2.1/README.MIPS *** gcc-2.1/README.MIPS Mon Mar 23 22:04:54 1992 --- gcc-2.2.1/README.MIPS Mon Apr 27 11:26:18 1992 *************** *** 1,69 **** ! The following two patches were suggested for mips-tfile.c. ! They arrived too late to be considered for installation. ! But it's possible that they actually are needed. ! If you have trouble with mips-tfile, please try these patches. ! ! Mon Mar 23 15:10:10 1992 Brendan Kehoe (brendan@cs.widener.edu) ! ! * mips-tfile.c (parse_begin, parse_bend): Look in the external ! symbols table for labels; also refer to each as an external ! symbol, not as a normal symbol. ! ! --- mips-tfile.c.~4~ Mon Mar 23 14:46:08 1992 ! +++ mips-tfile.c Mon Mar 23 15:08:58 1992 ! @@ -2813,7 +2813,7 @@ ! ! hash_ptr = hash_string (start, ! end_p1 - start, ! - &orig_str_hash[0], ! + &ext_str_hash[0], ! (symint_t *)0); ! ! if (hash_ptr == (shash_t *)0) ! @@ -2830,7 +2830,7 @@ ! ! (void) add_local_symbol ((const char *)0, (const char *)0, ! st_Block, sc_Text, ! - (symint_t)hash_ptr->sym_ptr->value - cur_oproc_begin->value, ! + (symint_t)hash_ptr->esym_ptr->asym.value - cur_oproc_begin->value, ! (symint_t)0); ! } ! ! @@ -2863,7 +2863,7 @@ ! ! hash_ptr = hash_string (start, ! end_p1 - start, ! - &orig_str_hash[0], ! + &ext_str_hash[0], ! (symint_t *)0); ! ! if (hash_ptr == (shash_t *)0) ! @@ -2880,7 +2880,7 @@ ! ! (void) add_local_symbol ((const char *)0, (const char *)0, ! st_End, sc_Text, ! - (symint_t)hash_ptr->sym_ptr->value - cur_oproc_begin->value, ! + (symint_t)hash_ptr->esym_ptr->asym.value - cur_oproc_begin->value, ! (symint_t)0); ! } ! ! ! Mon Mar 23 15:10:10 1992 Brendan Kehoe (brendan@cs.widener.edu) ! ! * mips-tfile.c (copy_object): It doesn't make sense to enter ! static variables into the original symbol table, since the ! same name may show up a number of times. ! ! -- ! --- mips-tfile.c.~4~ Mon Mar 23 15:08:58 1992 ! +++ mips-tfile.c Mon Mar 23 16:23:44 1992 ! @@ -4581,7 +4581,6 @@ ! break; ! ! case st_Global: ! - case st_Static: ! case st_Label: ! case st_Proc: ! case st_StaticProc: ! --- 1,13 ---- ! If you use the 1.31 version of the MIPS assembler (such as was shipped ! with Ultrix 3.1), you will need to use the -fno-delayed-branch switch ! when optimizing floating point code. Otherwise, the assembler will ! complain when the GCC compiler fills a branch delay slot with a ! floating point instruction, such as add.d. ! ! The GCC compiler on the MIPS will put small strings into the short ! data area, rather than the read-only data section. This is so that ! references to the strings only take one instruction, instead of the ! normal two instructions. ! Users have reported some problems with version 2.0 of the MIPS ! compiler tools (Ultrix 4.1). Version 2.10 seems to work (Ultrix 4.2). diff -rc2N gcc-2.1/README.RS6000 gcc-2.2.1/README.RS6000 *** gcc-2.1/README.RS6000 Wed Mar 11 23:44:56 1992 --- gcc-2.2.1/README.RS6000 Sat Apr 25 02:10:23 1992 *************** *** 1,22 **** ! The current version of the assembler (/bin/as) for the RS/6000 has ! certain problems that prevent prevent the "-g" option in GCC from ! working. ! ! IBM has produced a fixed version of the assembler. The replacement ! assembler is not a standard component of either AIX 3.1.5 or AIX 3.2, ! but is expected to become standard in a future distribution. ! ! If you have an RS/6000, you can get the fixed assembler either on ! diskette or via VNET ftp. VNET distribution may be desirable if you ! have an IBM rep nearby with a networked VM machine. ! In either case, execute lslpp -h bos.obj to determine your release level. (Look on the ! ACTIVE line for something like 03.01.0005.0012.) If you know your ! customer number, please have it available; if you do not, you will ! still be able to obtain the fixed assembler, but you will need to be ! insistent. Then call IBM Support at 800-237-5511. Ask for emergency ! shipment of the RS/6000 AIX fix for APAR IX22829. They may ask you to ! verify that it's a fix for ".extern foo conflicts with defining foo"; ! say yes. You will receive a tar or tar.Z file containing an assembler ! plus installation instructions. --- 1,35 ---- ! Debugging code compiled with GCC on the RS/6000 requires that you ! upgrade the AIX assembler /bin/as with a replacement that is available ! from IBM. ! Any customer can order and get the replacement assembler, and install ! it on one or more machines. It is distributed both on diskette and ! via VNET, for downloading via ftp. VNET distribution may be desirable ! if you have a friendly IBM rep nearby with a networked VM machine. ! ! In either case, to order, execute lslpp -h bos.obj to determine your release level. (Look on the ! ACTIVE line for something like 03.01.0005.0012.) Then call IBM Support ! at 800-237-5511. Ask for emergency shipment of the rs6000 AIX fix for ! APAR IX22829. They may ask you to verify that it's a fix for ".extern ! foo conflicts with defining foo"; say yes. They may also ask you for ! your customer number. If you do not know it, you will still be able ! to get the fix, but you will have to be persistent. ! ! You will receive a tar or tar.Z file containing an assembler plus ! installation instructions. ! ! If you tell them you're running AIX version 3.2, you may be told that ! no fix is available yet. In fact the 3.15 fix works fine on version ! 3.2. Talk them into shipping it to you anyway. ! ! A second upgrade is in the works that will replace IX22829 and fix two ! more problems with debug information. There's no scheduled ! availability yet, but it's probably summer '92. Ask for the fix for ! APAR IX26107, "Don't allow .csect name[BS] or [UC]" ! ! IBM has corresponding support organizations outside of North America. ! Call your IBM branch office and ask them to put you in touch with the ! department that handles emergency fixes for AIX on the RS/6000. If ! that doesn't work, ask for the department that handles software defect ! support for AIX on the RS/6000. Then ask for the emergency APAR fix. diff -rc2N gcc-2.1/README.TRAD gcc-2.2.1/README.TRAD *** gcc-2.1/README.TRAD Fri Jan 17 16:51:19 1992 --- gcc-2.2.1/README.TRAD Thu May 28 16:30:28 1992 *************** *** 1,4 **** ! This is a partial list of how `gcc -traditional' disagrees with ! traditional C compilers. --------------------------------------------------------------------------- --- 1,5 ---- ! This is a partial list of how `gcc -traditional' disagrees with ! traditional C compilers (perhaps only some of them). Most of these ! differences are not bugs. --------------------------------------------------------------------------- diff -rc2N gcc-2.1/README.X11 gcc-2.2.1/README.X11 *** gcc-2.1/README.X11 Thu Mar 5 23:25:51 1992 --- gcc-2.2.1/README.X11 Fri May 29 15:15:32 1992 *************** *** 1,6 **** ! How to compile X11R5 (patch level 9) with GCC version 2: The patches include support for building the shared libraries with GCC 2 on ! the Sparc and 68k machines. Sun forgot to include a static version of libdl.a with some versions --- 1,17 ---- ! How to compile X11R5 (patch level 11) with GCC version 2: The patches include support for building the shared libraries with GCC 2 on ! the Sparc and 68k machines. NOTE: Such shared libraries DO NOT WORK ! with executables previously linked using Sun CC! This is because ! neither those executables nor the gcc-compiled shared libraries contain ! libgcc.a. The shared libraries do work with executables linked using ! GCC (running the Sun linker, of course) because GCC tells the linker to ! link in libgcc.a. Because of these limitations the default behavior is ! to NOT build the shared libraries with gcc. If you want the gcc-compiled ! shared libraries turn on "Gcc2BuildLibs" in site.def ! ! If you want to build a shared library that works with executables ! linked with Sun CC, you will have to arrange to include libgcc.a in ! the shared libraries. The instructions below do not handle this. Sun forgot to include a static version of libdl.a with some versions *************** *** 13,20 **** most likely be turned on by -O2 optimization. ! mit/config/sunLib.rules -- If HasGcc2 is defined, then use -fpic to ! generate PIC code. Make sure that gcc does not use gas (the GNU assembler) ! when compiling PIC code; gas does not assemble it correctly. If you ! have gas installed where gcc uses it by default, you might have to add -B/bin/ to the PositionIndependentCFlags. --- 24,31 ---- most likely be turned on by -O2 optimization. ! mit/config/sunLib.rules -- If HasGcc2 and Gcc2BuildLibs are defined, then ! use gcc -fpic to generate PIC code. Make sure that gcc does not use gas (the ! GNU assembler) when compiling PIC code; gas does not assemble it correctly. ! If you have gas installed where gcc uses it by default, you might have to add -B/bin/ to the PositionIndependentCFlags. *************** *** 48,66 **** #if HasFortran *** mit/config/sunLib.rules.ORIG Tue Dec 31 11:11:24 1991 ! --- mit/config/sunLib.rules Thu Jan 2 15:39:29 1992 *************** ! *** 23,29 **** ! --- 23,33 ---- #define SharedLibraryLoadFlags -assert pure-text #endif #ifndef PositionIndependentCFlags ! + #if defined(HasGcc2) + #define PositionIndependentCFlags -fpic + #else #define PositionIndependentCFlags -pic - + #endif #endif /* *** mit/config/site.def.ORIG Tue Dec 31 11:13:49 1991 --- mit/config/site.def Tue Dec 31 12:02:59 1991 --- 59,78 ---- #if HasFortran *** mit/config/sunLib.rules.ORIG Tue Dec 31 11:11:24 1991 ! --- mit/config/sunLib.rules Tue May 5 12:26:12 1992 *************** ! *** 23,30 **** ! --- 23,34 ---- #define SharedLibraryLoadFlags -assert pure-text #endif #ifndef PositionIndependentCFlags ! + #if defined(HasGcc2) && defined (Gcc2BuildLibs) + #define PositionIndependentCFlags -fpic + #else #define PositionIndependentCFlags -pic #endif + + #endif /* + * InstallSharedLibrary - generate rules to install the shared library. *** mit/config/site.def.ORIG Tue Dec 31 11:13:49 1991 --- mit/config/site.def Tue Dec 31 12:02:59 1991 *************** *** 74,78 **** #endif /* BeforeVendorCF */ ! --- 25,32 ---- #ifdef BeforeVendorCF --- 86,90 ---- #endif /* BeforeVendorCF */ ! --- 25,33 ---- #ifdef BeforeVendorCF *************** *** 80,83 **** --- 92,96 ---- ! #define HasGcc YES ! #define HasGcc2 YES + ! /* #define Gcc2BuildLibs YES */ #endif /* BeforeVendorCF */ *************** *** 84,98 **** *** mit/config/sun.cf.ORIG Tue Dec 31 11:13:57 1991 ! --- mit/config/sun.cf Wed Jan 15 12:13:53 1992 *************** *** 34,42 **** ! --- 34,47 ---- #if HasGcc - + #define OptimizedCDebugFlags -O + #if defined(HasGcc2) ! + #define OptimizedCDebugFlags -O2 ! + #else #define SharedLibraryCcCmd cc #define ExtraLoadFlags -B/usr/bin/ --- 97,112 ---- *** mit/config/sun.cf.ORIG Tue Dec 31 11:13:57 1991 ! --- mit/config/sun.cf Tue May 5 12:29:50 1992 *************** *** 34,42 **** ! --- 41,61 ---- #if HasGcc + #if defined(HasGcc2) ! + #define OptimizedCDebugFlags -O2 ! + /* Leave Alone XXX */ ! + #else ! + #define OptimizedCDebugFlags -O #define SharedLibraryCcCmd cc #define ExtraLoadFlags -B/usr/bin/ *************** *** 99,106 **** #define AllocateLocalDefines /**/ + #endif .c.o: $(CC) -c $(CFLAGS) $*.c - *** mit/rgb/Imakefile.ORIG Wed Jan 15 16:43:18 1992 --- mit/rgb/Imakefile Thu Jan 2 13:34:09 1992 --- 113,125 ---- #define AllocateLocalDefines /**/ + #endif + + + + #if !defined(Gcc2BuildLibs) + + #define SharedLibraryCcCmd cc + + #define ExtraLoadFlags -B/usr/bin/ + + #define AllocateLocalDefines /**/ + + #endif .c.o: $(CC) -c $(CFLAGS) $*.c *** mit/rgb/Imakefile.ORIG Wed Jan 15 16:43:18 1992 --- mit/rgb/Imakefile Thu Jan 2 13:34:09 1992 *************** *** 141,144 **** $(RM) $@ cc -c $(DBM_DEFINES) $(CDEBUGFLAGS) $(ALLDEFINES) $*.c - - --- 160,161 ---- diff -rc2N gcc-2.1/SERVICE gcc-2.2.1/SERVICE *** gcc-2.1/SERVICE Tue Mar 24 21:49:29 1992 --- gcc-2.2.1/SERVICE Tue Jun 9 22:40:29 1992 *************** *** 580,614 **** Updated: 7/20/91  - Isaac J. Salzman - Sun Microsystems Inc. - 2550 Garcia Ave., MS: MTV23-41 - Mt. View, CA 94043-1100 - 1+ 415-336-4338 (work) - - X11 - Installation, customization, support, some training, etc. All - available window managers, XView, Andrew, InterViews, (but NO - Motif!). - Emacs/Epoch - Installation, customization, support, etc. - GCC/G++ - Installation, support, etc.. - MH - Installation, customization, support, sendmail config, etc. - OTHER - Consulting on - most GNUware, SunOS/BSD UNIX IPC programming, - (most anything hat's BSD UNIX related), Sparcstation Audio, - MIDI. - - Rate: Negotiable - around $65/hr. I'll take quick e-mail/phone questions - for free (e-mail preferred). - - Experiance: 8.5+ years BSD UNIX systems programming (Sun's, VAXen) including - support of GNU Emacs & MH. About 6+ years of X11 experience. - Extensive knowledge of C, C++, perl, shell programming, XView, and - SunOS. Resume available upon request. - - Dergree: B.S. Computer Science, California State University, Northridge. - - Availibilty: My time is limited so it has to be a very short - or *very* - interesting project. :-) - - Updated: 18 August 91 -  John Sechrest Jasmic Systems Internet: --- 580,583 ---- diff -rc2N gcc-2.1/alloca.c gcc-2.2.1/alloca.c *** gcc-2.1/alloca.c Wed Nov 27 13:31:04 1991 --- gcc-2.2.1/alloca.c Tue Jun 9 22:40:30 1992 *************** *** 43,48 **** -- must know STACK_DIRECTION at compile-time #endif /* STACK_DIRECTION undefined */ ! #endif static ! #endif emacs #ifndef alloca /* If compiling with GCC, this file's not needed. */ --- 43,48 ---- -- must know STACK_DIRECTION at compile-time #endif /* STACK_DIRECTION undefined */ ! #endif /* static */ ! #endif /* emacs */ #ifndef alloca /* If compiling with GCC, this file's not needed. */ diff -rc2N gcc-2.1/assert.h gcc-2.2.1/assert.h *** gcc-2.1/assert.h Thu Jan 30 16:16:11 1992 --- gcc-2.2.1/assert.h Mon Jun 8 17:12:58 1992 *************** *** 14,18 **** #define __assert(expression, file, lineno) \ ! (printf ("%s:%d: failed assertion\n", file, lineno), \ abort (), 0) --- 14,18 ---- #define __assert(expression, file, lineno) \ ! (printf ("%s:%u: failed assertion\n", file, lineno), \ abort (), 0) *************** *** 19,26 **** #else ! #ifdef __STDC__ /* Defined in libgcc.a */ extern void __eprintf (const char *, const char *, int, const char *); #define assert(expression) \ --- 19,32 ---- #else ! #if defined(__STDC__) || defined (__cplusplus) /* Defined in libgcc.a */ + #ifdef __cplusplus + extern "C" { extern void __eprintf (const char *, const char *, int, const char *); + } + #else + extern void __eprintf (const char *, const char *, int, const char *); + #endif #define assert(expression) \ *************** *** 28,35 **** #define __assert(expression, file, line) \ ! (__eprintf ("%s:%d: failed assertion `%s'\n", \ file, line, expression), 0) ! #else /* no __STDC__; i.e. -traditional. */ extern void __eprintf (); /* Defined in libgcc.a */ --- 34,41 ---- #define __assert(expression, file, line) \ ! (__eprintf ("%s:%u: failed assertion `%s'\n", \ file, line, expression), 0) ! #else /* no __STDC__ and not C++; i.e. -traditional. */ extern void __eprintf (); /* Defined in libgcc.a */ *************** *** 39,46 **** #define __assert(expression, file, lineno) \ ! (__eprintf ("%s:%d: failed assertion `%s'\n", \ file, lineno, "expression"), 0) ! #endif /* no __STDC__; i.e. -traditional. */ #endif /* no __GNU__; i.e., /bin/cc. */ #endif --- 45,52 ---- #define __assert(expression, file, lineno) \ ! (__eprintf ("%s:%u: failed assertion `%s'\n", \ file, lineno, "expression"), 0) ! #endif /* no __STDC__ and not C++; i.e. -traditional. */ #endif /* no __GNU__; i.e., /bin/cc. */ #endif diff -rc2N gcc-2.1/c++ gcc-2.2.1/c++ *** gcc-2.1/c++ Wed Mar 11 18:17:19 1992 --- gcc-2.2.1/c++ Tue May 26 14:56:14 1992 *************** *** 28,32 **** quote=yes ;; ! -[cSE]) # Don't specify libraries if we won't link, # since that would cause a warning. --- 28,32 ---- quote=yes ;; ! -[cSEM] | -MM) # Don't specify libraries if we won't link, # since that would cause a warning. diff -rc2N gcc-2.1/c-aux-info.c gcc-2.2.1/c-aux-info.c *** gcc-2.1/c-aux-info.c Thu Mar 19 15:24:13 1992 --- gcc-2.2.1/c-aux-info.c Sat May 9 20:34:30 1992 *************** *** 24,29 **** #include - #include - #include #include "config.h" #include "flags.h" --- 24,27 ---- *************** *** 31,38 **** #include "c-tree.h" - #ifndef errno - extern int errno; - #endif - extern char* xmalloc (); --- 29,32 ---- *************** *** 55,74 **** static char * gen_decl (); void gen_aux_info_record (); - - #if 0 - /* Virtually every UN*X system now in common use (except for pre-4.3-tahoe - BSD systems) now provides getcwd as called for by POSIX. Allow for - the few exceptions to the general rule here. */ - - #if !(defined (USG) || defined (VMS)) - extern char *getwd (); - #define getcwd(buf,len) getwd(buf) - #define GUESSPATHLEN (MAXPATHLEN + 1) - #else /* (defined (USG) || defined (VMS)) */ - extern char *getcwd (); - /* We actually use this as a starting point, not a limit. */ - #define GUESSPATHLEN 100 - #endif /* (defined (USG) || defined (VMS)) */ - #endif /* 0 */ /* Take two strings and mash them together into a newly allocated area. */ --- 49,52 ---- *************** *** 623,646 **** if (! compiled_from_record++) { - #if 0 - int size; - char *wd; - char *value; - - /* Read the working directory, avoiding arbitrary limit. */ - size = GUESSPATHLEN; - while (1) - { - wd = (char *) xmalloc (size); - value = getcwd (wd, size); - if (value != 0 || errno != ERANGE) - break; - free (wd); - size *= 2; - } - - if (value != 0) - fprintf (aux_info_file, "/* compiled from: %s */\n", wd); - #endif /* The first line tells which directory file names are relative to. Currently, -fgen-aux-info works only for files in the working --- 601,604 ---- diff -rc2N gcc-2.1/c-common.c gcc-2.2.1/c-common.c *** gcc-2.1/c-common.c Tue Feb 4 14:51:11 1992 --- gcc-2.2.1/c-common.c Tue May 26 15:22:26 1992 *************** *** 28,31 **** --- 28,78 ---- #define NULL 0 + /* Make bindings for __FUNCTION__ and __PRETTY_FUNCTION__. */ + + void + declare_function_name () + { + tree decl, init; + char *name, *printable_name; + + if (current_function_decl == NULL) + { + name = ""; + printable_name = "top level"; + } + else + { + char *kind = "function"; + if (TREE_CODE (TREE_TYPE (current_function_decl)) == METHOD_TYPE) + kind = "method"; + name = IDENTIFIER_POINTER (DECL_NAME (current_function_decl)); + printable_name = (*decl_printable_name) (current_function_decl, &kind); + } + + push_obstacks_nochange (); + decl = build_decl (VAR_DECL, get_identifier ("__FUNCTION__"), + char_array_type_node); + TREE_STATIC (decl) = 1; + TREE_READONLY (decl) = 1; + TREE_USED (decl) = 1; + DECL_IGNORED_P (decl) = 1; + init = build_string (strlen (name) + 1, name); + TREE_TYPE (init) = char_array_type_node; + DECL_INITIAL (decl) = init; + finish_decl (pushdecl (decl), init, NULL_TREE); + + push_obstacks_nochange (); + decl = build_decl (VAR_DECL, get_identifier ("__PRETTY_FUNCTION__"), + char_array_type_node); + TREE_STATIC (decl) = 1; + TREE_READONLY (decl) = 1; + TREE_USED (decl) = 1; + DECL_IGNORED_P (decl) = 1; + init = build_string (strlen (printable_name) + 1, printable_name); + TREE_TYPE (init) = char_array_type_node; + DECL_INITIAL (decl) = init; + finish_decl (pushdecl (decl), init, NULL_TREE); + } + /* Given a chain of STRING_CST nodes, concatenate them into one STRING_CST *************** *** 148,154 **** tree a; for (a = attributes; a; a = TREE_CHAIN (a)) ! if (TREE_VALUE (a) != 0 && TREE_CODE (TREE_VALUE (a)) == TREE_LIST ! && TREE_PURPOSE (TREE_VALUE (a)) == get_identifier ("aligned")) { int align = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (a))) --- 195,233 ---- tree a; for (a = attributes; a; a = TREE_CHAIN (a)) ! if (TREE_VALUE (a) == get_identifier ("packed")) ! { ! if (TREE_CODE (decl) == FIELD_DECL) ! DECL_PACKED (decl) = 1; ! } ! else if (TREE_VALUE (a) != 0 && TREE_CODE (TREE_VALUE (a)) == TREE_LIST ! && TREE_PURPOSE (TREE_VALUE (a)) == get_identifier ("mode")) ! { ! int i; ! char *specified_name ! = IDENTIFIER_POINTER (TREE_VALUE (TREE_VALUE (a))); ! ! /* Give this decl a type with the specified mode. */ ! for (i = 0; i < NUM_MACHINE_MODES; i++) ! if (!strcmp (specified_name, GET_MODE_NAME (i))) ! { ! tree type ! = type_for_mode (i, TREE_UNSIGNED (TREE_TYPE (decl))); ! if (type != 0) ! { ! TREE_TYPE (decl) = type; ! DECL_SIZE (decl) = 0; ! layout_decl (decl); ! } ! else ! error ("no data type for mode `%s'", specified_name); ! break; ! } ! if (i == NUM_MACHINE_MODES) ! error ("unknown machine mode `%s'", specified_name); ! } ! else if (TREE_VALUE (a) != 0 ! && TREE_CODE (TREE_VALUE (a)) == TREE_LIST ! && TREE_PURPOSE (TREE_VALUE (a)) == get_identifier ("aligned")) { int align = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (a))) *************** *** 156,172 **** if (exact_log2 (align) == -1) ! warning_with_decl (decl, ! "requested alignment of `%s' is not a power of 2"); else if (TREE_CODE (decl) != VAR_DECL && TREE_CODE (decl) != FIELD_DECL) ! warning_with_decl (decl, ! "alignment specified for `%s' which is not a variable"); ! ! /* ??? The maximum alignment gcc can currently handle is 16 bytes! ! We should change the representation to be the log of the ! actual alignment since we only handle powers of 2 anyway. */ ! else if (align > 255) ! warning_with_decl (decl, ! "requested alignment of `%s' exceeds compiler limits"); else DECL_ALIGN (decl) = align; --- 235,244 ---- if (exact_log2 (align) == -1) ! error_with_decl (decl, ! "requested alignment of `%s' is not a power of 2"); else if (TREE_CODE (decl) != VAR_DECL && TREE_CODE (decl) != FIELD_DECL) ! error_with_decl (decl, ! "alignment specified for `%s'"); else DECL_ALIGN (decl) = align; *************** *** 174,185 **** else if (TREE_VALUE (a) != 0 && TREE_CODE (TREE_VALUE (a)) == TREE_LIST ! && TREE_PURPOSE (TREE_VALUE (a)) == get_identifier ("packed")) ! { ! if (TREE_CODE (decl) == FIELD_DECL) ! DECL_PACKED (decl) = 1; ! } ! else if (TREE_VALUE (a) != 0 ! && TREE_CODE (TREE_VALUE (a)) == TREE_LIST ! && TREE_PURPOSE (TREE_VALUE (a)) == get_identifier ("format")) { tree list = TREE_VALUE (TREE_VALUE (a)); --- 246,250 ---- else if (TREE_VALUE (a) != 0 && TREE_CODE (TREE_VALUE (a)) == TREE_LIST ! && TREE_PURPOSE (TREE_VALUE (a)) == get_identifier ("format")) { tree list = TREE_VALUE (TREE_VALUE (a)); *************** *** 191,196 **** if (TREE_CODE (decl) != FUNCTION_DECL) { ! warning_with_decl (decl, ! "argument format specified for non-function `%s'"); return; } --- 256,261 ---- if (TREE_CODE (decl) != FUNCTION_DECL) { ! error_with_decl (decl, ! "argument format specified for non-function `%s'"); return; } *************** *** 202,206 **** else { ! warning_with_decl (decl,"unrecognized format specifier for `%s'"); return; } --- 267,271 ---- else { ! error_with_decl (decl, "unrecognized format specifier for `%s'"); return; } *************** *** 208,212 **** if (first_arg_num != 0 && first_arg_num <= format_num) { ! warning_with_decl (decl, "format string arg follows the args to be formatted, for `%s'"); return; --- 273,277 ---- if (first_arg_num != 0 && first_arg_num <= format_num) { ! error_with_decl (decl, "format string arg follows the args to be formatted, for `%s'"); return; *************** *** 372,377 **** --- 437,444 ---- opname = ">>"; break; case TRUNC_MOD_EXPR: + case FLOOR_MOD_EXPR: opname = "%"; break; case TRUNC_DIV_EXPR: + case FLOOR_DIV_EXPR: opname = "/"; break; case BIT_AND_EXPR: *************** *** 385,388 **** --- 452,458 ---- case BIT_XOR_EXPR: opname = "^"; break; + case LROTATE_EXPR: + case RROTATE_EXPR: + opname = "rotate"; break; } error ("invalid operands to binary %s", opname); *************** *** 601,605 **** } ! if (max_lt && !unsignedp0) { /* This is the case of (char)x >?< 0x80, which people used to use --- 671,675 ---- } ! if (!max_gt && !unsignedp0) { /* This is the case of (char)x >?< 0x80, which people used to use *************** *** 611,617 **** } ! if (min_gt && unsignedp0) { ! /* This is the case of (unsigned char)x >?< -1. */ if (val == integer_zero_node) warning ("comparison is always 0 due to limited range of data type"); --- 681,687 ---- } ! if (!min_lt && unsignedp0) { ! /* This is the case of (unsigned char)x >?< -1 or < 0. */ if (val == integer_zero_node) warning ("comparison is always 0 due to limited range of data type"); diff -rc2N gcc-2.1/c-convert.c gcc-2.2.1/c-convert.c *** gcc-2.1/c-convert.c Tue Jan 28 22:42:48 1992 --- gcc-2.2.1/c-convert.c Tue Apr 21 14:00:03 1992 *************** *** 269,273 **** case NEGATE_EXPR: case BIT_NOT_EXPR: - case ABS_EXPR: { register tree typex = type; --- 269,272 ---- diff -rc2N gcc-2.1/c-decl.c gcc-2.2.1/c-decl.c *** gcc-2.1/c-decl.c Sun Mar 22 21:07:53 1992 --- gcc-2.2.1/c-decl.c Thu Jun 4 17:30:48 1992 *************** *** 175,181 **** tree string_ftype_ptr_ptr, int_ftype_string_string; - /* Function type `size_t (const char *)' */ - tree sizet_ftype_string; - /* Function type `int (const void *, const void *, size_t)' */ tree int_ftype_cptr_cptr_sizet; --- 175,178 ---- *************** *** 204,207 **** --- 201,208 ---- static tree enum_next_value; + /* Nonzero means that there was overflow computing enum_next_value. */ + + static int enum_overflow; + /* Parsing a function declarator leaves a list of parameter names or a chain or parameter decls here. */ *************** *** 400,407 **** int flag_no_asm; ! /* Nonzero means don't recognize the non-ANSI builtin functions. */ int flag_no_builtin; /* Nonzero means do some things the same way PCC does. */ --- 401,413 ---- int flag_no_asm; ! /* Nonzero means don't recognize any builtin functions. */ int flag_no_builtin; + /* Nonzero means don't recognize the non-ANSI builtin functions. + -ansi sets this. */ + + int flag_no_nonansi_builtin; + /* Nonzero means do some things the same way PCC does. */ *************** *** 548,552 **** flag_no_ident = 0; else if (!strcmp (p, "-ansi")) ! flag_no_asm = 1, flag_no_builtin = 1, dollars_in_ident = 0; else if (!strcmp (p, "-Wimplicit")) warn_implicit = 1; --- 554,558 ---- flag_no_ident = 0; else if (!strcmp (p, "-ansi")) ! flag_no_asm = 1, flag_no_nonansi_builtin = 1, dollars_in_ident = 0; else if (!strcmp (p, "-Wimplicit")) warn_implicit = 1; *************** *** 575,579 **** else if (!strcmp (p, "-Wredundant-decls")) warn_redundant_decls = 1; ! else if (!strcmp (p, "-Wnoredundant-decls")) warn_redundant_decls = 0; else if (!strcmp (p, "-Wnested-externs")) --- 581,585 ---- else if (!strcmp (p, "-Wredundant-decls")) warn_redundant_decls = 1; ! else if (!strcmp (p, "-Wno-redundant-decls")) warn_redundant_decls = 0; else if (!strcmp (p, "-Wnested-externs")) *************** *** 613,616 **** --- 619,626 ---- else if (!strcmp (p, "-Wno-trigraphs")) ; /* cpp handles this one. */ + else if (!strcmp (p, "-Wimport")) + ; /* cpp handles this one. */ + else if (!strcmp (p, "-Wno-import")) + ; /* cpp handles this one. */ else if (!strcmp (p, "-Wall")) { *************** *** 1316,1323 **** } } ! /* Warn if function is now inline ! but was previously declared not inline and has been called. */ else { if (TREE_CODE (olddecl) == FUNCTION_DECL && ! TREE_INLINE (olddecl) && TREE_INLINE (newdecl) --- 1326,1334 ---- } } ! /* Warn about mismatches in various flags. */ else { + /* Warn if function is now inline + but was previously declared not inline and has been called. */ if (TREE_CODE (olddecl) == FUNCTION_DECL && ! TREE_INLINE (olddecl) && TREE_INLINE (newdecl) *************** *** 1326,1330 **** "`%s' declared inline after being called"); if (TREE_CODE (olddecl) == FUNCTION_DECL ! && TREE_INLINE (olddecl) != TREE_INLINE (newdecl)) warning_with_decl (newdecl, "`%s' declarations disagree about `inline'"); --- 1337,1342 ---- "`%s' declared inline after being called"); if (TREE_CODE (olddecl) == FUNCTION_DECL ! && TREE_INLINE (olddecl) != TREE_INLINE (newdecl) ! && ! (TREE_EXTERNAL (olddecl) && TREE_EXTERNAL (newdecl))) warning_with_decl (newdecl, "`%s' declarations disagree about `inline'"); *************** *** 1336,1341 **** warning_with_decl (newdecl, "static declaration for `%s' follows non-static"); ! /* These bits are logically part of the type. */ ! if (pedantic && (TREE_READONLY (newdecl) != TREE_READONLY (olddecl) || TREE_THIS_VOLATILE (newdecl) != TREE_THIS_VOLATILE (olddecl))) --- 1348,1355 ---- warning_with_decl (newdecl, "static declaration for `%s' follows non-static"); ! /* These bits are logically part of the type, for variables. ! But not for functions ! (where qualifiers are not valid ANSI anyway). */ ! if (pedantic && TREE_CODE (olddecl) != FUNCTION_DECL && (TREE_READONLY (newdecl) != TREE_READONLY (olddecl) || TREE_THIS_VOLATILE (newdecl) != TREE_THIS_VOLATILE (olddecl))) *************** *** 1370,1375 **** /* Since the type is OLDDECL's, make OLDDECL's size go with. */ DECL_SIZE (newdecl) = DECL_SIZE (olddecl); ! if (DECL_ALIGN (olddecl) > DECL_ALIGN (newdecl)) ! DECL_ALIGN (newdecl) = DECL_ALIGN (olddecl); } --- 1384,1390 ---- /* Since the type is OLDDECL's, make OLDDECL's size go with. */ DECL_SIZE (newdecl) = DECL_SIZE (olddecl); ! if (TREE_CODE (olddecl) != FUNCTION_DECL) ! if (DECL_ALIGN (olddecl) > DECL_ALIGN (newdecl)) ! DECL_ALIGN (newdecl) = DECL_ALIGN (olddecl); } *************** *** 1551,1564 **** } ! /* If declaring a type as a typedef, and the type has no known ! typedef name, install this TYPE_DECL as its typedef name. If ! generating prototypes, *don't* assign the current name to the ! existing type node, but rather give the name its own associated ! type node. This new type node is created as a type variant of ! the existing type node, but it is essentially identical to the ! existing one. Obviously, we don't generate these type variants ! if the node that we are working on is a standard type and it has ! not yet been assigned a name. In that case we must allow the ! standard type to given its standard name (by the compiler). Since all standard types are effectively declared at line zero in the source file, we can easily check to see if we are working --- 1566,1608 ---- } ! /* If we are processing a typedef statement, generate a whole new ! ..._TYPE node (which will be just an variant of the existing ! ..._TYPE node with identical properties) and then install the ! TYPE_DECL node generated to represent the typedef name as the ! TYPE_NAME of this brand new (duplicate) ..._TYPE node. ! ! The whole point here is to end up with a situation where each ! and every ..._TYPE node the compiler creates will be uniquely ! associated with AT MOST one node representing a typedef name. ! This way, even though the compiler substitutes corresponding ! ..._TYPE nodes for TYPE_DECL (i.e. "typedef name") nodes very ! early on, later parts of the compiler can always do the reverse ! translation and get back the corresponding typedef name. For ! example, given: ! ! typedef struct S MY_TYPE; ! MY_TYPE object; ! ! Later parts of the compiler might only know that `object' was of ! type `struct S' if if were not for code just below. With this ! code however, later parts of the compiler see something like: ! ! struct S' == struct S ! typedef struct S' MY_TYPE; ! struct S' object; ! ! And they can then deduce (from the node for type struct S') that ! the original object declaration was: ! ! MY_TYPE object; ! ! Being able to do this is important for proper support of protoize, ! and also for generating precise symbolic debugging information ! which takes full account of the programmer's (typedef) vocabulary. ! ! Obviously, we don't want to generate a duplicate ..._TYPE node if ! the TYPE_DECL node that we are now processing really represents a ! standard built-in type. ! Since all standard types are effectively declared at line zero in the source file, we can easily check to see if we are working *************** *** 1576,1581 **** tree tt = TREE_TYPE (x); ! tt = c_build_type_variant (tt, ! TYPE_READONLY (tt), TYPE_VOLATILE (tt)); TYPE_NAME (tt) = x; TREE_TYPE (x) = tt; --- 1620,1624 ---- tree tt = TREE_TYPE (x); ! tt = build_type_copy (tt); TYPE_NAME (tt) = x; TREE_TYPE (x) = tt; *************** *** 1769,1772 **** --- 1812,1817 ---- /* Maybe warn if shadowing something else. */ else if (warn_shadow && !TREE_EXTERNAL (x) + /* No shadow warnings for internally generated vars. */ + && !DECL_IGNORED_P (x) /* No shadow warnings for vars made for inlining. */ && ! DECL_FROM_INLINE (x)) *************** *** 2214,2219 **** /* Either char* or void*. */ tree traditional_ptr_type_node; ! /* Data type of memcpy. */ ! tree memcpy_ftype; int wchar_type_size; tree temp; --- 2259,2265 ---- /* Either char* or void*. */ tree traditional_ptr_type_node; ! /* Data types of memcpy and strlen. */ ! tree memcpy_ftype, strlen_ftype; ! tree void_ftype_any; int wchar_type_size; tree temp; *************** *** 2376,2379 **** --- 2422,2428 ---- endlink = tree_cons (NULL_TREE, void_type_node, NULL_TREE); + void_ftype_any + = build_function_type (void_type_node, 0); + double_ftype_double = build_function_type (double_type_node, *************** *** 2433,2438 **** endlink))); ! sizet_ftype_string /* strlen prototype */ ! = build_function_type (sizetype, tree_cons (NULL_TREE, const_string_type_node, endlink)); --- 2482,2487 ---- endlink))); ! strlen_ftype /* strlen prototype */ ! = build_function_type (flag_traditional ? integer_type_node : sizetype, tree_cons (NULL_TREE, const_string_type_node, endlink)); *************** *** 2474,2480 **** endlink)), BUILT_IN_ALLOCA, "alloca"); ! if (! flag_no_builtin) { - tree exit_type; temp = builtin_function ("alloca", build_function_type (ptr_type_node, --- 2523,2528 ---- endlink)), BUILT_IN_ALLOCA, "alloca"); ! if (! flag_no_builtin && !flag_no_nonansi_builtin) { temp = builtin_function ("alloca", build_function_type (ptr_type_node, *************** *** 2485,2506 **** /* Suppress error if redefined as a non-function. */ DECL_BUILT_IN_NONANSI (temp) = 1; ! /* Declare these functions volatile ! to avoid spurious "control drops through" warnings. */ ! /* Don't specify the argument types, to avoid errors ! from certain code which isn't valid in ANSI but which exists. */ ! temp = builtin_function ("abort", ! build_function_type (void_type_node, 0), ! NOT_BUILT_IN, 0); ! TREE_THIS_VOLATILE (temp) = 1; ! TREE_SIDE_EFFECTS (temp) = 1; ! /* Suppress error if redefined as a non-function. */ ! DECL_BUILT_IN_NONANSI (temp) = 1; ! exit_type = build_function_type (void_type_node, 0); ! temp = builtin_function ("exit", exit_type, NOT_BUILT_IN, 0); ! TREE_THIS_VOLATILE (temp) = 1; ! TREE_SIDE_EFFECTS (temp) = 1; ! /* Suppress error if redefined as a non-function. */ ! DECL_BUILT_IN_NONANSI (temp) = 1; ! temp = builtin_function ("_exit", exit_type, NOT_BUILT_IN, 0); TREE_THIS_VOLATILE (temp) = 1; TREE_SIDE_EFFECTS (temp) = 1; --- 2533,2537 ---- /* Suppress error if redefined as a non-function. */ DECL_BUILT_IN_NONANSI (temp) = 1; ! temp = builtin_function ("_exit", void_ftype_any, NOT_BUILT_IN, 0); TREE_THIS_VOLATILE (temp) = 1; TREE_SIDE_EFFECTS (temp) = 1; *************** *** 2545,2549 **** builtin_function ("__builtin_strcpy", string_ftype_ptr_ptr, BUILT_IN_STRCPY, "strcpy"); ! builtin_function ("__builtin_strlen", sizet_ftype_string, BUILT_IN_STRLEN, "strlen"); builtin_function ("__builtin_fsqrt", double_ftype_double, --- 2576,2580 ---- builtin_function ("__builtin_strcpy", string_ftype_ptr_ptr, BUILT_IN_STRCPY, "strcpy"); ! builtin_function ("__builtin_strlen", strlen_ftype, BUILT_IN_STRLEN, "strlen"); builtin_function ("__builtin_fsqrt", double_ftype_double, *************** *** 2552,2557 **** for these functions, since applications cannot validly use them with any other meaning. ! However, a traditional C program can do so. */ ! if (!flag_traditional) { builtin_function ("abs", int_ftype_int, BUILT_IN_ABS, 0); --- 2583,2588 ---- for these functions, since applications cannot validly use them with any other meaning. ! However, honor the -fno-builtin option. */ ! if (!flag_no_builtin) { builtin_function ("abs", int_ftype_int, BUILT_IN_ABS, 0); *************** *** 2562,2570 **** builtin_function ("strcmp", int_ftype_string_string, BUILT_IN_STRCMP, 0); builtin_function ("strcpy", string_ftype_ptr_ptr, BUILT_IN_STRCPY, 0); ! builtin_function ("strlen", sizet_ftype_string, BUILT_IN_STRLEN, 0); ! #if 0 /* No good, since open-coded implementation fails to set errno. ! The ANSI committee made a real mistake in specifying math fns. */ builtin_function ("sqrt", double_ftype_double, BUILT_IN_FSQRT, 0); ! #endif } --- 2593,2609 ---- builtin_function ("strcmp", int_ftype_string_string, BUILT_IN_STRCMP, 0); builtin_function ("strcpy", string_ftype_ptr_ptr, BUILT_IN_STRCPY, 0); ! builtin_function ("strlen", strlen_ftype, BUILT_IN_STRLEN, 0); builtin_function ("sqrt", double_ftype_double, BUILT_IN_FSQRT, 0); ! ! /* Declare these functions volatile ! to avoid spurious "control drops through" warnings. */ ! /* Don't specify the argument types, to avoid errors ! from certain code which isn't valid in ANSI but which exists. */ ! temp = builtin_function ("abort", void_ftype_any, NOT_BUILT_IN, 0); ! TREE_THIS_VOLATILE (temp) = 1; ! TREE_SIDE_EFFECTS (temp) = 1; ! temp = builtin_function ("exit", void_ftype_any, NOT_BUILT_IN, 0); ! TREE_THIS_VOLATILE (temp) = 1; ! TREE_SIDE_EFFECTS (temp) = 1; } *************** *** 2583,2586 **** --- 2622,2628 ---- #endif + /* Create the global bindings for __FUNCTION__ and __PRETTY_FUNCTION__. */ + declare_function_name (); + start_identifier_warnings (); *************** *** 2606,2609 **** --- 2648,2656 ---- TREE_EXTERNAL (decl) = 1; TREE_PUBLIC (decl) = 1; + /* If -traditional, permit redefining a builtin function any way you like. + (Though really, if the program redefines these functions, + it probably won't work right unless compiled with -fno-builtin.) */ + if (flag_traditional && name[0] != '_') + DECL_BUILT_IN_NONANSI (decl) = 1; if (library_name) DECL_ASSEMBLER_NAME (decl) = get_identifier (library_name); *************** *** 3063,3067 **** tree parm; { ! tree decl; int old_immediate_size_expand = immediate_size_expand; /* Don't try computing parm sizes now -- wait till fn is called. */ --- 3110,3114 ---- tree parm; { ! tree decl, olddecl; int old_immediate_size_expand = immediate_size_expand; /* Don't try computing parm sizes now -- wait till fn is called. */ *************** *** 3072,3075 **** --- 3119,3128 ---- decl = grokdeclarator (TREE_VALUE (parm), TREE_PURPOSE (parm), PARM, 0); + if (DECL_NAME (decl)) + { + olddecl = lookup_name (DECL_NAME (decl)); + if (pedantic && olddecl != 0 && TREE_CODE (olddecl) == TYPE_DECL) + pedwarn_with_decl (decl, "ANSI C forbids parameter `%s' shadowing typedef"); + } decl = pushdecl (decl); *************** *** 3302,3306 **** } else if (specbits & (1 << i)) ! warning ("duplicate `%s'", IDENTIFIER_POINTER (id)); specbits |= 1 << i; goto found; --- 3355,3359 ---- } else if (specbits & (1 << i)) ! pedwarn ("duplicate `%s'", IDENTIFIER_POINTER (id)); specbits |= 1 << i; goto found; *************** *** 3453,3459 **** inlinep = !! (specbits & (1 << (int) RID_INLINE)); if (constp > 1) ! warning ("duplicate `const'"); if (volatilep > 1) ! warning ("duplicate `volatile'"); if (! flag_gen_aux_info && (TYPE_READONLY (type) || TYPE_VOLATILE (type))) type = TYPE_MAIN_VARIANT (type); --- 3506,3512 ---- inlinep = !! (specbits & (1 << (int) RID_INLINE)); if (constp > 1) ! pedwarn ("duplicate `const'"); if (volatilep > 1) ! pedwarn ("duplicate `volatile'"); if (! flag_gen_aux_info && (TYPE_READONLY (type) || TYPE_VOLATILE (type))) type = TYPE_MAIN_VARIANT (type); *************** *** 3602,3606 **** size = integer_one_node; } ! itype = build_index_type (build_int_2 (TREE_INT_CST_LOW (size) - 1, 0)); } else --- 3655,3660 ---- size = integer_one_node; } ! itype = build_index_type (size_binop (MINUS_EXPR, size, ! size_one_node)); } else *************** *** 3875,3881 **** if (type == float_type_node) DECL_ARG_TYPE (decl) = double_type_node; ! else if (TREE_CODE (type) == INTEGER_TYPE ! && TYPE_PRECISION (type) < TYPE_PRECISION (integer_type_node)) ! DECL_ARG_TYPE (decl) = integer_type_node; DECL_ARG_TYPE_AS_WRITTEN (decl) = type_as_written; --- 3929,3946 ---- if (type == float_type_node) DECL_ARG_TYPE (decl) = double_type_node; ! /* Don't use TYPE_PREISION to decide whether to promote, ! because we should convert short if it's the same size as int, ! but we should not convert long if it's the same size as int. */ ! else if (type == char_type_node || type == signed_char_type_node ! || type == unsigned_char_type_node ! || type == short_integer_type_node ! || type == short_unsigned_type_node) ! { ! if (TYPE_PRECISION (type) == TYPE_PRECISION (integer_type_node) ! && TREE_UNSIGNED (type)) ! DECL_ARG_TYPE (decl) = unsigned_type_node; ! else ! DECL_ARG_TYPE (decl) = integer_type_node; ! } DECL_ARG_TYPE_AS_WRITTEN (decl) = type_as_written; *************** *** 4178,4182 **** } ! /* Extract enumerator values and other non-parms declared with the parms. */ for (decl = parms; decl; ) { --- 4243,4248 ---- } ! /* Extract enumerator values and other non-parms declared with the parms. ! Likewise any forward parm decls that didn't have real parm decls. */ for (decl = parms; decl; ) { *************** *** 4188,4191 **** --- 4254,4263 ---- new_parms = decl; } + else if (TREE_ASM_WRITTEN (decl)) + { + error_with_decl (decl, "parameter `%s' has just a forward declaration"); + TREE_CHAIN (decl) = new_parms; + new_parms = decl; + } decl = next; } *************** *** 4250,4253 **** --- 4322,4329 ---- { enum tree_code code = TREE_CODE (TREE_VALUE (elt)); + /* An anonymous union parm type is meaningful as a GNU extension. + So don't warn for that. */ + if (code == UNION_TYPE && !pedantic) + continue; if (TREE_PURPOSE (elt) != 0) warning ("`%s %s' declared inside parameter list", *************** *** 4433,4437 **** /* Install struct as DECL_CONTEXT of each field decl. Also process specified field sizes. ! Set DECL_FRAME_SIZE to the specified size, or 0 if none specified. The specified size is found in the DECL_INITIAL. Store 0 there, except for ": 0" fields (so we can find them --- 4509,4513 ---- /* Install struct as DECL_CONTEXT of each field decl. Also process specified field sizes. ! Set DECL_FIELD_SIZE to the specified size, or 0 if none specified. The specified size is found in the DECL_INITIAL. Store 0 there, except for ": 0" fields (so we can find them *************** *** 4441,4445 **** { DECL_CONTEXT (x) = t; ! DECL_FRAME_SIZE (x) = 0; /* If any field is const, the structure type is pseudo-const. */ --- 4517,4521 ---- { DECL_CONTEXT (x) = t; ! DECL_FIELD_SIZE (x) = 0; /* If any field is const, the structure type is pseudo-const. */ *************** *** 4516,4520 **** register int width = TREE_INT_CST_LOW (DECL_INITIAL (x)); ! DECL_FRAME_SIZE (x) = width; DECL_BIT_FIELD (x) = 1; DECL_INITIAL (x) = NULL; --- 4592,4596 ---- register int width = TREE_INT_CST_LOW (DECL_INITIAL (x)); ! DECL_FIELD_SIZE (x) = width; DECL_BIT_FIELD (x) = 1; DECL_INITIAL (x) = NULL; *************** *** 4533,4538 **** } else ! /* Non-bit-fields are aligned for their type. */ ! DECL_ALIGN (x) = MAX (DECL_ALIGN (x), TYPE_ALIGN (TREE_TYPE (x))); } --- 4609,4619 ---- } else ! { ! int min_align = (DECL_PACKED (x) ? BITS_PER_UNIT ! : TYPE_ALIGN (TREE_TYPE (x))); ! /* Non-bit-fields are aligned for their type, except packed ! fields which require only BITS_PER_UNIT alignment. */ ! DECL_ALIGN (x) = MAX (DECL_ALIGN (x), min_align); ! } } *************** *** 4636,4640 **** if (DECL_BIT_FIELD (x) && TREE_CODE (TREE_TYPE (x)) == INTEGER_TYPE ! && (TREE_INT_CST_LOW (DECL_SIZE (x)) < TYPE_PRECISION (integer_type_node))) TREE_TYPE (x) = integer_type_node; --- 4717,4721 ---- if (DECL_BIT_FIELD (x) && TREE_CODE (TREE_TYPE (x)) == INTEGER_TYPE ! && (TYPE_PRECISION (TREE_TYPE (x)) < TYPE_PRECISION (integer_type_node))) TREE_TYPE (x) = integer_type_node; *************** *** 4728,4731 **** --- 4809,4813 ---- enum_next_value = integer_zero_node; + enum_overflow = 0; return enumtype; *************** *** 4820,4824 **** TREE_TYPE (TREE_PURPOSE (pair)) = enumtype; DECL_SIZE (TREE_PURPOSE (pair)) = TYPE_SIZE (enumtype); ! DECL_ALIGN (TREE_PURPOSE (pair)) = TYPE_ALIGN (enumtype); } --- 4902,4907 ---- TREE_TYPE (TREE_PURPOSE (pair)) = enumtype; DECL_SIZE (TREE_PURPOSE (pair)) = TYPE_SIZE (enumtype); ! if (TREE_CODE (TREE_PURPOSE (pair)) != FUNCTION_DECL) ! DECL_ALIGN (TREE_PURPOSE (pair)) = TYPE_ALIGN (enumtype); } *************** *** 4865,4869 **** in the default. */ if (value == 0) ! value = enum_next_value; if (pedantic && ! int_fits_type_p (value, integer_type_node)) --- 4948,4956 ---- in the default. */ if (value == 0) ! { ! value = enum_next_value; ! if (enum_overflow) ! error ("overflow in enumeration values"); ! } if (pedantic && ! int_fits_type_p (value, integer_type_node)) *************** *** 4875,4878 **** --- 4962,4966 ---- /* Set basis for default for next value. */ enum_next_value = build_binary_op (PLUS_EXPR, value, integer_one_node, 0); + enum_overflow = tree_int_cst_lt (enum_next_value, value); /* Now create a declaration for the enum value name. */ *************** *** 5290,5314 **** /* Type for passing arg must be consistent with that declared for the arg. */ ! if (! comptypes (DECL_ARG_TYPE (parm), TREE_VALUE (type)) ! /* If -traditional, allow `unsigned int' instead of `int' ! in the prototype. */ ! && (! (flag_traditional ! && DECL_ARG_TYPE (parm) == integer_type_node ! && TREE_VALUE (type) == unsigned_type_node))) { ! error ("argument `%s' doesn't match function prototype", ! IDENTIFIER_POINTER (DECL_NAME (parm))); ! if (DECL_ARG_TYPE (parm) == integer_type_node ! && TREE_VALUE (type) == TREE_TYPE (parm)) ! { ! error ("a formal parameter type that promotes to `int'"); ! error ("can match only `int' in the prototype"); ! } ! if (DECL_ARG_TYPE (parm) == double_type_node ! && TREE_VALUE (type) == TREE_TYPE (parm)) { ! error ("a formal parameter type that promotes to `double'"); ! error ("can match only `double' in the prototype"); } } } --- 5378,5408 ---- /* Type for passing arg must be consistent with that declared for the arg. */ ! if (! comptypes (DECL_ARG_TYPE (parm), TREE_VALUE (type))) { ! if (TREE_TYPE (parm) == TREE_VALUE (type)) { ! /* Adjust argument to match prototype. E.g. a previous ! `int foo(float);' prototype causes ! `int foo(x) float x; {...}' to be treated like ! `int foo(float x) {...}'. This is particularly ! useful for argument types like uid_t. */ ! DECL_ARG_TYPE (parm) = TREE_TYPE (parm); ! #ifdef PROMOTE_PROTOTYPES ! if (TREE_CODE (TREE_TYPE (parm)) == INTEGER_TYPE ! && TYPE_PRECISION (TREE_TYPE (parm)) ! < TYPE_PRECISION (integer_type_node)) ! DECL_ARG_TYPE (parm) = integer_type_node; ! #endif ! if (pedantic) ! warning ("promoted argument `%s' doesn't match prototype", ! IDENTIFIER_POINTER (DECL_NAME (parm))); } + /* If -traditional, allow `int' argument to match + `unsigned' prototype. */ + else if (! (flag_traditional + && TREE_TYPE (parm) == integer_type_node + && TREE_VALUE (type) == unsigned_type_node)) + error ("argument `%s' doesn't match prototype", + IDENTIFIER_POINTER (DECL_NAME (parm))); } } *************** *** 5385,5388 **** --- 5479,5486 ---- mark_varargs (); + /* Declare __FUNCTION__ and __PRETTY_FUNCTION__ for this function. */ + + declare_function_name (); + /* Set up parameters and prepare for return, for the function. */ *************** *** 5653,5656 **** --- 5751,5757 ---- struct c_function *p = (struct c_function *) xmalloc (sizeof (struct c_function)); + + if (pedantic) + pedwarn ("ANSI C forbids nested functions"); push_function_context (); diff -rc2N gcc-2.1/c-lex.c gcc-2.2.1/c-lex.c *** gcc-2.1/c-lex.c Fri Mar 13 23:58:29 1992 --- gcc-2.2.1/c-lex.c Thu Jun 4 14:36:38 1992 *************** *** 354,360 **** register int c; { ! #if 0 ! register int inside; ! #endif for (;;) --- 354,358 ---- register int c; { ! static int newline_warning = 0; for (;;) *************** *** 362,408 **** switch (c) { ! /* Don't recognize comments in cc1: all comments are removed by cpp, ! and cpp output can include / and * consecutively as operators. */ ! #if 0 ! case '/': ! c = getc (finput); ! if (c != '*') ! { ! ungetc (c, finput); ! return '/'; ! } ! ! c = getc (finput); ! ! inside = 1; ! while (inside) ! { ! if (c == '*') ! { ! while (c == '*') ! c = getc (finput); ! ! if (c == '/') ! { ! inside = 0; ! c = getc (finput); ! } ! } ! else if (c == '\n') ! { ! lineno++; ! c = getc (finput); ! } ! else if (c == EOF) ! { ! error ("unterminated comment"); ! break; ! } ! else ! c = getc (finput); ! } ! ! break; ! #endif case '\n': --- 360,366 ---- switch (c) { ! /* We don't recognize comments here, because ! cpp output can include / and * consecutively as operators. ! Also, there's no need, since cpp removes all comments. */ case '\n': *************** *** 413,419 **** case '\t': case '\f': - #if 0 /* ANSI says no. */ - case '\r': - #endif case '\v': case '\b': --- 371,374 ---- *************** *** 421,424 **** --- 376,391 ---- break; + case '\r': + /* ANSI C says the effects of a carriage return in a source file + are undefined. */ + if (pedantic && !newline_warning) + { + warning ("carriage return in source file"); + warning ("(we only warn about the first carriage return)"); + newline_warning = 1; + } + c = getc (finput); + break; + case '\\': c = getc (finput); *************** *** 956,962 **** switch (c) { - case '\r': - if (!flag_traditional) /* ANSI says no */ - goto found_nonwhite; case ' ': case '\t': --- 923,926 ---- *************** *** 967,970 **** --- 931,937 ---- break; + case '\r': + /* Call skip_white_space so we can warn if appropriate. */ + case '\n': case '/': *************** *** 1103,1106 **** --- 1070,1085 ---- if (lastiddecl != 0 && TREE_CODE (lastiddecl) == TYPE_DECL) value = TYPENAME; + /* A user-invisible read-only initialized variable + should be replaced by its value. + We handle only strings since that's the only case used in C. */ + else if (lastiddecl != 0 && TREE_CODE (lastiddecl) == VAR_DECL + && DECL_IGNORED_P (lastiddecl) + && TREE_READONLY (lastiddecl) + && DECL_INITIAL (lastiddecl) != 0 + && TREE_CODE (DECL_INITIAL (lastiddecl)) == STRING_CST) + { + yylval.ttype = DECL_INITIAL (lastiddecl); + value = STRING; + } else if (doing_objc_thang) { *************** *** 1312,1316 **** } #ifdef ERANGE ! if (errno == ERANGE && !flag_traditional) { char *p1 = token_buffer; --- 1291,1295 ---- } #ifdef ERANGE ! if (errno == ERANGE && !flag_traditional && pedantic) { char *p1 = token_buffer; *************** *** 1332,1336 **** so test the value to distinguish overflow from that. */ if (*p1 != 0 && (value > 1.0 || value < -1.0)) ! warning ("floating point number exceeds range of `double'"); } #endif --- 1311,1315 ---- so test the value to distinguish overflow from that. */ if (*p1 != 0 && (value > 1.0 || value < -1.0)) ! pedwarn ("floating point number exceeds range of `double'"); } #endif *************** *** 1343,1349 **** if (f_seen) error ("two `f's in floating constant"); ! f_seen = 1; ! type = float_type_node; ! value = REAL_VALUE_TRUNCATE (TYPE_MODE (type), value); } else if (c == 'l' || c == 'L') --- 1322,1333 ---- if (f_seen) error ("two `f's in floating constant"); ! else ! { ! f_seen = 1; ! type = float_type_node; ! value = REAL_VALUE_TRUNCATE (TYPE_MODE (type), value); ! if (REAL_VALUE_ISINF (value) && pedantic) ! pedwarn ("floating point number exceeds range of `float'"); ! } } else if (c == 'l' || c == 'L') *************** *** 1463,1470 **** } if (warn) ! warning ("integer constant out of range"); } else if (overflow) ! warning ("integer constant larger than compiler can handle"); /* If it overflowed our internal buffer, then make it unsigned. --- 1447,1454 ---- } if (warn) ! pedwarn ("integer constant out of range"); } else if (overflow) ! pedwarn ("integer constant larger than compiler can handle"); /* If it overflowed our internal buffer, then make it unsigned. *************** *** 1614,1620 **** != TREE_UNSIGNED (ansi_type)) warning ("integer constant is unsigned in ANSI C, signed with -traditional"); ! else abort (); } #endif TREE_TYPE (yylval.ttype) = type; --- 1598,1608 ---- != TREE_UNSIGNED (ansi_type)) warning ("integer constant is unsigned in ANSI C, signed with -traditional"); ! else ! warning ("width of integer constant may change on other systems with -traditional"); } #endif + + if (!flag_traditional && !int_fits_type_p (yylval.ttype, type)) + pedwarn ("integer constant out of range"); TREE_TYPE (yylval.ttype) = type; diff -rc2N gcc-2.1/c-parse.y gcc-2.2.1/c-parse.y *** gcc-2.1/c-parse.y Thu Mar 12 00:27:18 1992 --- gcc-2.2.1/c-parse.y Thu May 21 14:08:40 1992 *************** *** 338,341 **** --- 338,342 ---- TREE_CONSTANT ($$) = 1; } /* This seems to be impossible on some machines, so let's turn it off. + You can use __builtin_next_arg to find the anonymous stack args. | '&' ELLIPSIS { tree types = TYPE_ARG_TYPES (TREE_TYPE (current_function_decl)); *************** *** 517,520 **** --- 518,524 ---- /* The statements have side effects, so the group does. */ TREE_SIDE_EFFECTS (rtl_exp) = 1; + /* Clear TREE_USED which is always set by poplevel. This + block will only be used if the BIND_EXPR is used. */ + TREE_USED ($3) = 0; /* Make a BIND_EXPR for the BLOCK already made. */ *************** *** 779,782 **** --- 783,796 ---- IDENTIFIER_POINTER ($1)); $$ = $1; } + | IDENTIFIER '(' IDENTIFIER ')' + { /* If not "mode (m)", then issue warning. */ + if (strcmp (IDENTIFIER_POINTER ($1), "mode") != 0) + { + warning ("`%s' attribute directive ignored", + IDENTIFIER_POINTER ($1)); + $$ = $1; + } + else + $$ = tree_cons ($1, $3); } | IDENTIFIER '(' CONSTANT ')' { /* if not "aligned(n)", then issue warning */ *************** *** 1230,1233 **** --- 1244,1262 ---- ; + /* This is a subroutine of stmt. + It is used twice, once for valid DO statements + and once for catching errors in parsing the end test. */ + do_stmt_start: + DO + { stmt_count++; + emit_line_note ($-1, $0); + /* See comment in `while' alternative, above. */ + emit_nop (); + expand_start_loop_continue_elsewhere (1); + position_after_white_space (); } + lineno_labeled_stmt WHILE + { expand_loop_continue_here (); } + ; + save_filename: { $$ = input_filename; } *************** *** 1301,1308 **** I think it ought to work to put the nop after the line number. We will see. --rms, July 15, 1991. */ ! emit_nop (); ! expand_start_loop (1); } '(' expr ')' ! { emit_line_note (input_filename, lineno); expand_exit_loop_if_false (0, truthvalue_conversion ($4)); position_after_white_space (); } --- 1330,1340 ---- I think it ought to work to put the nop after the line number. We will see. --rms, July 15, 1991. */ ! emit_nop (); } '(' expr ')' ! { /* Don't start the loop till we have succeeded ! in parsing the end test. This is to make sure ! that we end every loop we start. */ ! expand_start_loop (1); ! emit_line_note (input_filename, lineno); expand_exit_loop_if_false (0, truthvalue_conversion ($4)); position_after_white_space (); } *************** *** 1309,1326 **** lineno_labeled_stmt { expand_end_loop (); } ! | DO ! { stmt_count++; ! emit_line_note ($-1, $0); ! /* See comment in `while' alternative, above. */ ! emit_nop (); ! expand_start_loop_continue_elsewhere (1); ! position_after_white_space (); } ! lineno_labeled_stmt WHILE ! { expand_loop_continue_here (); } '(' expr ')' ';' { emit_line_note (input_filename, lineno); ! expand_exit_loop_if_false (0, truthvalue_conversion ($7)); expand_end_loop (); clear_momentary (); } | FOR '(' xexpr ';' --- 1341,1354 ---- lineno_labeled_stmt { expand_end_loop (); } ! | do_stmt_start '(' expr ')' ';' { emit_line_note (input_filename, lineno); ! expand_exit_loop_if_false (0, truthvalue_conversion ($3)); expand_end_loop (); clear_momentary (); } + /* This rule is needed to make sure we end every loop we start. */ + | do_stmt_start error + { expand_end_loop (); + clear_momentary (); } | FOR '(' xexpr ';' *************** *** 1330,1342 **** emit_nop (); if ($3) c_expand_expr_stmt ($3); ! expand_start_loop_continue_elsewhere (1); } xexpr ';' ! { emit_line_note (input_filename, lineno); ! if ($6) ! expand_exit_loop_if_false (0, truthvalue_conversion ($6)); } xexpr ')' ! /* Don't let the tree nodes for $9 be discarded ! by clear_momentary during the parsing of the next stmt. */ ! { push_momentary (); position_after_white_space (); } lineno_labeled_stmt --- 1358,1382 ---- emit_nop (); if ($3) c_expand_expr_stmt ($3); ! /* Next step is to call expand_start_loop_continue_elsewhere, ! but wait till after we parse the entire for (...). ! Otherwise, invalid input might cause us to call that ! fn without calling expand_end_loop. */ ! } xexpr ';' ! /* Can't emit now; wait till after expand_start_loop... */ ! { $7 = lineno; ! $$ = input_filename; } xexpr ')' ! { ! /* Start the loop. Doing this after parsing ! all the expressions ensures we will end the loop. */ ! expand_start_loop_continue_elsewhere (1); ! /* Emit the end-test, with a line number. */ ! emit_line_note ($8, $7); ! if ($6) ! expand_exit_loop_if_false (0, truthvalue_conversion ($6)); ! /* Don't let the tree nodes for $9 be discarded by ! clear_momentary during the parsing of the next stmt. */ ! push_momentary (); position_after_white_space (); } lineno_labeled_stmt *************** *** 1562,1565 **** --- 1602,1607 ---- | parms ';' { tree parm; + if (pedantic) + pedwarn ("ANSI C forbids forward parameter declarations"); /* Mark the forward decls as such. */ for (parm = getdecls (); parm; parm = TREE_CHAIN (parm)) *************** *** 1623,1635 **** parmlist_or_identifiers_1: ! parmlist_2 ')' ! | parms ';' ! { tree parm; ! /* Mark the forward decls as such. */ ! for (parm = getdecls (); parm; parm = TREE_CHAIN (parm)) ! TREE_ASM_WRITTEN (parm) = 1; ! clear_parm_order (); } ! parmlist_or_identifiers_1 ! { $$ = $4; } | identifiers ')' { tree t; --- 1665,1669 ---- parmlist_or_identifiers_1: ! parmlist_1 | identifiers ')' { tree t; *************** *** 1638,1643 **** error ("`...' in old-style identifier list"); $$ = tree_cons (NULL_TREE, NULL_TREE, $1); } - | error ')' - { $$ = tree_cons (NULL_TREE, NULL_TREE, NULL_TREE); } ; --- 1672,1675 ---- diff -rc2N gcc-2.1/c-typeck.c gcc-2.2.1/c-typeck.c *** gcc-2.1/c-typeck.c Sun Mar 22 15:04:27 1992 --- gcc-2.2.1/c-typeck.c Thu May 28 01:20:58 1992 *************** *** 783,786 **** --- 783,797 ---- return size_int (TYPE_ALIGN (type) / BITS_PER_UNIT); } + + /* Print a warning if a constant expression had overflow in folding. + This doesn't really work--it is waiting for changes in fold. */ + + void + constant_expression_warning (value) + tree value; + { + if (TREE_CODE (value) == NON_LVALUE_EXPR && TREE_CONSTANT_OVERFLOW (value)) + pedwarn ("overflow in constant expression"); + } /* Implement the __alignof keyword: Return the minimum required *************** *** 1148,1159 **** tree rval, type; - index = default_conversion (index); - if (index != error_mark_node - && TREE_CODE (TREE_TYPE (index)) != INTEGER_TYPE) - { - error ("array subscript is not an integer"); - return error_mark_node; - } - /* Subscripting with type char is likely to lose on a machine where chars are signed. --- 1159,1162 ---- *************** *** 1166,1169 **** --- 1169,1182 ---- warning ("array subscript has type `char'"); + /* Apply default promotions *after* noticing character types. */ + index = default_conversion (index); + + /* Require integer *after* promotion, for sake of enums. */ + if (TREE_CODE (TREE_TYPE (index)) != INTEGER_TYPE) + { + error ("array subscript is not an integer"); + return error_mark_node; + } + /* An array that is indexed by a non-constant cannot be stored in a register; we must be able to do *************** *** 1715,1718 **** --- 1728,1735 ---- if (i == fci->pointer_count && wanted_type != 0 && wanted_type != cur_type + /* If we want `void *', allow any pointer type. + (Anything else would already have got a warning.) */ + && ! (wanted_type == void_type_node + && fci->pointer_count > 0) /* Don't warn about differences merely in signedness. */ && !(TREE_CODE (wanted_type) == INTEGER_TYPE *************** *** 1725,1731 **** this = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (wanted_type))); that = 0; ! if (TYPE_NAME (cur_type) != 0) ! if (DECL_NAME (TYPE_NAME (cur_type)) != 0) ! that = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (cur_type))); /* A nameless type can't possibly match what the format wants. --- 1742,1751 ---- this = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (wanted_type))); that = 0; ! if (TYPE_NAME (cur_type) != 0 ! && TREE_CODE (cur_type) != INTEGER_TYPE ! && !(TREE_CODE (cur_type) == POINTER_TYPE ! && TREE_CODE (TREE_TYPE (cur_type)) == INTEGER_TYPE) ! && DECL_NAME (TYPE_NAME (cur_type)) != 0) ! that = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (cur_type))); /* A nameless type can't possibly match what the format wants. *************** *** 1950,1962 **** { int formal_prec = TYPE_PRECISION (type); - int actual_prec = TYPE_PRECISION (TREE_TYPE (val)); - int int_prec = TYPE_PRECISION (integer_type_node); if (TREE_CODE (type) != REAL_TYPE && TREE_CODE (TREE_TYPE (val)) == REAL_TYPE) ! warning ("floating argument converted to integer"); else if (TREE_CODE (type) == REAL_TYPE && TREE_CODE (TREE_TYPE (val)) != REAL_TYPE) ! warning ("integer argument converted to floating"); else if (TREE_CODE (type) == REAL_TYPE && TREE_CODE (TREE_TYPE (val)) == REAL_TYPE) --- 1970,1980 ---- { int formal_prec = TYPE_PRECISION (type); if (TREE_CODE (type) != REAL_TYPE && TREE_CODE (TREE_TYPE (val)) == REAL_TYPE) ! warn_for_assignment ("%s as integer rather than floating due to prototype", (char *) 0, name, parmnum + 1); else if (TREE_CODE (type) == REAL_TYPE && TREE_CODE (TREE_TYPE (val)) != REAL_TYPE) ! warn_for_assignment ("%s as floating rather than integer due to prototype", (char *) 0, name, parmnum + 1); else if (TREE_CODE (type) == REAL_TYPE && TREE_CODE (TREE_TYPE (val)) == REAL_TYPE) *************** *** 1963,1969 **** { /* Warn if any argument is passed as `float', ! since withtout a prototype it would be `double'. */ if (formal_prec == TYPE_PRECISION (float_type_node)) ! warning ("floating argument passed as `float' rather than `double'"); } /* Detect integer changing in width or signedness. */ --- 1981,1987 ---- { /* Warn if any argument is passed as `float', ! since without a prototype it would be `double'. */ if (formal_prec == TYPE_PRECISION (float_type_node)) ! warn_for_assignment ("%s as `float' rather than `double' due to prototype", (char *) 0, name, parmnum + 1); } /* Detect integer changing in width or signedness. */ *************** *** 1976,1981 **** tree type1 = TREE_TYPE (would_have_been); ! if (TYPE_PRECISION (type) != TYPE_PRECISION (type)) ! warning ("prototype changes width used for integer argument"); else if (TREE_UNSIGNED (type) == TREE_UNSIGNED (type1)) ; --- 1994,2004 ---- tree type1 = TREE_TYPE (would_have_been); ! if (TREE_CODE (type) == ENUMERAL_TYPE ! && type == TREE_TYPE (val)) ! /* No warning if function asks for enum ! and the actual arg is that enum type. */ ! ; ! else if (formal_prec != TYPE_PRECISION (type1)) ! warn_for_assignment ("%s with different width due to prototype", (char *) 0, name, parmnum + 1); else if (TREE_UNSIGNED (type) == TREE_UNSIGNED (type1)) ; *************** *** 1985,1992 **** if a constant value is unaffected. */ ; else if (TREE_UNSIGNED (type)) ! warning ("argument passed as unsigned due to prototype"); else ! warning ("argument passed as signed due to prototype"); } } --- 2008,2021 ---- if a constant value is unaffected. */ ; + else if (TREE_CODE (TREE_TYPE (val)) == ENUMERAL_TYPE + && int_fits_type_p (TYPE_MIN_VALUE (TREE_TYPE (val)), type) + && int_fits_type_p (TYPE_MAX_VALUE (TREE_TYPE (val)), type)) + /* Change in signedness doesn't matter + if an enum value is unaffected. */ + ; else if (TREE_UNSIGNED (type)) ! warn_for_assignment ("%s as unsigned due to prototype", (char *) 0, name, parmnum + 1); else ! warn_for_assignment ("%s as signed due to prototype", (char *) 0, name, parmnum + 1); } } *************** *** 2289,2292 **** --- 2318,2322 ---- case TRUNC_MOD_EXPR: + case FLOOR_MOD_EXPR: if (code0 == INTEGER_TYPE && code1 == INTEGER_TYPE) shorten = 1; *************** *** 2540,2549 **** final_type = result_type; ! /* Handle the case that OP0 does not *contain* a conversion but it *requires* conversion to FINAL_TYPE. */ ! if (op0 == arg0 && TREE_TYPE (op0) != final_type) unsigned0 = TREE_UNSIGNED (TREE_TYPE (op0)); ! if (op1 == arg1 && TREE_TYPE (op1) != final_type) unsigned1 = TREE_UNSIGNED (TREE_TYPE (op1)); --- 2570,2583 ---- final_type = result_type; ! /* Handle the case that OP0 (or OP1) does not *contain* a conversion but it *requires* conversion to FINAL_TYPE. */ ! if ((TYPE_PRECISION (TREE_TYPE (op0)) ! == TYPE_PRECISION (TREE_TYPE (arg0))) ! && TREE_TYPE (op0) != final_type) unsigned0 = TREE_UNSIGNED (TREE_TYPE (op0)); ! if ((TYPE_PRECISION (TREE_TYPE (op1)) ! == TYPE_PRECISION (TREE_TYPE (arg1))) ! && TREE_TYPE (op1) != final_type) unsigned1 = TREE_UNSIGNED (TREE_TYPE (op1)); *************** *** 2933,2937 **** if (typecode == POINTER_TYPE) { ! if (pedantic && (TREE_CODE (TREE_TYPE (result_type)) == FUNCTION_TYPE || TREE_CODE (TREE_TYPE (result_type)) == VOID_TYPE)) --- 2967,2971 ---- if (typecode == POINTER_TYPE) { ! if ((pedantic || warn_pointer_arith) && (TREE_CODE (TREE_TYPE (result_type)) == FUNCTION_TYPE || TREE_CODE (TREE_TYPE (result_type)) == VOID_TYPE)) *************** *** 3000,3004 **** /* Report a read-only lvalue. */ ! if (TYPE_READONLY (TREE_TYPE (arg))) readonly_warning (arg, ((code == PREINCREMENT_EXPR --- 3034,3038 ---- /* Report a read-only lvalue. */ ! if (TREE_READONLY (arg)) readonly_warning (arg, ((code == PREINCREMENT_EXPR *************** *** 3319,3323 **** case PARM_DECL: case RESULT_DECL: ! if (TREE_REGDECL (x) && !TREE_ADDRESSABLE (x)) { if (TREE_PUBLIC (x)) --- 3353,3369 ---- case PARM_DECL: case RESULT_DECL: ! if (TREE_REGDECL (x) && !TREE_ADDRESSABLE (x) ! && TREE_NONLOCAL (x)) ! { ! if (TREE_PUBLIC (x)) ! { ! error ("global register variable `%s' used in nested function", ! IDENTIFIER_POINTER (DECL_NAME (x))); ! return 0; ! } ! pedwarn ("register variable `%s' used in nested function", ! IDENTIFIER_POINTER (DECL_NAME (x))); ! } ! else if (TREE_REGDECL (x) && !TREE_ADDRESSABLE (x)) { if (TREE_PUBLIC (x)) *************** *** 3541,3545 **** if (TREE_CHAIN (list) == 0) { ! #if 0 /* If something inside inhibited lvalueness, we shoukd not override. */ /* Consider (x, y+0), which is not an lvalue since y+0 is not. */ --- 3587,3591 ---- if (TREE_CHAIN (list) == 0) { ! #if 0 /* If something inside inhibited lvalueness, we should not override. */ /* Consider (x, y+0), which is not an lvalue since y+0 is not. */ *************** *** 4178,4181 **** --- 4224,4230 ---- #endif + /* ANSI wants warnings about out-of-range constant initializers. */ + constant_expression_warning (value); + DECL_INITIAL (decl) = value; } *************** *** 4335,4338 **** --- 4384,4388 ---- static char message[] = "initialization of `%s'"; register int needed = sizeof (message) + spelling_length () + 1; + char *temp; if (size < 0) *************** *** 4341,4345 **** buffer = (char *) xrealloc (buffer, size = needed); ! sprintf (buffer, message, print_spelling (alloca (needed))); return buffer; } --- 4391,4396 ---- buffer = (char *) xrealloc (buffer, size = needed); ! temp = (char *) alloca (needed); ! sprintf (buffer, message, print_spelling (temp)); return buffer; } *************** *** 4354,4358 **** If OFWHAT is null, the component name is stored on the spelling stack. ! If the compoment name is a null string, then LOCAL is omitted entirely. */ void --- 4405,4409 ---- If OFWHAT is null, the component name is stored on the spelling stack. ! If the component name is a null string, then LOCAL is omitted entirely. */ void *************** *** 4380,4384 **** If OFWHAT is null, the component name is stored on the spelling stack. ! If the compoment name is a null string, then LOCAL is omitted entirely. */ void --- 4431,4435 ---- If OFWHAT is null, the component name is stored on the spelling stack. ! If the component name is a null string, then LOCAL is omitted entirely. */ void *************** *** 4430,4433 **** --- 4481,4485 ---- int raw_constructor = TREE_CODE (init) == CONSTRUCTOR && TREE_TYPE (init) == 0; + tree inside_init = init; /* By default, assume we use one element from a list. *************** *** 4445,4455 **** /* Strip NON_LVALUE_EXPRs since we aren't using as an lvalue. */ if (TREE_CODE (init) == NON_LVALUE_EXPR) ! init = TREE_OPERAND (init, 0); ! if (init && raw_constructor ! && CONSTRUCTOR_ELTS (init) != 0 ! && TREE_CHAIN (CONSTRUCTOR_ELTS (init)) == 0) { ! element = TREE_VALUE (CONSTRUCTOR_ELTS (init)); /* Strip NON_LVALUE_EXPRs since we aren't using as an lvalue. */ if (element && TREE_CODE (element) == NON_LVALUE_EXPR) --- 4497,4507 ---- /* Strip NON_LVALUE_EXPRs since we aren't using as an lvalue. */ if (TREE_CODE (init) == NON_LVALUE_EXPR) ! inside_init = TREE_OPERAND (init, 0); ! if (inside_init && raw_constructor ! && CONSTRUCTOR_ELTS (inside_init) != 0 ! && TREE_CHAIN (CONSTRUCTOR_ELTS (inside_init)) == 0) { ! element = TREE_VALUE (CONSTRUCTOR_ELTS (inside_init)); /* Strip NON_LVALUE_EXPRs since we aren't using as an lvalue. */ if (element && TREE_CODE (element) == NON_LVALUE_EXPR) *************** *** 4468,4475 **** || typ1 == unsigned_wchar_type_node || typ1 == signed_wchar_type_node) ! && ((init && TREE_CODE (init) == STRING_CST) || (element && TREE_CODE (element) == STRING_CST))) { ! tree string = element ? element : init; if ((TYPE_MAIN_VARIANT (TREE_TYPE (TREE_TYPE (string))) --- 4520,4527 ---- || typ1 == unsigned_wchar_type_node || typ1 == signed_wchar_type_node) ! && ((inside_init && TREE_CODE (inside_init) == STRING_CST) || (element && TREE_CODE (element) == STRING_CST))) { ! tree string = element ? element : inside_init; if ((TYPE_MAIN_VARIANT (TREE_TYPE (TREE_TYPE (string))) *************** *** 4511,4529 **** For an array, this is allowed only for a string constant. */ ! if (init && (TREE_TYPE (init) == type ! || (code == ARRAY_TYPE && TREE_TYPE (init) ! && comptypes (TREE_TYPE (init), type)) || (code == POINTER_TYPE ! && TREE_TYPE (init) != 0 ! && (TREE_CODE (TREE_TYPE (init)) == ARRAY_TYPE ! || TREE_CODE (TREE_TYPE (init)) == FUNCTION_TYPE) ! && comptypes (TREE_TYPE (TREE_TYPE (init)), TREE_TYPE (type))))) { if (code == POINTER_TYPE ! && (TREE_CODE (TREE_TYPE (init)) == ARRAY_TYPE ! || TREE_CODE (TREE_TYPE (init)) == FUNCTION_TYPE)) ! init = default_conversion (init); ! else if (code == ARRAY_TYPE && TREE_CODE (init) != STRING_CST) { error_init ("array%s initialized from non-constant array expression", --- 4563,4581 ---- For an array, this is allowed only for a string constant. */ ! if (inside_init && (TREE_TYPE (inside_init) == type ! || (code == ARRAY_TYPE && TREE_TYPE (inside_init) ! && comptypes (TREE_TYPE (inside_init), type)) || (code == POINTER_TYPE ! && TREE_TYPE (inside_init) != 0 ! && (TREE_CODE (TREE_TYPE (inside_init)) == ARRAY_TYPE ! || TREE_CODE (TREE_TYPE (inside_init)) == FUNCTION_TYPE) ! && comptypes (TREE_TYPE (TREE_TYPE (inside_init)), TREE_TYPE (type))))) { if (code == POINTER_TYPE ! && (TREE_CODE (TREE_TYPE (inside_init)) == ARRAY_TYPE ! || TREE_CODE (TREE_TYPE (inside_init)) == FUNCTION_TYPE)) ! inside_init = default_conversion (inside_init); ! else if (code == ARRAY_TYPE && TREE_CODE (inside_init) != STRING_CST) { error_init ("array%s initialized from non-constant array expression", *************** *** 4532,4552 **** } ! if (optimize && TREE_READONLY (init) && TREE_CODE (init) == VAR_DECL) ! init = decl_constant_value (init); ! if (require_constant && ! TREE_CONSTANT (init)) { error_init ("initializer element%s is not constant", " for `%s'", ofwhat); ! init = error_mark_node; } ! else if (require_constant && initializer_constant_valid_p (init) == 0) { error_init ("initializer element%s is not computable at load time", " for `%s'", ofwhat); ! init = error_mark_node; } ! return init; } --- 4584,4605 ---- } ! if (optimize && TREE_READONLY (inside_init) ! && TREE_CODE (inside_init) == VAR_DECL) ! inside_init = decl_constant_value (inside_init); ! if (require_constant && ! TREE_CONSTANT (inside_init)) { error_init ("initializer element%s is not constant", " for `%s'", ofwhat); ! inside_init = error_mark_node; } ! else if (require_constant && initializer_constant_valid_p (inside_init) == 0) { error_init ("initializer element%s is not computable at load time", " for `%s'", ofwhat); ! inside_init = error_mark_node; } ! return inside_init; } *************** *** 4609,4613 **** if (raw_constructor) ! result = process_init_constructor (type, init, 0, require_constant, constructor_constant, 0); --- 4662,4666 ---- if (raw_constructor) ! result = process_init_constructor (type, inside_init, 0, require_constant, constructor_constant, 0); *************** *** 4641,4649 **** return error_mark_node; } ! init = element; } #if 0 /* A non-raw constructor is an actual expression. */ ! if (TREE_CODE (init) == CONSTRUCTOR) { error_init ("initializer for scalar%s has extra braces", --- 4694,4702 ---- return error_mark_node; } ! inside_init = element; } #if 0 /* A non-raw constructor is an actual expression. */ ! if (TREE_CODE (inside_init) == CONSTRUCTOR) { error_init ("initializer for scalar%s has extra braces", *************** *** 4657,4678 **** if (ofwhat) push_string (ofwhat); ! init = convert_for_assignment (type, default_conversion (init), ! &initialization_message, NULL_TREE, 0); }); ! if (require_constant && ! TREE_CONSTANT (init)) { error_init ("initializer element%s is not constant", " for `%s'", ofwhat); ! init = error_mark_node; } ! else if (require_constant && initializer_constant_valid_p (init) == 0) { error_init ("initializer element%s is not computable at load time", " for `%s'", ofwhat); ! init = error_mark_node; } ! return init; } --- 4710,4735 ---- if (ofwhat) push_string (ofwhat); ! inside_init ! = convert_for_assignment (type, ! default_conversion (raw_constructor ! ? inside_init ! : init), ! &initialization_message, NULL_TREE, 0); }); ! if (require_constant && ! TREE_CONSTANT (inside_init)) { error_init ("initializer element%s is not constant", " for `%s'", ofwhat); ! inside_init = error_mark_node; } ! else if (require_constant && initializer_constant_valid_p (inside_init) == 0) { error_init ("initializer element%s is not computable at load time", " for `%s'", ofwhat); ! inside_init = error_mark_node; } ! return inside_init; } *************** *** 4689,4693 **** { if (raw_constructor) ! return process_init_constructor (type, init, 0, constructor_constant, constructor_constant, ofwhat); else if (tail != 0) --- 4746,4751 ---- { if (raw_constructor) ! return process_init_constructor (type, inside_init, ! 0, constructor_constant, constructor_constant, ofwhat); else if (tail != 0) *************** *** 4701,4705 **** return process_init_constructor (type, build_nt (CONSTRUCTOR, 0, ! tree_cons (0, init, 0)), 0, constructor_constant, constructor_constant, ofwhat); --- 4759,4763 ---- return process_init_constructor (type, build_nt (CONSTRUCTOR, 0, ! tree_cons (0, inside_init, 0)), 0, constructor_constant, constructor_constant, ofwhat); diff -rc2N gcc-2.1/caller-save.c gcc-2.2.1/caller-save.c *** gcc-2.1/caller-save.c Fri Feb 21 01:30:52 1992 --- gcc-2.2.1/caller-save.c Sat Apr 11 20:29:24 1992 *************** *** 473,477 **** else if (regno >= FIRST_PSEUDO_REGISTER && reg_equiv_address[regno] != 0) ! restore_referenced_regs (XEXP (reg_equiv_address[regno], 0), insn, insn_mode); --- 473,477 ---- else if (regno >= FIRST_PSEUDO_REGISTER && reg_equiv_address[regno] != 0) ! restore_referenced_regs (reg_equiv_address[regno], insn, insn_mode); *************** *** 522,525 **** --- 522,535 ---- enum insn_code code; int i; + + /* A common failure mode if register status is not correct in the RTL + is for this routine to be called with a REGNO we didn't expect to + save. That will cause us to write an insn with a (nil) SET_DEST + or SET_SRC. Instead of doing so and causing a crash later, check + for this common case and abort here instead. This will remove one + step in debugging such problems. */ + + if (regno_save_mem[regno] == 0) + abort (); /* If INSN is a CALL_INSN, we must insert our insns before any diff -rc2N gcc-2.1/calls.c gcc-2.2.1/calls.c *** gcc-2.1/calls.c Fri Mar 13 23:58:35 1992 --- gcc-2.2.1/calls.c Mon Jun 1 21:41:11 1992 *************** *** 54,58 **** Also 0 if not passed in registers. */ int partial; ! /* Non-zero if argument must be passed on stack. */ int pass_on_stack; /* Offset of this argument from beginning of stack-args. */ --- 54,61 ---- Also 0 if not passed in registers. */ int partial; ! /* Non-zero if argument must be passed on stack. ! Note that some arguments may be passed on the stack ! even though pass_on_stack is zero, just because FUNCTION_ARG says so. ! pass_on_stack identifies arguments that *cannot* go in registers. */ int pass_on_stack; /* Offset of this argument from beginning of stack-args. */ *************** *** 88,91 **** --- 91,101 ---- /* Size of STACK_USAGE_MAP. */ static int highest_outgoing_arg_in_use; + + /* stack_arg_under_construction is nonzero when an argument may be + initialized with a constructor call (including a C function that + returns a BLKmode struct) and expand_call must take special action + to make sure the object being constructed does not overlap the + argument list for the constructor call. */ + int stack_arg_under_construction; #endif *************** *** 324,329 **** CONST_CALL_P (call_insn) = 1; - inhibit_defer_pop = old_inhibit_defer_pop; - #ifndef ACCUMULATE_OUTGOING_ARGS /* If returning from the subroutine does not automatically pop the args, --- 334,337 ---- *************** *** 350,353 **** --- 358,363 ---- } #endif + + inhibit_defer_pop = old_inhibit_defer_pop; } *************** *** 359,367 **** rtx ! expand_call (exp, target, ignore, modifier) tree exp; rtx target; int ignore; - enum expand_modifier modifier; { /* List of actual parameters. */ --- 369,376 ---- rtx ! expand_call (exp, target, ignore) tree exp; rtx target; int ignore; { /* List of actual parameters. */ *************** *** 434,437 **** --- 443,449 ---- #endif + /* Size of the stack reserved for paramter registers. */ + int reg_parm_stack_space = 0; + /* 1 if scanning parms front to back, -1 if scanning back to front. */ int inc; *************** *** 448,453 **** /* Nonzero if this is a call to an inline function. */ int is_integrable = 0; - /* Nonzero if this is a call to __builtin_new. */ - int is_builtin_new; /* Nonzero if this is a call to a `const' function. Note that only explicitly named functions are handled as `const' here. */ --- 460,463 ---- *************** *** 469,472 **** --- 479,483 ---- rtx old_stack_level = 0; int old_pending_adj; + int old_stack_arg_under_construction; int old_inhibit_defer_pop = inhibit_defer_pop; tree old_cleanups = cleanups_this_call; *************** *** 517,520 **** --- 528,539 ---- is_volatile = TYPE_VOLATILE (TREE_TYPE (TREE_TYPE (p))); + #ifdef REG_PARM_STACK_SPACE + #ifdef MAYBE_REG_PARM_STACK_SPACE + reg_parm_stack_space = MAYBE_REG_PARM_STACK_SPACE; + #else + reg_parm_stack_space = REG_PARM_STACK_SPACE (fndecl); + #endif + #endif + /* Warn if this value is an aggregate type, regardless of which calling convention we are using for it. */ *************** *** 569,572 **** --- 588,592 ---- { rtx temp; + rtx before_call = get_last_insn (); temp = expand_inline_function (fndecl, actparms, target, *************** *** 577,580 **** --- 597,602 ---- if ((int) temp != -1) { + int i; + /* Perform all cleanups needed for the arguments of this call (i.e. destructors in C++). It is ok if these destructors *************** *** 584,587 **** --- 606,667 ---- expand_cleanups_to (old_cleanups); + #ifdef ACCUMULATE_OUTGOING_ARGS + /* If the outgoing argument list must be preserved, push + the stack before executing the inlined function if it + makes any calls. */ + + for (i = reg_parm_stack_space - 1; i >= 0; i--) + if (i < highest_outgoing_arg_in_use && stack_usage_map[i] != 0) + break; + + if (stack_arg_under_construction || i >= 0) + { + rtx insn = NEXT_INSN (before_call), seq; + + /* Look for a call in the inline function code. + If OUTGOING_ARGS_SIZE (DECL_SAVED_INSNS (fndecl)) is + nonzero then there is a call and it is not necessary + to scan the insns. */ + + if (OUTGOING_ARGS_SIZE (DECL_SAVED_INSNS (fndecl)) == 0) + for (; insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == CALL_INSN) + break; + + if (insn) + { + /* Reserve enough stack space so that the largest + argument list of any function call in the inline + function does not overlap the argument list being + evaluated. This is usually an overestimate because + allocate_dynamic_stack_space reserves space for an + outgoing argument list in addition to the requested + space, but there is no way to ask for stack space such + that an argument list of a certain length can be + safely constructed. */ + + int adjust = OUTGOING_ARGS_SIZE (DECL_SAVED_INSNS (fndecl)); + #ifdef REG_PARM_STACK_SPACE + /* Add the stack space reserved for register arguments + in the inline function. What is really needed is the + largest value of reg_parm_stack_space in the inline + function, but that is not available. Using the current + value of reg_parm_stack_space is wrong, but gives + correct results on all supported machines. */ + adjust += reg_parm_stack_space; + #endif + start_sequence (); + emit_stack_save (SAVE_BLOCK, &old_stack_level, 0); + allocate_dynamic_stack_space (gen_rtx (CONST_INT, VOIDmode, + adjust), + 0, BITS_PER_UNIT); + seq = get_insns (); + end_sequence (); + emit_insns_before (seq, NEXT_INSN (before_call)); + emit_stack_restore (SAVE_BLOCK, old_stack_level, 0); + } + } + #endif + /* If the result is equivalent to TARGET, return TARGET to simplify checks in store_expr. They can be equivalent but not equal in the *************** *** 666,674 **** } - is_builtin_new - = (name != 0 - && IDENTIFIER_LENGTH (DECL_NAME (fndecl)) == 13 - && (!strcmp (name, "__builtin_new"))); - if (may_be_alloca) current_function_calls_alloca = 1; --- 746,749 ---- *************** *** 699,706 **** if (structure_value_addr && struct_value_rtx == 0) { actparms = tree_cons (error_mark_node, make_tree (build_pointer_type (TREE_TYPE (funtype)), ! force_reg (Pmode, structure_value_addr)), actparms); structure_value_addr_parm = 1; --- 774,791 ---- if (structure_value_addr && struct_value_rtx == 0) { + #ifdef ACCUMULATE_OUTGOING_ARGS + /* If the stack will be adjusted, make sure the structure address + does not refer to virtual_outgoing_args_rtx. */ + rtx temp = (stack_arg_under_construction + ? copy_addr_to_reg (structure_value_addr) + : force_reg (Pmode, structure_value_addr)); + #else + rtx temp = force_reg (Pmode, structure_value_addr); + #endif + actparms = tree_cons (error_mark_node, make_tree (build_pointer_type (TREE_TYPE (funtype)), ! temp), actparms); structure_value_addr_parm = 1; *************** *** 798,802 **** if (old_stack_level == 0) { ! old_stack_level = copy_to_mode_reg (Pmode, stack_pointer_rtx); old_pending_adj = pending_stack_adjust; pending_stack_adjust = 0; --- 883,887 ---- if (old_stack_level == 0) { ! emit_stack_save (SAVE_BLOCK, &old_stack_level, 0); old_pending_adj = pending_stack_adjust; pending_stack_adjust = 0; *************** *** 804,808 **** copy = gen_rtx (MEM, BLKmode, ! allocate_dynamic_stack_space (size_rtx, 0)); } else --- 889,894 ---- copy = gen_rtx (MEM, BLKmode, ! allocate_dynamic_stack_space (size_rtx, 0, ! TYPE_ALIGN (type))); } else *************** *** 852,856 **** if (args[i].reg == 0 || args[i].partial != 0 #ifdef REG_PARM_STACK_SPACE ! || REG_PARM_STACK_SPACE (fndecl) > 0 #endif || args[i].pass_on_stack) --- 938,942 ---- if (args[i].reg == 0 || args[i].partial != 0 #ifdef REG_PARM_STACK_SPACE ! || reg_parm_stack_space > 0 #endif || args[i].pass_on_stack) *************** *** 904,907 **** --- 990,998 ---- } + #ifdef FINAL_REG_PARM_STACK_SPACE + reg_parm_stack_space = FINAL_REG_PARM_STACK_SPACE (args_size.constant, + args_size.var); + #endif + /* Compute the actual size of the argument block required. The variable and constant sizes must be combined, the size may have to be rounded, *************** *** 928,932 **** #ifdef REG_PARM_STACK_SPACE ! if (REG_PARM_STACK_SPACE (fndecl) > 0) { args_size.var --- 1019,1023 ---- #ifdef REG_PARM_STACK_SPACE ! if (reg_parm_stack_space > 0) { args_size.var *************** *** 939,943 **** args_size.var = size_binop (MINUS_EXPR, args_size.var, ! size_int (REG_PARM_STACK_SPACE (fndecl))); #endif } --- 1030,1034 ---- args_size.var = size_binop (MINUS_EXPR, args_size.var, ! size_int (reg_parm_stack_space)); #endif } *************** *** 953,959 **** #ifdef REG_PARM_STACK_SPACE args_size.constant = MAX (args_size.constant, ! REG_PARM_STACK_SPACE (fndecl)); #ifndef OUTGOING_REG_PARM_STACK_SPACE ! args_size.constant -= REG_PARM_STACK_SPACE (fndecl); #endif #endif --- 1044,1050 ---- #ifdef REG_PARM_STACK_SPACE args_size.constant = MAX (args_size.constant, ! reg_parm_stack_space); #ifndef OUTGOING_REG_PARM_STACK_SPACE ! args_size.constant -= reg_parm_stack_space; #endif #endif *************** *** 1000,1004 **** } ! if (copy_to_evaluate_size >= args_size.constant / 2) must_preallocate = 1; } --- 1091,1096 ---- } ! if (copy_to_evaluate_size * 2 >= args_size.constant ! && args_size.constant > 0) must_preallocate = 1; } *************** *** 1052,1058 **** if (old_stack_level == 0) { ! old_stack_level = copy_to_mode_reg (Pmode, stack_pointer_rtx); old_pending_adj = pending_stack_adjust; pending_stack_adjust = 0; } argblock = push_block (ARGS_SIZE_RTX (args_size), 0, 0); --- 1144,1157 ---- if (old_stack_level == 0) { ! emit_stack_save (SAVE_BLOCK, &old_stack_level, 0); old_pending_adj = pending_stack_adjust; pending_stack_adjust = 0; + #ifdef ACCUMULATE_OUTGOING_ARGS + /* stack_arg_under_construction says whether a stack arg is + being constructed at the old stack level. Pushing the stack + gets a clean outgoing argument block. */ + old_stack_arg_under_construction = stack_arg_under_construction; + stack_arg_under_construction = 0; + #endif } argblock = push_block (ARGS_SIZE_RTX (args_size), 0, 0); *************** *** 1090,1094 **** map must be allocated for its entire size, not just the part that is the responsibility of the caller. */ ! needed += REG_PARM_STACK_SPACE (fndecl); #endif --- 1189,1193 ---- map must be allocated for its entire size, not just the part that is the responsibility of the caller. */ ! needed += reg_parm_stack_space; #endif *************** *** 1109,1116 **** highest_outgoing_arg_in_use - initial_highest_arg_in_use); needed = 0; ! /* No need to copy this virtual register; the space we're ! using gets preallocated at the start of the function ! so the stack pointer won't change here. */ argblock = virtual_outgoing_args_rtx; #else /* not ACCUMULATE_OUTGOING_ARGS */ if (inhibit_defer_pop == 0) --- 1208,1218 ---- highest_outgoing_arg_in_use - initial_highest_arg_in_use); needed = 0; ! ! /* The address of the outgoing argument list must not be copied to a ! register here, because argblock would be left pointing to the ! wrong place after the call to allocate_dynamic_stack_space below. */ ! argblock = virtual_outgoing_args_rtx; + #else /* not ACCUMULATE_OUTGOING_ARGS */ if (inhibit_defer_pop == 0) *************** *** 1146,1149 **** --- 1248,1292 ---- } + + #ifdef ACCUMULATE_OUTGOING_ARGS + /* The save/restore code in store_one_arg handles all cases except one: + a constructor call (including a C function returning a BLKmode struct) + to initialize an argument. */ + if (stack_arg_under_construction) + { + #if defined(REG_PARM_STACK_SPACE) && ! defined(OUTGOING_REG_PARM_STACK_SPACE) + rtx push_size = gen_rtx (CONST_INT, VOIDmode, + reg_parm_stack_space + args_size.constant); + #else + rtx push_size = gen_rtx (CONST_INT, VOIDmode, args_size.constant); + #endif + if (old_stack_level == 0) + { + emit_stack_save (SAVE_BLOCK, &old_stack_level, 0); + old_pending_adj = pending_stack_adjust; + pending_stack_adjust = 0; + /* stack_arg_under_construction says whether a stack arg is + being constructed at the old stack level. Pushing the stack + gets a clean outgoing argument block. */ + old_stack_arg_under_construction = stack_arg_under_construction; + stack_arg_under_construction = 0; + /* Make a new map for the new argument list. */ + stack_usage_map = (char *)alloca (highest_outgoing_arg_in_use); + bzero (stack_usage_map, highest_outgoing_arg_in_use); + highest_outgoing_arg_in_use = 0; + } + allocate_dynamic_stack_space (push_size, 0, BITS_PER_UNIT); + } + /* If argument evaluation might modify the stack pointer, copy the + address of the argument list to a register. */ + for (i = 0; i < num_actuals; i++) + if (args[i].pass_on_stack) + { + argblock = copy_addr_to_reg (argblock); + break; + } + #endif + + /* If we preallocated stack space, compute the address of each argument. We need not ensure it is a valid memory address here; it will be *************** *** 1254,1258 **** Here we compute the boundary of the that needs to be saved, if any. */ ! for (i = 0; i < REG_PARM_STACK_SPACE (fndecl); i++) { if (i >= highest_outgoing_arg_in_use --- 1397,1401 ---- Here we compute the boundary of the that needs to be saved, if any. */ ! for (i = 0; i < reg_parm_stack_space; i++) { if (i >= highest_outgoing_arg_in_use *************** *** 1307,1311 **** if (args[i].reg == 0 || args[i].pass_on_stack) store_one_arg (&args[i], argblock, may_be_alloca, ! args_size.var != 0, fndecl); /* Now store any partially-in-registers parm. --- 1450,1454 ---- if (args[i].reg == 0 || args[i].pass_on_stack) store_one_arg (&args[i], argblock, may_be_alloca, ! args_size.var != 0, fndecl, reg_parm_stack_space); /* Now store any partially-in-registers parm. *************** *** 1315,1319 **** if (args[i].partial != 0 && ! args[i].pass_on_stack) store_one_arg (&args[i], argblock, may_be_alloca, ! args_size.var != 0, fndecl); #ifndef PUSH_ARGS_REVERSED --- 1458,1462 ---- if (args[i].partial != 0 && ! args[i].pass_on_stack) store_one_arg (&args[i], argblock, may_be_alloca, ! args_size.var != 0, fndecl, reg_parm_stack_space); #ifndef PUSH_ARGS_REVERSED *************** *** 1328,1331 **** --- 1471,1482 ---- #endif + /* If register arguments require space on the stack and stack space + was not preallocated, allocate stack space here for arguments + passed in registers. */ + #if ! defined(ALLOCATE_OUTGOING_ARGS) && defined(OUTGOING_REG_PARM_STACK_SPACE) + if (must_preallocate == 0 && reg_parm_stack_space > 0) + anti_adjust_stack (gen_rtx (CONST_INT, VOIDmode, reg_parm_stack_space)); + #endif + /* Pass the function the address in which to return a structure value. */ if (structure_value_addr && ! structure_value_addr_parm) *************** *** 1460,1471 **** emit_barrier (); - /* For calls to __builtin_new, note that it can never return 0. - This is because a new handler will be called, and 0 it not - among the numbers it is supposed to return. */ - #if 0 - if (is_builtin_new) - emit_note (name, NOTE_INSN_BUILTIN_NEW); - #endif - /* If value type not void, return an rtx for the value. */ --- 1611,1614 ---- *************** *** 1484,1490 **** { if (target == 0 || GET_CODE (target) != MEM) ! target = gen_rtx (MEM, TYPE_MODE (TREE_TYPE (exp)), ! memory_address (TYPE_MODE (TREE_TYPE (exp)), ! structure_value_addr)); } else if (pcc_struct_value) --- 1627,1639 ---- { if (target == 0 || GET_CODE (target) != MEM) ! { ! target = gen_rtx (MEM, TYPE_MODE (TREE_TYPE (exp)), ! memory_address (TYPE_MODE (TREE_TYPE (exp)), ! structure_value_addr)); ! MEM_IN_STRUCT_P (target) ! = (TREE_CODE (TREE_TYPE (exp)) == ARRAY_TYPE ! || TREE_CODE (TREE_TYPE (exp)) == RECORD_TYPE ! || TREE_CODE (TREE_TYPE (exp)) == UNION_TYPE); ! } } else if (pcc_struct_value) *************** *** 1491,1496 **** { if (target == 0) ! target = gen_rtx (MEM, TYPE_MODE (TREE_TYPE (exp)), ! copy_to_reg (valreg)); else if (TYPE_MODE (TREE_TYPE (exp)) != BLKmode) emit_move_insn (target, gen_rtx (MEM, TYPE_MODE (TREE_TYPE (exp)), --- 1640,1651 ---- { if (target == 0) ! { ! target = gen_rtx (MEM, TYPE_MODE (TREE_TYPE (exp)), ! copy_to_reg (valreg)); ! MEM_IN_STRUCT_P (target) ! = (TREE_CODE (TREE_TYPE (exp)) == ARRAY_TYPE ! || TREE_CODE (TREE_TYPE (exp)) == RECORD_TYPE ! || TREE_CODE (TREE_TYPE (exp)) == UNION_TYPE); ! } else if (TYPE_MODE (TREE_TYPE (exp)) != BLKmode) emit_move_insn (target, gen_rtx (MEM, TYPE_MODE (TREE_TYPE (exp)), *************** *** 1516,1527 **** expand_cleanups_to (old_cleanups); ! /* If size of args is variable, restore saved stack-pointer value. */ if (old_stack_level) { ! emit_move_insn (stack_pointer_rtx, old_stack_level); pending_stack_adjust = old_pending_adj; } - #ifdef ACCUMULATE_OUTGOING_ARGS else --- 1671,1687 ---- expand_cleanups_to (old_cleanups); ! /* If size of args is variable or this was a constructor call for a stack ! argument, restore saved stack-pointer value. */ if (old_stack_level) { ! emit_stack_restore (SAVE_BLOCK, old_stack_level, 0); pending_stack_adjust = old_pending_adj; + #ifdef ACCUMULATE_OUTGOING_ARGS + stack_arg_under_construction = old_stack_arg_under_construction; + highest_outgoing_arg_in_use = initial_highest_arg_in_use; + stack_usage_map = initial_stack_usage_map; + #endif } #ifdef ACCUMULATE_OUTGOING_ARGS else *************** *** 1570,1577 **** #endif ! /* If this was alloca, record the new stack level for nonlocal gotos. */ ! if (may_be_alloca && nonlocal_goto_stack_level != 0) ! emit_move_insn (nonlocal_goto_stack_level, stack_pointer_rtx); pop_temp_slots (); --- 1730,1740 ---- #endif ! /* If this was alloca, record the new stack level for nonlocal gotos. ! Check for the handler slots since we might not have a save area ! for non-local gotos. */ + if (may_be_alloca && nonlocal_goto_handler_slot != 0) + emit_stack_save (SAVE_NONLOCAL, &nonlocal_goto_stack_level, 0); + pop_temp_slots (); *************** *** 1634,1638 **** static void ! store_one_arg (arg, argblock, may_be_alloca, variable_size, fndecl) struct arg_data *arg; rtx argblock; --- 1797,1802 ---- static void ! store_one_arg (arg, argblock, may_be_alloca, variable_size, fndecl, ! reg_parm_stack_space) struct arg_data *arg; rtx argblock; *************** *** 1640,1643 **** --- 1804,1808 ---- int variable_size; tree fndecl; + int reg_parm_stack_space; { register tree pval = arg->tree_value; *************** *** 1678,1682 **** /* Don't store things in the fixed argument area at this point; it has already been saved. */ ! && i > REG_PARM_STACK_SPACE (fndecl) #endif ) --- 1843,1847 ---- /* Don't store things in the fixed argument area at this point; it has already been saved. */ ! && i > reg_parm_stack_space #endif ) *************** *** 1729,1733 **** it directly into its stack slot. Otherwise, we can. */ if (arg->value == 0) ! arg->value = expand_expr (pval, partial ? 0 : arg->stack, VOIDmode, 0); /* Don't allow anything left on stack from computation --- 1894,1926 ---- it directly into its stack slot. Otherwise, we can. */ if (arg->value == 0) ! { ! #ifdef ACCUMULATE_OUTGOING_ARGS ! /* stack_arg_under_construction is nonzero if a function argument is ! being evaluated directly into the outgoing argument list and ! expand_call must take special action to preserve the argument list ! if it is called recursively. ! ! For scalar function arguments stack_usage_map is sufficient to ! determine which stack slots must be saved and restored. Scalar ! arguments in general have pass_on_stack == 0. ! ! If this argument is initialized by a function which takes the ! address of the argument (a C++ constructor or a C function ! returning a BLKmode structure), then stack_usage_map is ! insufficient and expand_call must push the stack around the ! function call. Such arguments have pass_on_stack == 1. ! ! Note that it is always safe to set stack_arg_under_construction, ! but this generates suboptimal code if set when not needed. */ ! ! if (arg->pass_on_stack) ! stack_arg_under_construction++; ! #endif ! arg->value = expand_expr (pval, partial ? 0 : arg->stack, VOIDmode, 0); ! #ifdef ACCUMULATE_OUTGOING_ARGS ! if (arg->pass_on_stack) ! stack_arg_under_construction--; ! #endif ! } /* Don't allow anything left on stack from computation diff -rc2N gcc-2.1/cccp.1 gcc-2.2.1/cccp.1 *** gcc-2.1/cccp.1 Wed Jan 22 20:00:03 1992 --- gcc-2.2.1/cccp.1 Tue Mar 31 21:12:05 1992 *************** *** 1,9 **** ! .\" Copyright (c) 1991 Free Software Foundation \-*-Text-*- .\" See section COPYING for conditions for redistribution .TH cpp 1 "2Jan1992" "GNU Tools" "GNU Tools" - .SH NAME ! cccp, cpp: The GNU C-Compatible Compiler Preprocessor. ! .SH SYNOPSIS .hy 0 --- 1,7 ---- ! .\" Copyright (c) 1991, 1992 Free Software Foundation \-*-Text-*- .\" See section COPYING for conditions for redistribution .TH cpp 1 "2Jan1992" "GNU Tools" "GNU Tools" .SH NAME ! cccp, cpp \- The GNU C-Compatible Compiler Preprocessor. .SH SYNOPSIS .hy 0 *************** *** 164,168 **** \& or both file names are omitted, the standard output and standard input are used for the omitted file names. - .SH OPTIONS Here is a table of command options accepted by the C preprocessor. --- 162,165 ---- *************** *** 562,566 **** .B \-ansi\c \&\|', you must call the preprocessor directly. - .SH "SEE ALSO" .RB "`\|" Cpp "\|'" --- 559,562 ---- *************** *** 569,573 **** \&; .I The C Preprocessor\c ! , Richard M. Stallman, July 1990. .br .BR gcc "(" 1 ");" --- 565,569 ---- \&; .I The C Preprocessor\c ! , Richard M. Stallman. .br .BR gcc "(" 1 ");" *************** *** 578,585 **** .I Using and Porting GNU CC (for version 2.0)\c ! , Richard M. Stallman, November 1990. ! .SH COPYING ! Copyright (c) 1991 Free Software Foundation, Inc. .PP Permission is granted to make and distribute verbatim copies of --- 574,580 ---- .I Using and Porting GNU CC (for version 2.0)\c ! , Richard M. Stallman. .SH COPYING ! Copyright (c) 1991, 1992 Free Software Foundation, Inc. .PP Permission is granted to make and distribute verbatim copies of diff -rc2N gcc-2.1/cccp.c gcc-2.2.1/cccp.c *** gcc-2.1/cccp.c Sun Mar 22 22:45:33 1992 --- gcc-2.2.1/cccp.c Sat Jun 6 17:46:01 1992 *************** *** 54,57 **** --- 54,62 ---- #endif + /* By default, colon separates directories in a path. */ + #ifndef PATH_SEPARATOR + #define PATH_SEPARATOR ':' + #endif + /* In case config.h defines these. */ #undef bcopy *************** *** 66,70 **** #ifndef VMS - #include #ifndef USG #include /* for __DATE__ and __TIME__ */ --- 71,74 ---- *************** *** 330,336 **** static int debug_output = 0; - /* Holds local startup time. */ - static struct tm *timebuf = NULL; - /* Nonzero indicates special processing used by the pcp program. The special effects of this mode are: --- 334,337 ---- *************** *** 524,527 **** --- 525,532 ---- static struct file_name_list *all_include_files = 0; + /* Directory prefix that should replace `/usr' in the standard + include file directories. */ + static char *include_prefix; + /* Global list of strings read in from precompiled files. This list is kept in the order the strings are read in, with new strings being *************** *** 573,576 **** --- 578,582 ---- int line; /* Line number of definition */ char *file; /* File of definition */ + char rest_args; /* Nonzero if last arg. absorbs the rest */ struct reflist { struct reflist *next; *************** *** 579,582 **** --- 585,589 ---- char raw_before; /* Nonzero if a ## operator before arg. */ char raw_after; /* Nonzero if a ## operator after arg. */ + char rest_args; /* Nonzero if this arg. absorbs the rest */ int nchars; /* Number of literal chars to copy before this arg occurrence. */ *************** *** 601,604 **** --- 608,625 ---- }; + /* + * special extension string that can be added to the last macro argument to + * allow it to absorb the "rest" of the arguments when expanded. Ex: + * #define wow(a, b...) process(b, a, b) + * { wow(1, 2, 3); } -> { process( 2, 3, 1, 2, 3); } + * { wow(one, two); } -> { process( two, one, two); } + * if this "rest_arg" is used with the concat token '##' and if it is not + * supplied then the token attached to with ## will not be outputed. Ex: + * #define wow(a, b...) process(b ## , a, ## b) + * { wow(1, 2); } -> { process( 2, 1,2); } + * { wow(one); } -> { process( one); { + */ + static char rest_extension[] = "..."; + #define REST_EXTENSION_LENGTH (sizeof (rest_extension) - 1) /* The structure of a node in the hash table. The hash table *************** *** 887,890 **** --- 908,912 ---- int inhibit_predefs = 0; int no_standard_includes = 0; + int no_standard_cplusplus_includes = 0; int missing_newline = 0; *************** *** 985,988 **** --- 1007,1016 ---- pend_files[i] = argv[i+1], i++; } + if (!strcmp (argv[i], "-iprefix")) { + if (i + 1 == argc) + fatal ("Filename missing after -iprefix option"); + else + include_prefix = argv[++i]; + } /* Add directory to end of path for includes. */ if (!strcmp (argv[i], "-idirafter")) { *************** *** 1267,1270 **** --- 1295,1301 ---- You must specify all include-file directories with -I. */ no_standard_includes = 1; + else if (!strcmp (argv[i], "-nostdinc++")) + /* -nostdinc++ causes no default C++-specific include directories. */ + no_standard_cplusplus_includes = 1; else if (!strcmp (argv[i], "-noprecomp")) no_precomp = 1; *************** *** 1447,1451 **** for (num_dirs = 1, startp = epath; *startp; startp++) ! if (*startp == ':') num_dirs++; include_defaults --- 1478,1482 ---- for (num_dirs = 1, startp = epath; *startp; startp++) ! if (*startp == PATH_SEPARATOR) num_dirs++; include_defaults *************** *** 1457,1466 **** while (1) { /* Handle cases like c:/usr/lib:d:/gcc/lib */ ! if ((*endp == ':' #ifdef __MSDOS__ && (endp-startp != 1 || !isalpha (*startp))) #endif ) ! || (*endp == 0)) { strncpy (nstore, startp, endp-startp); if (endp == startp) --- 1488,1499 ---- while (1) { /* Handle cases like c:/usr/lib:d:/gcc/lib */ ! if ((*endp == PATH_SEPARATOR ! #if 0 /* Obsolete, now that we use semicolons as the path separator. */ #ifdef __MSDOS__ && (endp-startp != 1 || !isalpha (*startp))) #endif + #endif ) ! || *endp == 0) { strncpy (nstore, startp, endp-startp); if (endp == startp) *************** *** 1489,1493 **** if (!no_standard_includes) { struct default_include *p = include_defaults; ! char *specd_prefix = getenv ("GCC_EXEC_PREFIX"); char *default_prefix = savestring (GCC_INCLUDE_DIR); int default_len = 0; --- 1522,1526 ---- if (!no_standard_includes) { struct default_include *p = include_defaults; ! char *specd_prefix = include_prefix; char *default_prefix = savestring (GCC_INCLUDE_DIR); int default_len = 0; *************** *** 1502,1506 **** for (p = include_defaults; p->fname; p++) { /* Some standard dirs are only for C++. */ ! if (!p->cplusplus || cplusplus) { /* Does this dir start with the prefix? */ if (!strncmp (p->fname, default_prefix, default_len)) { --- 1535,1539 ---- for (p = include_defaults; p->fname; p++) { /* Some standard dirs are only for C++. */ ! if (!p->cplusplus || (cplusplus && !no_standard_cplusplus_includes)) { /* Does this dir start with the prefix? */ if (!strncmp (p->fname, default_prefix, default_len)) { *************** *** 1534,1538 **** for (p = include_defaults; p->fname; p++) { /* Some standard dirs are only for C++. */ ! if (!p->cplusplus || cplusplus) { struct file_name_list *new = (struct file_name_list *) xmalloc (sizeof (struct file_name_list)); --- 1567,1571 ---- for (p = include_defaults; p->fname; p++) { /* Some standard dirs are only for C++. */ ! if (!p->cplusplus || (cplusplus && !no_standard_cplusplus_includes)) { struct file_name_list *new = (struct file_name_list *) xmalloc (sizeof (struct file_name_list)); *************** *** 1829,1838 **** /* Find the end of this name. */ ! #ifdef __MSDOS__ ! /* Handle cases like c:/usr/lib:d:/gcc/lib */ ! while (*q != 0 && (*q != ':' || (q - p == 1 && isalpha (*p)))) q++; ! #else ! while (*q != 0 && *q != ':') q++; ! #endif if (p == q) { /* An empty name in the path stands for the current directory. */ --- 1862,1866 ---- /* Find the end of this name. */ ! while (*q != 0 && *q != PATH_SEPARATOR) q++; if (p == q) { /* An empty name in the path stands for the current directory. */ *************** *** 3316,3319 **** --- 3344,3349 ---- SKIP_WHITE_SPACE (xp); } + } else { + *cp++ = *xp++; } break; *************** *** 3323,3327 **** { register U_CHAR *bp1 ! = skip_quoted_string (xp - 1, limit, ip->lineno, 0, 0, 0); while (xp != bp1) if (*xp == '\\') { --- 3353,3357 ---- { register U_CHAR *bp1 ! = skip_quoted_string (xp - 1, bp, ip->lineno, 0, 0, 0); while (xp != bp1) if (*xp == '\\') { *************** *** 3406,3409 **** --- 3436,3450 ---- } + static struct tm * + timestamp () + { + static struct tm *timebuf; + if (!timebuf) { + time_t t = time (0); + timebuf = localtime (&t); + } + return timebuf; + } + static char *monthnames[] = {"Jan", "Feb", "Mar", "Apr", "May", "Jun", "Jul", "Aug", "Sep", "Oct", "Nov", "Dec", *************** *** 3424,3427 **** --- 3465,3469 ---- int true_indepth; FILE_BUF *ip = NULL; + struct tm *timebuf; int paren = 0; /* For special `defined' keyword */ *************** *** 3509,3512 **** --- 3551,3555 ---- case T_TIME: buf = (char *) alloca (20); + timebuf = timestamp (); if (hp->type == T_DATE) sprintf (buf, "\"%s %2d %4d\"", monthnames[timebuf->tm_mon], *************** *** 3967,3971 **** if (S_ISREG (st_mode)) { ! fp->buf = (U_CHAR *) alloca (st_size + 2); fp->bufp = fp->buf; --- 4010,4014 ---- if (S_ISREG (st_mode)) { ! fp->buf = (U_CHAR *) xmalloc (st_size + 2); fp->bufp = fp->buf; *************** *** 4042,4045 **** --- 4085,4089 ---- input_file_stack_tick++; output_line_command (&instack[indepth], op, 0, leave_file); + free (fp->buf); return; *************** *** 4048,4051 **** --- 4092,4096 ---- perror_with_name (fname); close (f); + free (fp->buf); } *************** *** 4492,4496 **** --- 4537,4546 ---- bcopy (buf, op->bufp, limit - buf); op->bufp += (limit - buf); + #if 0 *op->bufp++ = '\n'; + /* Count the line we have just made in the output, + to get in sync properly. */ + op->lineno++; + #endif } *************** *** 4511,4514 **** --- 4561,4565 ---- int length; int argno; + char rest_args; }; *************** *** 4525,4528 **** --- 4576,4580 ---- int line = instack[indepth].lineno; char *file = instack[indepth].nominal_fname; + int rest_args = 0; DEFINITION *defn; *************** *** 4559,4572 **** temp->next = arg_ptrs; temp->argno = argno++; arg_ptrs = temp; ! if (!is_idstart[*bp]) ! pedwarn ("parameter name starts with a digit in `#define'"); /* Find the end of the arg name. */ while (is_idchar[*bp]) { bp++; } temp->length = bp - temp->name; arglengths += temp->length + 2; SKIP_WHITE_SPACE (bp); --- 4611,4638 ---- temp->next = arg_ptrs; temp->argno = argno++; + temp->rest_args = 0; arg_ptrs = temp; ! if (rest_args) ! pedwarn ("another parameter follows `%s'", ! rest_extension); + if (!is_idstart[*bp]) + pedwarn ("invalid character in macro parameter name"); + /* Find the end of the arg name. */ while (is_idchar[*bp]) { bp++; + /* do we have a "special" rest-args extension here? */ + if (limit - bp > REST_EXTENSION_LENGTH && + strncmp (rest_extension, bp, REST_EXTENSION_LENGTH) == 0) { + rest_args = 1; + temp->rest_args = 1; + break; + } } temp->length = bp - temp->name; + if (rest_args == 1) + bp += REST_EXTENSION_LENGTH; arglengths += temp->length + 2; SKIP_WHITE_SPACE (bp); *************** *** 4605,4608 **** --- 4671,4675 ---- /* now everything from bp before limit is the definition. */ defn = collect_expansion (bp, limit, argno, arg_ptrs); + defn->rest_args = rest_args; /* Now set defn->args.argnames to the result of concatenating *************** *** 5047,5050 **** --- 5114,5118 ---- tpat->raw_before = concat == id_beg; tpat->raw_after = 0; + tpat->rest_args = arg->rest_args; tpat->stringify = (traditional ? expected_delimiter != '\0' : stringify == id_beg); *************** *** 5720,5724 **** copy[length] = 0; SKIP_WHITE_SPACE (copy); ! error ("#warning %s", copy); return 0; } --- 5788,5792 ---- copy[length] = 0; SKIP_WHITE_SPACE (copy); ! warning ("#warning %s", copy); return 0; } *************** *** 5773,5777 **** buf++; if (!strncmp (buf, "once", 4)) { ! warning ("`#pragma once' is obsolete"); do_once (); } --- 5841,5848 ---- buf++; if (!strncmp (buf, "once", 4)) { ! /* Allow #pragma once in system headers, since that's not the user's ! fault. */ ! if (!instack[indepth].system_header_p) ! warning ("`#pragma once' is obsolete"); do_once (); } *************** *** 6721,6724 **** --- 6792,6796 ---- int xbuf_len; int start_line = instack[indepth].lineno; + int rest_args, rest_zero; CHECK_DEPTH (return;); *************** *** 6754,6764 **** /* Parse all the macro args that are supplied. I counts them. The first NARGS args are stored in ARGS. ! The rest are discarded. */ i = 0; do { /* Discard the open-parenthesis or comma before the next arg. */ ++instack[indepth].bufp; ! parse_error ! = macarg ((i < nargs || (nargs == 0 && i == 0)) ? &args[i] : 0); if (parse_error) { error_with_line (line_for_error (start_line), parse_error); --- 6826,6847 ---- /* Parse all the macro args that are supplied. I counts them. The first NARGS args are stored in ARGS. ! The rest are discarded. ! If rest_args is set then we assume macarg absorbed the rest of the args. ! */ i = 0; + rest_args = 0; do { /* Discard the open-parenthesis or comma before the next arg. */ ++instack[indepth].bufp; ! if (rest_args) ! continue; ! if (i < nargs || (nargs == 0 && i == 0)) { ! /* if we are working on last arg which absorbes rest of args... */ ! if (i == nargs - 1 && defn->rest_args) ! rest_args = 1; ! parse_error = macarg (&args[i], rest_args); ! } ! else ! parse_error = macarg (0, 0); if (parse_error) { error_with_line (line_for_error (start_line), parse_error); *************** *** 6777,6780 **** --- 6860,6864 ---- } + rest_zero = 0; if (nargs == 0 && i > 0) error ("arguments given to macro `%s'", hp->name); *************** *** 6783,6786 **** --- 6867,6873 ---- if (nargs == 1 && i == 0 && traditional) ; + /* the rest args token is allowed to absorb 0 tokens */ + else if (i == nargs - 1 && defn->rest_args) + rest_zero = 1; else if (i == 0) error ("macro `%s' used without args", hp->name); *************** *** 6806,6810 **** register int totlen; /* total amount of exp buffer filled so far */ ! register struct reflist *ap; /* Macro really takes args. Compute the expansion of this call. */ --- 6893,6897 ---- register int totlen; /* total amount of exp buffer filled so far */ ! register struct reflist *ap, *last_ap; /* Macro really takes args. Compute the expansion of this call. */ *************** *** 6833,6841 **** of where we are copying from. */ offset = totlen = 0; ! for (ap = defn->pattern; ap != NULL; ap = ap->next) { register struct argdata *arg = &args[ap->argno]; ! for (i = 0; i < ap->nchars; i++) ! xbuf[totlen++] = exp[offset++]; if (ap->stringify != 0) { --- 6920,6933 ---- of where we are copying from. */ offset = totlen = 0; ! for (last_ap = NULL, ap = defn->pattern; ap != NULL; ! last_ap = ap, ap = ap->next) { register struct argdata *arg = &args[ap->argno]; ! /* add chars to XBUF unless rest_args was zero with concatenation */ ! for (i = 0; i < ap->nchars; i++, offset++) ! if (! (rest_zero && ((ap->rest_args && ap->raw_before) ! || (last_ap != NULL && last_ap->rest_args ! && last_ap->raw_after)))) ! xbuf[totlen++] = exp[offset]; if (ap->stringify != 0) { *************** *** 6961,6966 **** after handling the arg list, copy that in too. */ ! for (i = offset; i < defn->length; i++) ! xbuf[totlen++] = exp[i]; xbuf[totlen] = 0; --- 7053,7064 ---- after handling the arg list, copy that in too. */ ! for (i = offset; i < defn->length; i++) { ! /* if we've reached the end of the macro */ ! if (exp[i] == ')') ! rest_zero = 0; ! if (! (rest_zero && last_ap != NULL && last_ap->rest_args ! && last_ap->raw_after)) ! xbuf[totlen++] = exp[i]; ! } xbuf[totlen] = 0; *************** *** 7008,7011 **** --- 7106,7110 ---- /* * Parse a macro argument and store the info on it into *ARGPTR. + * REST_ARGS is passed to macarg1 to make it absorb the rest of the args. * Return nonzero to indicate a syntax error. */ *************** *** 7012,7017 **** static char * ! macarg (argptr) register struct argdata *argptr; { FILE_BUF *ip = &instack[indepth]; --- 7111,7117 ---- static char * ! macarg (argptr, rest_args) register struct argdata *argptr; + int rest_args; { FILE_BUF *ip = &instack[indepth]; *************** *** 7023,7027 **** input stack level. */ U_CHAR *bp = macarg1 (ip->bufp, ip->buf + ip->length, ! &paren, &newlines, &comments); /* If we find the end of the argument at this level, --- 7123,7127 ---- input stack level. */ U_CHAR *bp = macarg1 (ip->bufp, ip->buf + ip->length, ! &paren, &newlines, &comments, rest_args); /* If we find the end of the argument at this level, *************** *** 7061,7065 **** comments = 0; bp = macarg1 (ip->bufp, ip->buf + ip->length, &paren, ! &newlines, &comments); final_start = bufsize; bufsize += bp - ip->bufp; --- 7161,7165 ---- comments = 0; bp = macarg1 (ip->bufp, ip->buf + ip->length, &paren, ! &newlines, &comments, rest_args); final_start = bufsize; bufsize += bp - ip->bufp; *************** *** 7150,7160 **** Increment *NEWLINES each time a newline is passed. Set *COMMENTS to 1 if a comment is seen. */ static U_CHAR * ! macarg1 (start, limit, depthptr, newlines, comments) U_CHAR *start; register U_CHAR *limit; int *depthptr, *newlines, *comments; { register U_CHAR *bp = start; --- 7250,7262 ---- Increment *NEWLINES each time a newline is passed. + REST_ARGS notifies macarg1 that it should absorb the rest of the args. Set *COMMENTS to 1 if a comment is seen. */ static U_CHAR * ! macarg1 (start, limit, depthptr, newlines, comments, rest_args) U_CHAR *start; register U_CHAR *limit; int *depthptr, *newlines, *comments; + int rest_args; { register U_CHAR *bp = start; *************** *** 7227,7231 **** break; case ',': ! if ((*depthptr) == 0) return bp; break; --- 7329,7334 ---- break; case ',': ! /* if we've returned to lowest level and we aren't absorbing all args */ ! if ((*depthptr) == 0 && rest_args == 0) return bp; break; *************** *** 7973,7981 **** FILE_BUF *outp; { - time_t t; - - t = time (0); - timebuf = localtime (&t); - install ("__LINE__", -1, T_SPECLINE, 0, -1); install ("__DATE__", -1, T_DATE, 0, -1); --- 8076,8079 ---- *************** *** 8000,8005 **** char directive[2048]; register struct directive *dp = &directive_table[0]; ! sprintf (directive, " __BASE_FILE__ \"%s\"", instack[0].nominal_fname); output_line_command (inp, outp, 0, same_file); --- 8098,8104 ---- char directive[2048]; register struct directive *dp = &directive_table[0]; + struct tm *timebuf = timestamp (); ! sprintf (directive, " __BASE_FILE__ \"%s\"\n", instack[0].nominal_fname); output_line_command (inp, outp, 0, same_file); *************** *** 8006,8030 **** pass_thru_directive (directive, &directive[strlen (directive)], outp, dp); ! sprintf (directive, " __VERSION__ \"%s\"", version_string); output_line_command (inp, outp, 0, same_file); pass_thru_directive (directive, &directive[strlen (directive)], outp, dp); ! sprintf (directive, " __SIZE_TYPE__ %s", SIZE_TYPE); output_line_command (inp, outp, 0, same_file); pass_thru_directive (directive, &directive[strlen (directive)], outp, dp); ! sprintf (directive, " __PTRDIFF_TYPE__ %s", PTRDIFF_TYPE); output_line_command (inp, outp, 0, same_file); pass_thru_directive (directive, &directive[strlen (directive)], outp, dp); ! sprintf (directive, " __WCHAR_TYPE__ %s", WCHAR_TYPE); output_line_command (inp, outp, 0, same_file); pass_thru_directive (directive, &directive[strlen (directive)], outp, dp); ! sprintf (directive, " __WCHAR_TYPE__ %s", WCHAR_TYPE); output_line_command (inp, outp, 0, same_file); pass_thru_directive (directive, &directive[strlen (directive)], outp, dp); ! sprintf (directive, " __DATE__ \"%s %2d %4d\"", monthnames[timebuf->tm_mon], timebuf->tm_mday, timebuf->tm_year + 1900); --- 8105,8129 ---- pass_thru_directive (directive, &directive[strlen (directive)], outp, dp); ! sprintf (directive, " __VERSION__ \"%s\"\n", version_string); output_line_command (inp, outp, 0, same_file); pass_thru_directive (directive, &directive[strlen (directive)], outp, dp); ! sprintf (directive, " __SIZE_TYPE__ %s\n", SIZE_TYPE); output_line_command (inp, outp, 0, same_file); pass_thru_directive (directive, &directive[strlen (directive)], outp, dp); ! sprintf (directive, " __PTRDIFF_TYPE__ %s\n", PTRDIFF_TYPE); output_line_command (inp, outp, 0, same_file); pass_thru_directive (directive, &directive[strlen (directive)], outp, dp); ! sprintf (directive, " __WCHAR_TYPE__ %s\n", WCHAR_TYPE); output_line_command (inp, outp, 0, same_file); pass_thru_directive (directive, &directive[strlen (directive)], outp, dp); ! sprintf (directive, " __WCHAR_TYPE__ %s\n", WCHAR_TYPE); output_line_command (inp, outp, 0, same_file); pass_thru_directive (directive, &directive[strlen (directive)], outp, dp); ! sprintf (directive, " __DATE__ \"%s %2d %4d\"\n", monthnames[timebuf->tm_mon], timebuf->tm_mday, timebuf->tm_year + 1900); *************** *** 8032,8036 **** pass_thru_directive (directive, &directive[strlen (directive)], outp, dp); ! sprintf (directive, " __TIME__ \"%02d:%02d:%02d\"", timebuf->tm_hour, timebuf->tm_min, timebuf->tm_sec); output_line_command (inp, outp, 0, same_file); --- 8131,8135 ---- pass_thru_directive (directive, &directive[strlen (directive)], outp, dp); ! sprintf (directive, " __TIME__ \"%02d:%02d:%02d\"\n", timebuf->tm_hour, timebuf->tm_min, timebuf->tm_sec); output_line_command (inp, outp, 0, same_file); diff -rc2N gcc-2.1/collect2.c gcc-2.2.1/collect2.c *** gcc-2.1/collect2.c Thu Mar 19 17:07:22 1992 --- gcc-2.2.1/collect2.c Fri Jun 5 19:03:21 1992 *************** *** 35,39 **** --- 35,41 ---- #include #include + #ifdef NO_WAIT_H #include + #endif #ifndef errno *************** *** 46,50 **** #ifndef __STDC__ - #include "gvarargs.h" #define generic char #define const --- 48,51 ---- *************** *** 51,55 **** #else - #include "gstdarg.h" #define generic void #endif --- 52,55 ---- *************** *** 171,174 **** --- 171,175 ---- static int vflag; /* true if -v */ static int rflag; /* true if -r */ + static int strip_flag; /* true if -s */ static int debug; /* true if -debug */ *************** *** 179,182 **** --- 180,184 ---- static char *o_file; /* .o for constructor/destructor list. */ static char *nm_file_name; /* pathname of nm */ + static char *strip_file_name; /* pathname of strip */ static struct head constructors; /* list of constructors found */ *************** *** 185,189 **** extern char *getenv (); extern char *mktemp (); - extern int vfork (); static void add_to_list (); static void scan_prog_file (); --- 187,190 ---- *************** *** 199,207 **** generic *xmalloc (); - - #if !defined(HAVE_STRERROR) && !defined(_OSF_SOURCE) - char * ! strerror (e) int e; { --- 200,205 ---- generic *xmalloc (); char * ! my_strerror (e) int e; { *************** *** 219,225 **** return buffer; } - - #endif - /* Delete tempfiles and exit function. */ --- 217,220 ---- *************** *** 239,311 **** - #ifndef __STDC__ - /* Die when sys call fails. */ - /*VARARGS*/ - static void - fatal_perror (va_alist) - { - char *string; - va_list vptr; - int e = errno; - - va_start (vptr); - string = va_arg (vptr, char *); - fprintf (stderr, "collect: "); - vfprintf (stderr, string, vptr); - fprintf (stderr, ": %s\n", strerror (e)); - va_end (vptr); - my_exit (1); - } - - /* Just die. */ - - /*VARARGS*/ - static void - fatal (va_alist) - { - char *string; - va_list vptr; - - va_start (vptr); - string = va_arg (vptr, char *); - fprintf (stderr, "collect: "); - vfprintf (stderr, string, vptr); - fprintf (stderr, "\n"); - va_end (vptr); - my_exit (1); - } - - /* Write error message. */ - - /*VARARGS*/ - static void - error (va_alist) - { - char *string; - va_list vptr; - - va_start (vptr); - string = va_arg (vptr, char *); - fprintf (stderr, "collect: "); - vfprintf (stderr, string, vptr); - fprintf (stderr, "\n"); - va_end (vptr); - } - - #else - static void ! fatal_perror (char *string, ...) { - va_list vptr; int e = errno; - va_start (vptr, string); fprintf (stderr, "collect: "); ! vfprintf (stderr, string, vptr); ! fprintf (stderr, ": %s\n", strerror (e)); ! va_end (vptr); my_exit (1); } --- 234,248 ---- /* Die when sys call fails. */ static void ! fatal_perror (string, arg1, arg2, arg3) ! char *string; { int e = errno; fprintf (stderr, "collect: "); ! fprintf (stderr, string, arg1, arg2, arg3); ! fprintf (stderr, ": %s\n", my_strerror (e)); my_exit (1); } *************** *** 314,326 **** static void ! fatal (char *string, ...) { - va_list vptr; - - va_start (vptr, string); fprintf (stderr, "collect: "); ! vfprintf (stderr, string, vptr); fprintf (stderr, "\n"); - va_end (vptr); my_exit (1); } --- 251,260 ---- static void ! fatal (string, arg1, arg2, arg3) ! char *string; { fprintf (stderr, "collect: "); ! fprintf (stderr, string, arg1, arg2, arg3); fprintf (stderr, "\n"); my_exit (1); } *************** *** 329,345 **** static void ! error (char *string, ...) { - va_list vptr; - - va_start (vptr, string); fprintf (stderr, "collect: "); ! vfprintf (stderr, string, vptr); fprintf (stderr, "\n"); - va_end (vptr); } - #endif - /* In case obstack is linked in, and abort is defined to fancy_abort, provide a default entry. */ --- 263,274 ---- static void ! error (string, arg1, arg2, arg3, arg4) ! char *string; { fprintf (stderr, "collect: "); ! fprintf (stderr, string, arg1, arg2, arg3, arg4); fprintf (stderr, "\n"); } /* In case obstack is linked in, and abort is defined to fancy_abort, provide a default entry. */ *************** *** 375,379 **** return ptr; ! fatal ("Out of memory."); return (generic *)0; } --- 304,308 ---- return ptr; ! fatal ("out of memory"); return (generic *)0; } *************** *** 387,391 **** return ptr; ! fatal ("Out of memory."); return (generic *)0; } --- 316,320 ---- return ptr; ! fatal ("out of memory"); return (generic *)0; } *************** *** 399,403 **** { char *output = (char *) xmalloc (size + 1); ! strcpy (output, input); return output; } --- 328,333 ---- { char *output = (char *) xmalloc (size + 1); ! bcopy (input, output, size); ! output[size] = 0; return output; } *************** *** 520,524 **** char *q = p; while (*q && *q != ' ') q++; ! if (*p == '-' && (p[1] == 'm' || p[1] == 'f')) num_c_args++; --- 450,454 ---- char *q = p; while (*q && *q != ' ') q++; ! if (*p == '-' && p[1] == 'm') num_c_args++; *************** *** 539,543 **** signal (SIGBUS, handler); ! /* Try to discover a valid linker/assembler/nm to use. */ len = strlen (argv[0]); prefix = (char *)0; --- 469,473 ---- signal (SIGBUS, handler); ! /* Try to discover a valid linker/assembler/nm/strip to use. */ len = strlen (argv[0]); prefix = (char *)0; *************** *** 588,595 **** #endif ld_file_name = xcalloc (len + sizeof ("real-ld"), 1); nm_file_name = xcalloc (len + sizeof ("gnm"), 1); ! memcpy (ld_file_name, prefix, len); strcpy (ld_file_name + len, "real-ld"); if (access (ld_file_name, X_OK) < 0) --- 518,533 ---- #endif + #ifdef STANDARD_EXEC_PREFIX + if (clen < sizeof (STANDARD_EXEC_PREFIX) - 1) + clen = sizeof (STANDARD_EXEC_PREFIX) - 1; + #endif + + /* Allocate enough string space for the longest possible pathnames. */ ld_file_name = xcalloc (len + sizeof ("real-ld"), 1); nm_file_name = xcalloc (len + sizeof ("gnm"), 1); + strip_file_name = xcalloc (len + sizeof ("gstrip"), 1); ! /* Determine the full path name of the ld program to use. */ ! bcopy (prefix, ld_file_name, len); strcpy (ld_file_name + len, "real-ld"); if (access (ld_file_name, X_OK) < 0) *************** *** 602,606 **** ld_file_name = REAL_LD_FILE_NAME; #else ! ld_file_name = (access ("/usr/bin/ld", X_OK) == 0) ? "/usr/bin/ld" : "/bin/ld"; #endif } --- 540,545 ---- ld_file_name = REAL_LD_FILE_NAME; #else ! ld_file_name = (access ("/usr/bin/ld", X_OK) == 0 ! ? "/usr/bin/ld" : "/bin/ld"); #endif } *************** *** 607,610 **** --- 546,550 ---- } + /* Determine the full path name of the C compiler to use. */ c_file_name = getenv ("COLLECT_GCC"); if (c_file_name == 0 || c_file_name[0] != '/') *************** *** 611,615 **** { c_file_name = xcalloc (clen + sizeof ("gcc"), 1); ! memcpy (c_file_name, prefix, len); strcpy (c_file_name + len, "gcc"); if (access (c_file_name, X_OK) < 0) --- 551,555 ---- { c_file_name = xcalloc (clen + sizeof ("gcc"), 1); ! bcopy (prefix, c_file_name, len); strcpy (c_file_name + len, "gcc"); if (access (c_file_name, X_OK) < 0) *************** *** 633,637 **** } ! memcpy (nm_file_name, prefix, len); strcpy (nm_file_name + len, "nm"); if (access (nm_file_name, X_OK) < 0) --- 573,578 ---- } ! /* Determine the full path name of the nm to use. */ ! bcopy (prefix, nm_file_name, len); strcpy (nm_file_name + len, "nm"); if (access (nm_file_name, X_OK) < 0) *************** *** 644,648 **** nm_file_name = REAL_NM_FILE_NAME; #else ! nm_file_name = (access ("/usr/bin/nm", X_OK) == 0) ? "/usr/bin/nm" : "/bin/nm"; #endif } --- 585,608 ---- nm_file_name = REAL_NM_FILE_NAME; #else ! nm_file_name = (access ("/usr/bin/nm", X_OK) == 0 ! ? "/usr/bin/nm" : "/bin/nm"); ! #endif ! } ! } ! ! /* Determine the full pathname of the strip to use. */ ! bcopy (prefix, strip_file_name, len); ! strcpy (strip_file_name + len, "strip"); ! if (access (strip_file_name, X_OK) < 0) ! { ! strcpy (strip_file_name + len, "gstrip"); ! if (access (strip_file_name, X_OK) < 0) ! { ! free (strip_file_name); ! #ifdef REAL_STRIP_FILE_NAME ! strip_file_name = REAL_STRIP_FILE_NAME; ! #else ! strip_file_name = (access ("/usr/bin/strip", X_OK) == 0 ! ? "/usr/bin/strip" : "/bin/strip"); #endif } *************** *** 699,702 **** --- 659,673 ---- break; + case 's': + if (arg[2] == '\0') + { + /* We must strip after the nm run, otherwise C++ linking + won't work. Thus we strip in the second ld run, or + else with strip if there is no second ld run. */ + strip_flag = 1; + ld1--; + } + break; + case 'v': if (arg[2] == '\0') *************** *** 789,797 **** if (constructors.number == 0 && destructors.number == 0) ! return 0; outf = fopen (c_file, "w"); if (outf == (FILE *)0) ! fatal_perror ("Can't write %s", c_file); write_c_file (outf, c_file); --- 760,779 ---- if (constructors.number == 0 && destructors.number == 0) ! { ! /* Strip now if it was requested on the command line. */ ! if (strip_flag) ! { ! char **strip_argv = (char **) xcalloc (sizeof (char *), 3); ! strip_argv[0] = "strip"; ! strip_argv[1] = outfile; ! strip_argv[2] = (char *) 0; ! fork_execute (strip_file_name, strip_argv); ! } ! return 0; ! } outf = fopen (c_file, "w"); if (outf == (FILE *)0) ! fatal_perror ("%s", c_file); write_c_file (outf, c_file); *************** *** 798,802 **** if (fclose (outf)) ! fatal_perror ("Can't close %s", c_file); if (debug) --- 780,784 ---- if (fclose (outf)) ! fatal_perror ("closing %s", c_file); if (debug) *************** *** 898,902 **** { execvp (prog, argv); ! fatal_perror ("Execute %s", prog); } --- 880,884 ---- { execvp (prog, argv); ! fatal_perror ("executing %s", prog); } *************** *** 985,989 **** fprintf (stream, "typedef void entry_pt();\n\n"); ! write_list_with_asm (stream, "entry_pt ", constructors.first); fprintf (stream, "\nentry_pt * __CTOR_LIST__[] = {\n"); --- 967,971 ---- fprintf (stream, "typedef void entry_pt();\n\n"); ! write_list_with_asm (stream, "extern entry_pt ", constructors.first); fprintf (stream, "\nentry_pt * __CTOR_LIST__[] = {\n"); *************** *** 992,996 **** fprintf (stream, "\t0\n};\n\n"); ! write_list_with_asm (stream, "entry_pt ", destructors.first); fprintf (stream, "\nentry_pt * __DTOR_LIST__[] = {\n"); --- 974,978 ---- fprintf (stream, "\t0\n};\n\n"); ! write_list_with_asm (stream, "extern entry_pt ", destructors.first); fprintf (stream, "\nentry_pt * __DTOR_LIST__[] = {\n"); *************** *** 1071,1084 **** /* setup stdout */ if (dup2 (pipe_fd[1], 1) < 0) ! fatal_perror ("Dup2 (%d, 1)", pipe_fd[1]); if (close (pipe_fd[0]) < 0) ! fatal_perror ("Close (%d)", pipe_fd[0]); if (close (pipe_fd[1]) < 0) ! fatal_perror ("Close (%d)", pipe_fd[1]); execv (nm_file_name, nm_argv); ! fatal_perror ("Execute %s", nm_file_name); } --- 1053,1066 ---- /* setup stdout */ if (dup2 (pipe_fd[1], 1) < 0) ! fatal_perror ("dup2 (%d, 1)", pipe_fd[1]); if (close (pipe_fd[0]) < 0) ! fatal_perror ("close (%d)", pipe_fd[0]); if (close (pipe_fd[1]) < 0) ! fatal_perror ("close (%d)", pipe_fd[1]); execv (nm_file_name, nm_argv); ! fatal_perror ("executing %s", nm_file_name); } *************** *** 1088,1092 **** if (close (pipe_fd[1]) < 0) ! fatal_perror ("Close (%d)", pipe_fd[1]); if (debug) --- 1070,1074 ---- if (close (pipe_fd[1]) < 0) ! fatal_perror ("close (%d)", pipe_fd[1]); if (debug) *************** *** 1156,1167 **** #if defined(EXTENDED_COFF) ! # define GCC_SYMBOLS(X) (SYMHEADER(X).isymMax+SYMHEADER(X).iextMax) ! # define GCC_SYMENT SYMR ! # define GCC_OK_SYMBOL(X) ((X).st == stProc && (X).sc == scText) ! # define GCC_SYMINC(X) (1) ! # define GCC_SYMZERO(X) (SYMHEADER(X).isymMax) #else ! # define GCC_SYMBOLS(X) (HEADER(ldptr).f_nsyms) ! # define GCC_SYMENT SYMENT # define GCC_OK_SYMBOL(X) \ (((X).n_sclass == C_EXT) && \ --- 1138,1150 ---- #if defined(EXTENDED_COFF) ! # define GCC_SYMBOLS(X) (SYMHEADER(X).isymMax + SYMHEADER(X).iextMax) ! # define GCC_SYMENT SYMR ! # define GCC_OK_SYMBOL(X) ((X).st == stProc && (X).sc == scText) ! # define GCC_SYMINC(X) (1) ! # define GCC_SYMZERO(X) (SYMHEADER(X).isymMax) ! # define GCC_CHECK_HDR(X) (PSYMTAB(X) != 0) #else ! # define GCC_SYMBOLS(X) (HEADER(ldptr).f_nsyms) ! # define GCC_SYMENT SYMENT # define GCC_OK_SYMBOL(X) \ (((X).n_sclass == C_EXT) && \ *************** *** 1168,1173 **** (((X).n_type & N_TMASK) == (DT_NON << N_BTSHFT) || \ ((X).n_type & N_TMASK) == (DT_FCN << N_BTSHFT))) ! # define GCC_SYMINC(X) ((X).n_numaux+1) ! # define GCC_SYMZERO(X) 0 #endif --- 1151,1157 ---- (((X).n_type & N_TMASK) == (DT_NON << N_BTSHFT) || \ ((X).n_type & N_TMASK) == (DT_FCN << N_BTSHFT))) ! # define GCC_SYMINC(X) ((X).n_numaux+1) ! # define GCC_SYMZERO(X) 0 ! # define GCC_CHECK_HDR(X) (1) #endif *************** *** 1200,1251 **** fatal ("%s: not a COFF file", prog_name); ! sym_count = GCC_SYMBOLS (ldptr); ! sym_index = GCC_SYMZERO (ldptr); ! while (sym_index < sym_count) { ! GCC_SYMENT symbol; ! if (ldtbread (ldptr, sym_index, &symbol) <= 0) ! break; ! sym_index += GCC_SYMINC (symbol); ! if (GCC_OK_SYMBOL (symbol)) ! { ! char *name; ! if ((name = ldgetname (ldptr, &symbol)) == NULL) ! continue; /* should never happen */ #ifdef _AIX ! /* All AIX function names begin with a dot. */ ! if (*name++ != '.') ! continue; #endif ! switch (is_ctor_dtor (name)) ! { ! case 1: ! add_to_list (&constructors, name); ! break; ! ! case 2: ! add_to_list (&destructors, name); ! break; ! default: /* not a constructor or destructor */ ! continue; ! } #if !defined(EXTENDED_COFF) ! if (debug) ! fprintf (stderr, "\tsec=%d class=%d type=%s%o %s\n", ! symbol.n_scnum, symbol.n_sclass, ! (symbol.n_type ? "0" : ""), symbol.n_type, ! name); #else ! if (debug) ! fprintf (stderr, "\tiss = %5d, value = %5d, index = %5d, name = %s\n", ! symbol.iss, symbol.value, symbol.index, name); #endif } } --- 1184,1238 ---- fatal ("%s: not a COFF file", prog_name); ! if (GCC_CHECK_HDR (ldptr)) { ! sym_count = GCC_SYMBOLS (ldptr); ! sym_index = GCC_SYMZERO (ldptr); ! while (sym_index < sym_count) ! { ! GCC_SYMENT symbol; ! if (ldtbread (ldptr, sym_index, &symbol) <= 0) ! break; ! sym_index += GCC_SYMINC (symbol); ! if (GCC_OK_SYMBOL (symbol)) ! { ! char *name; ! if ((name = ldgetname (ldptr, &symbol)) == NULL) ! continue; /* should never happen */ #ifdef _AIX ! /* All AIX function names begin with a dot. */ ! if (*name++ != '.') ! continue; #endif ! switch (is_ctor_dtor (name)) ! { ! case 1: ! add_to_list (&constructors, name); ! break; ! ! case 2: ! add_to_list (&destructors, name); ! break; ! default: /* not a constructor or destructor */ ! continue; ! } #if !defined(EXTENDED_COFF) ! if (debug) ! fprintf (stderr, "\tsec=%d class=%d type=%s%o %s\n", ! symbol.n_scnum, symbol.n_sclass, ! (symbol.n_type ? "0" : ""), symbol.n_type, ! name); #else ! if (debug) ! fprintf (stderr, "\tiss = %5d, value = %5d, index = %5d, name = %s\n", ! symbol.iss, symbol.value, symbol.index, name); #endif + } } } *************** *** 1352,1356 **** prog_fd = open (prog_name, (rw) ? O_RDWR : O_RDONLY); if (prog_fd < 0) ! fatal_perror ("Can't read %s", prog_name); obj_file = read_file (prog_name, prog_fd, rw); --- 1339,1343 ---- prog_fd = open (prog_name, (rw) ? O_RDWR : O_RDONLY); if (prog_fd < 0) ! fatal_perror ("can't read %s", prog_name); obj_file = read_file (prog_name, prog_fd, rw); *************** *** 1375,1379 **** || hdr.moh_vendor_type != OUR_VENDOR_TYPE) { ! fatal ("incompatibilities exist between object file & expected values."); } #endif --- 1362,1366 ---- || hdr.moh_vendor_type != OUR_VENDOR_TYPE) { ! fatal ("incompatibilities between object file & expected values"); } #endif *************** *** 1398,1402 **** { load_union_t *ptr = (load_union_t *) xmalloc (load_hdr->hdr.ldci_cmd_size); ! memcpy (ptr, load_hdr, load_hdr->hdr.ldci_cmd_size); load_hdr = ptr; --- 1385,1389 ---- { load_union_t *ptr = (load_union_t *) xmalloc (load_hdr->hdr.ldci_cmd_size); ! bcopy (load_hdr, ptr, load_hdr->hdr.ldci_cmd_size); load_hdr = ptr; *************** *** 1506,1510 **** if (symbol_load_cmds == 0) ! fatal ("no symbol table found."); /* Update the program file now, rewrite header and load commands. At present, --- 1493,1497 ---- if (symbol_load_cmds == 0) ! fatal ("no symbol table found"); /* Update the program file now, rewrite header and load commands. At present, *************** *** 1519,1526 **** if (cmd_strings == -1) ! fatal ("no cmd_strings found."); ! /* Add __main to initializer list. */ ! if (main_sym != (symbol_info_t *)0) add_func_table (&hdr, load_array, main_sym, FNTC_INITIALIZATION); --- 1506,1518 ---- if (cmd_strings == -1) ! fatal ("no cmd_strings found"); ! ! /* Add __main to initializer list. ! If we are building a program instead of a shared library, don't ! do anything, since in the current version, you cannot do mallocs ! and such in the constructors. */ ! if (main_sym != (symbol_info_t *)0 ! && ((hdr.moh_flags & MOH_EXECABLE_F) == 0)) add_func_table (&hdr, load_array, main_sym, FNTC_INITIALIZATION); *************** *** 1576,1580 **** print_load_command (load_hdr, offset, i); ! memcpy (obj + offset, load_hdr, size); offset += size; } --- 1568,1572 ---- print_load_command (load_hdr, offset, i); ! bcopy (load_hdr, obj + offset, size); offset += size; } *************** *** 1584,1588 **** if (close (prog_fd)) ! fatal_perror ("Can't close %s", prog_name); if (debug) --- 1576,1580 ---- if (close (prog_fd)) ! fatal_perror ("closing %s", prog_name); if (debug) diff -rc2N gcc-2.1/combine.c gcc-2.2.1/combine.c *** gcc-2.1/combine.c Mon Mar 23 14:40:33 1992 --- gcc-2.2.1/combine.c Tue Jun 2 17:35:27 1992 *************** *** 908,915 **** && (reg_overlap_mentioned_p (i2dest, inner_dest) || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)))) ! /* This is the same test done in can_combine_p. */ || (GET_CODE (inner_dest) == REG && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER ! #ifndef SMALL_REGISTER_CLASSES && ! HARD_REGNO_MODE_OK (REGNO (inner_dest), GET_MODE (inner_dest)) --- 908,919 ---- && (reg_overlap_mentioned_p (i2dest, inner_dest) || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)))) ! /* This is the same test done in can_combine_p except that we ! allow a hard register with SMALL_REGISTER_CLASSES if SRC is a ! CALL operation. */ || (GET_CODE (inner_dest) == REG && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER ! #ifdef SMALL_REGISTER_CLASSES ! && GET_CODE (src) != CALL ! #else && ! HARD_REGNO_MODE_OK (REGNO (inner_dest), GET_MODE (inner_dest)) *************** *** 1151,1155 **** i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); ! /* See if I1 directly feeds into I3. It does if I1dest is not used in I2SRC. */ i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src); --- 1155,1159 ---- i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); ! /* See if I1 directly feeds into I3. It does if I1DEST is not used in I2SRC. */ i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src); *************** *** 1353,1359 **** } ! /* Fail if an autoincrement side-effect has been duplicated. */ ! if ((i2_is_used > 1 && FIND_REG_INC_NOTE (i2, 0) != 0) ! || (i1 != 0 && n_occurrences > 1 && FIND_REG_INC_NOTE (i1, 0) != 0) /* Fail if we tried to make a new register (we used to abort, but there's really no reason to). */ --- 1357,1367 ---- } ! /* Fail if an autoincrement side-effect has been duplicated. Be careful ! to count all the ways that I2SRC and I1SRC can be used. */ ! if ((FIND_REG_INC_NOTE (i2, 0) != 0 ! && i2_is_used + added_sets_2 > 1) ! || (i1 != 0 && FIND_REG_INC_NOTE (i1, 0) != 0 ! && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3) ! > 1)) /* Fail if we tried to make a new register (we used to abort, but there's really no reason to). */ *************** *** 1454,1462 **** /* If we were combining three insns and the result is a simple SET with no ASM_OPERANDS that wasn't recognized, try to split it into two ! insns. */ if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET && asm_noperands (newpat) < 0) { ! rtx *split = find_split_point (&newpat); /* If we can split it and use I2DEST, go ahead and see if that --- 1462,1498 ---- /* If we were combining three insns and the result is a simple SET with no ASM_OPERANDS that wasn't recognized, try to split it into two ! insns. There are two ways to do this. It can be split using a ! machine-specific method (like when you have an addition of a large ! constant) or by combine in the function find_split_point. */ ! if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET && asm_noperands (newpat) < 0) { ! rtx m_split, *split; ! ! /* See if the MD file can split NEWPAT. If it can't, see if letting it ! use I2DEST as a scratch register will help. */ ! ! m_split = split_insns (newpat, i3); ! if (m_split == 0) ! m_split = split_insns (gen_rtx (PARALLEL, VOIDmode, ! gen_rtvec (2, newpat, ! gen_rtx (CLOBBER, VOIDmode, ! i2dest))), ! i3); ! ! if (m_split && GET_CODE (m_split) == SEQUENCE ! && XVECLEN (m_split, 0) == 2 ! && (next_real_insn (i2) == i3 ! || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)), ! INSN_CUID (i2)))) ! { ! newi2pat = PATTERN (XVECEXP (m_split, 0, 0)); ! newpat = PATTERN (XVECEXP (m_split, 0, 1)); ! ! i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); ! if (i2_code_number >= 0) ! insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); ! } /* If we can split it and use I2DEST, go ahead and see if that *************** *** 1463,1467 **** helps things be recognized. Verify that none of the registers are set between I2 and I3. */ ! if (split #ifdef HAVE_cc0 && GET_CODE (i2dest) == REG --- 1499,1503 ---- helps things be recognized. Verify that none of the registers are set between I2 and I3. */ ! else if ((split = find_split_point (&newpat)) != 0 #ifdef HAVE_cc0 && GET_CODE (i2dest) == REG *************** *** 1910,1915 **** return find_split_point (&SUBREG_REG (x)); - #ifdef HAVE_lo_sum case MEM: /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it using LO_SUM and HIGH. */ --- 1946,1951 ---- return find_split_point (&SUBREG_REG (x)); case MEM: + #ifdef HAVE_lo_sum /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it using LO_SUM and HIGH. */ *************** *** 1923,1929 **** return &XEXP (XEXP (x, 0), 0); } - break; #endif case SET: #ifdef HAVE_cc0 --- 1959,2019 ---- return &XEXP (XEXP (x, 0), 0); } #endif + /* If we have a PLUS whose second operand is a constant and the + address is not valid, perhaps will can split it up using + the machine-specific way to split large constants. We use + the first psuedo-reg (one of the virtual regs) as a placeholder; + it will not remain in the result. */ + if (GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && ! memory_address_p (GET_MODE (x), XEXP (x, 0))) + { + rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; + rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)), + subst_insn); + + /* This should have produced two insns, each of which sets our + placeholder. If the source of the second is a valid address, + we can make put both sources together and make a split point + in the middle. */ + + if (seq && XVECLEN (seq, 0) == 2 + && GET_CODE (XVECEXP (seq, 0, 0)) == INSN + && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET + && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg + && ! reg_mentioned_p (reg, + SET_SRC (PATTERN (XVECEXP (seq, 0, 0)))) + && GET_CODE (XVECEXP (seq, 0, 1)) == INSN + && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET + && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg + && memory_address_p (GET_MODE (x), + SET_SRC (PATTERN (XVECEXP (seq, 0, 1))))) + { + rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0))); + rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1))); + + /* Replace the placeholder in SRC2 with SRC1. If we can + find where in SRC2 it was placed, that can become our + split point and we can replace this address with SRC2. + Just try two obvious places. */ + + src2 = replace_rtx (src2, reg, src1); + split = 0; + if (XEXP (src2, 0) == src1) + split = &XEXP (src2, 0); + else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' + && XEXP (XEXP (src2, 0), 0) == src1) + split = &XEXP (XEXP (src2, 0), 0); + + if (split) + { + SUBST (XEXP (x, 0), src2); + return split; + } + } + } + break; + case SET: #ifdef HAVE_cc0 *************** *** 2501,2508 **** /* For a constant, try to pick up the part we want. Handle a full ! word and low-order part. */ if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode && GET_MODE_SIZE (mode) == UNITS_PER_WORD && GET_MODE_CLASS (mode) == MODE_INT) { --- 2591,2601 ---- /* For a constant, try to pick up the part we want. Handle a full ! word and low-order part. Only do this if we are narrowing ! the constant; if it is being widened, we have no idea what ! the extra bits will have been set to. */ if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode && GET_MODE_SIZE (mode) == UNITS_PER_WORD + && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD && GET_MODE_CLASS (mode) == MODE_INT) { *************** *** 2513,2517 **** } ! if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)) return gen_lowpart_for_combine (mode, SUBREG_REG (x)); --- 2606,2611 ---- } ! if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x) ! && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode)) return gen_lowpart_for_combine (mode, SUBREG_REG (x)); *************** *** 2930,2938 **** X is a ZERO_EXTRACT of one bit. Similarly, we can convert EQ to (xor X 1). */ ! if (new_code == NE && mode != VOIDmode && op1 == const0_rtx && significant_bits (op0, GET_MODE (op0)) == 1) return gen_lowpart_for_combine (mode, op0); ! else if (new_code == EQ && mode != VOIDmode && op1 == const0_rtx && significant_bits (op0, GET_MODE (op0)) == 1) --- 3024,3032 ---- X is a ZERO_EXTRACT of one bit. Similarly, we can convert EQ to (xor X 1). */ ! if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT && op1 == const0_rtx && significant_bits (op0, GET_MODE (op0)) == 1) return gen_lowpart_for_combine (mode, op0); ! else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT && op1 == const0_rtx && significant_bits (op0, GET_MODE (op0)) == 1) *************** *** 2947,2951 **** This converts (ne (zero_extract X 1 Y) 0) to (sign_extract X 1 Y). */ ! if (new_code == NE && mode != VOIDmode && op1 == const0_rtx && significant_bits (op0, GET_MODE (op0)) == 1) --- 3041,3045 ---- This converts (ne (zero_extract X 1 Y) 0) to (sign_extract X 1 Y). */ ! if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT && op1 == const0_rtx && significant_bits (op0, GET_MODE (op0)) == 1) *************** *** 2962,2966 **** STORE_FLAG_VALUE when we are done, since we are only going to test the sign bit. */ ! if (new_code == NE && mode != VOIDmode && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT && STORE_FLAG_VALUE == 1 << (GET_MODE_BITSIZE (mode) - 1) --- 3056,3060 ---- STORE_FLAG_VALUE when we are done, since we are only going to test the sign bit. */ ! if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT && STORE_FLAG_VALUE == 1 << (GET_MODE_BITSIZE (mode) - 1) *************** *** 2992,2996 **** reversed, do so to avoid needing two sets of patterns for subtract-and-branch insns. */ ! if (XEXP (x, 1) == pc_rtx && reversible_comparison_p (XEXP (x, 0))) { SUBST (XEXP (x, 0), --- 3086,3092 ---- reversed, do so to avoid needing two sets of patterns for subtract-and-branch insns. */ ! if (XEXP (x, 1) == pc_rtx ! && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' ! && reversible_comparison_p (XEXP (x, 0))) { SUBST (XEXP (x, 0), *************** *** 3522,3525 **** --- 3618,3628 ---- break; + case FFS: + /* (ffs (*_extend )) = (ffs ) */ + if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND + || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) + SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); + break; + case FLOAT: /* (float (sign_extend )) = (float ). */ *************** *** 3594,3602 **** unsignedp = 1; case SIGN_EXTEND: ! /* If we somehow managed to end up with (sign/zero_extend (const_int x)), ! just return the CONST_INT. We can't know how much masking to do ! in that case. */ if (GET_CODE (XEXP (x, 0)) == CONST_INT) ! return XEXP (x, 0); if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0))) --- 3697,3710 ---- unsignedp = 1; case SIGN_EXTEND: ! /* We can't necessarily use a const_int for a multiword mode; ! it depends on implicitly extending the value. ! Since we don't know the right way to extend it, ! we can't tell whether the implicit way is right. ! ! Even for a mode that is no wider than a const_int, ! we can't win, because we need to sign extend one of its bits through ! the rest of it, and we don't know which bit. */ if (GET_CODE (XEXP (x, 0)) == CONST_INT) ! return x; if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0))) *************** *** 4146,4150 **** 0, in_code == COMPARE); ! /* One machines without logical shifts, if the operand of the AND is a logical shift and our mask turns off all the propagated sign bits, we can replace the logical shift with an arithmetic shift. */ --- 4254,4271 ---- 0, in_code == COMPARE); ! ! /* If we are have (and (rotate X C) M) and C is larger than the number ! of bits in M, this is an extraction. */ ! ! else if (GET_CODE (XEXP (x, 0)) == ROTATE ! && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT ! && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0 ! && i <= INTVAL (XEXP (XEXP (x, 0), 1))) ! new = make_extraction (mode, XEXP (XEXP (x, 0), 0), ! (GET_MODE_BITSIZE (mode) ! - INTVAL (XEXP (XEXP (x, 0), 1))), ! 0, i, 1, 0, in_code == COMPARE); ! ! /* On machines without logical shifts, if the operand of the AND is a logical shift and our mask turns off all the propagated sign bits, we can replace the logical shift with an arithmetic shift. */ *************** *** 4318,4323 **** case CONST_INT: if (bits < HOST_BITS_PER_INT) ! x = gen_rtx (CONST_INT, VOIDmode, ! INTVAL (x) & ((1 << (bits + 1)) - 1)); return x; --- 4439,4443 ---- case CONST_INT: if (bits < HOST_BITS_PER_INT) ! x = gen_rtx (CONST_INT, VOIDmode, INTVAL (x) & ((1 << bits) - 1)); return x; *************** *** 4346,4350 **** if (bits < HOST_BITS_PER_INT) ! mask &= (1 << (bits + 1)) - 1; x = simplify_and_const_int (x, mode, op, mask); --- 4466,4470 ---- if (bits < HOST_BITS_PER_INT) ! mask &= (1 << bits) - 1; x = simplify_and_const_int (x, mode, op, mask); *************** *** 4356,4360 **** if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT && bits < HOST_BITS_PER_INT ! && INTVAL (XEXP (x, 1)) == (1 << (bits + 1)) - 1) x = XEXP (x, 0); return x; --- 4476,4480 ---- if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT && bits < HOST_BITS_PER_INT ! && INTVAL (XEXP (x, 1)) == (1 << bits) - 1) x = XEXP (x, 0); return x; *************** *** 4576,4582 **** /* Non-paradoxical SUBREGs distributes over all operations, provided the inner modes and word numbers are the same, this is an extraction ! of a low-order part, and we would not be converting a single-word operation into a multi-word operation. The latter test is not ! required, but we prevents generating unneeded multi-word operations. Some of the previous tests are redundant given the latter test, but are retained because they are required for correctness. --- 4696,4703 ---- /* Non-paradoxical SUBREGs distributes over all operations, provided the inner modes and word numbers are the same, this is an extraction ! of a low-order part, we don't convert an fp operation to int or ! vice versa, and we would not be converting a single-word operation into a multi-word operation. The latter test is not ! required, but it prevents generating unneeded multi-word operations. Some of the previous tests are redundant given the latter test, but are retained because they are required for correctness. *************** *** 4587,4590 **** --- 4708,4713 ---- || SUBREG_WORD (lhs) != SUBREG_WORD (rhs) || ! subreg_lowpart_p (lhs) + || (GET_MODE_CLASS (GET_MODE (lhs)) + != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs)))) || (GET_MODE_SIZE (GET_MODE (lhs)) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs)))) *************** *** 5027,5031 **** case GE: case GEU: case LE: case LEU: ! significant = 1; /* A comparison operation only sets the bits given by its mode. The --- 5150,5156 ---- case GE: case GEU: case LE: case LEU: ! ! if (GET_MODE_CLASS (mode) == MODE_INT) ! significant = 1; /* A comparison operation only sets the bits given by its mode. The *************** *** 5897,5900 **** --- 6022,6052 ---- } + /* If we have (xshiftrt (plus FOO BAR) C), and the only bits + significant in BAR are those being shifted out and those + bits are known zero in FOO, we can replace the PLUS with FOO. + Similarly in the other operand order. This code occurs when + we are computing the size of a variable-size array. */ + + if ((code == ASHIFTRT || code == LSHIFTRT) + && count < HOST_BITS_PER_INT + && significant_bits (XEXP (varop, 1), result_mode) >> count == 0 + && (significant_bits (XEXP (varop, 1), result_mode) + & significant_bits (XEXP (varop, 0), result_mode)) == 0) + { + varop = XEXP (varop, 0); + continue; + } + else if ((code == ASHIFTRT || code == LSHIFTRT) + && count < HOST_BITS_PER_INT + && 0 == (significant_bits (XEXP (varop, 0), result_mode) + >> count) + && 0 == (significant_bits (XEXP (varop, 0), result_mode) + & significant_bits (XEXP (varop, 1), + result_mode))) + { + varop = XEXP (varop, 1); + continue; + } + /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ if (code == ASHIFT *************** *** 6192,6196 **** /* If we couldn't simplify X any other way, just enclose it in a SUBREG. Normally, this SUBREG won't match, but some patterns may ! include and explicit SUBREG or we may simplify it further in combine. */ else { --- 6344,6348 ---- /* If we couldn't simplify X any other way, just enclose it in a SUBREG. Normally, this SUBREG won't match, but some patterns may ! include an explicit SUBREG or we may simplify it further in combine. */ else { *************** *** 6459,6463 **** const_op = INTVAL (op1); if (mode_width <= HOST_BITS_PER_INT) ! const_op &= GET_MODE_MASK (mode); /* If we are comparing against a constant power of two and the value --- 6611,6615 ---- const_op = INTVAL (op1); if (mode_width <= HOST_BITS_PER_INT) ! const_op &= mask; /* If we are comparing against a constant power of two and the value *************** *** 6477,6481 **** /* Do some canonicalizations based on the comparison code. We prefer ! comparisons against zero and then prefer equality comparisons. */ switch (code) --- 6629,6634 ---- /* Do some canonicalizations based on the comparison code. We prefer ! comparisons against zero and then prefer equality comparisons. ! If we can reduce the size of a constant, we will do that too. */ switch (code) *************** *** 6482,6490 **** { case LT: ! /* < 1 is equivalent to <= 0 */ ! if (const_op == 1) { ! op1 = const0_rtx; ! const_op = 0; code = LE; /* ... fall through to LE case below. */ --- 6635,6643 ---- { case LT: ! /* < C is equivalent to <= (C - 1) */ ! if (const_op > 0) { ! const_op -= 1; ! op1 = gen_rtx (CONST_INT, VOIDmode, const_op); code = LE; /* ... fall through to LE case below. */ *************** *** 6494,6500 **** case LE: ! /* <= -1 is equivalent to < 0 */ ! if (op1 == constm1_rtx) ! op1 = const0_rtx, const_op = 0, code = LT; /* If we are doing a <= 0 comparison on a value known to have --- 6647,6657 ---- case LE: ! /* <= C is equivalent to < (C + 1); we do this for C < 0 */ ! if (const_op < 0) ! { ! const_op += 1; ! op1 = gen_rtx (CONST_INT, VOIDmode, const_op); ! code = LT; ! } /* If we are doing a <= 0 comparison on a value known to have *************** *** 6508,6516 **** case GE: ! /* >= 1 is equivalent to > 0. */ ! if (const_op == 1) { ! op1 = const0_rtx; ! const_op = 0; code = GT; /* ... fall through to GT below. */ --- 6665,6673 ---- case GE: ! /* >= C is equivalent to > (C - 1). */ ! if (const_op > 0) { ! const_op -= 1; ! op1 = gen_rtx (CONST_INT, VOIDmode, const_op); code = GT; /* ... fall through to GT below. */ *************** *** 6520,6526 **** case GT: ! /* > -1 is equivalent to >= 0. */ ! if (op1 == constm1_rtx) ! op1 = const0_rtx, const_op = 0, code = GE; /* If we are doing a > 0 comparison on a value known to have --- 6677,6687 ---- case GT: ! /* > C is equivalent to >= (C + 1); we do this for C < 0*/ ! if (const_op < 0) ! { ! const_op += 1; ! op1 = gen_rtx (CONST_INT, VOIDmode, const_op); ! code = GE; ! } /* If we are doing a > 0 comparison on a value known to have *************** *** 6533,6547 **** break; - case GEU: - /* unsigned >= 1 is equivalent to != 0 */ - if (const_op == 1) - op1 = const0_rtx, const_op = 0, code = NE; - break; - case LTU: ! /* unsigned < 1 is equivalent to == 0 */ ! if (const_op == 1) ! op1 = const0_rtx, const_op = 0, code = EQ; ! break; case LEU: --- 6694,6708 ---- break; case LTU: ! /* < C is equivalent to <= (C - 1). */ ! if (const_op > 0) ! { ! const_op -= 1; ! op1 = gen_rtx (CONST_INT, VOIDmode, const_op); ! code = LEU; ! /* ... fall through ... */ ! } ! else ! break; case LEU: *************** *** 6551,6554 **** --- 6712,6727 ---- break; + case GEU: + /* >= C is equivalent to < (C - 1). */ + if (const_op > 1) + { + const_op -= 1; + op1 = gen_rtx (CONST_INT, VOIDmode, const_op); + code = GTU; + /* ... fall through ... */ + } + else + break; + case GTU: /* unsigned > 0 is equivalent to != 0 */ *************** *** 6836,6839 **** --- 7009,7013 ---- || (code == EQ && reversible_comparison_p (op0)) || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT + && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT && (STORE_FLAG_VALUE & (1 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))) *************** *** 7610,7622 **** move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes); ! if (GET_CODE (dest) == ZERO_EXTRACT) ! { ! move_deaths (XEXP (dest, 1), from_cuid, to_insn, pnotes); ! move_deaths (XEXP (dest, 2), from_cuid, to_insn, pnotes); ! } ! ! while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG ! || GET_CODE (dest) == STRICT_LOW_PART) ! dest = XEXP (dest, 0); if (GET_CODE (dest) == MEM) --- 7784,7812 ---- move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes); ! /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG ! that accesses one word of a multi-word item, some ! piece of everything register in the expression is used by ! this insn, so remove any old death. */ ! ! if (GET_CODE (dest) == ZERO_EXTRACT ! || GET_CODE (dest) == STRICT_LOW_PART ! || (GET_CODE (dest) == SUBREG ! && (((GET_MODE_SIZE (GET_MODE (dest)) ! + UNITS_PER_WORD - 1) / UNITS_PER_WORD) ! == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) ! + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) ! { ! move_deaths (dest, from_cuid, to_insn, pnotes); ! return; ! } ! ! /* If this is some other SUBREG, we know it replaces the entire ! value, so use that as the destination. */ ! if (GET_CODE (dest) == SUBREG) ! dest = SUBREG_REG (dest); ! ! /* If this is a MEM, adjust deaths of anything used in the address. ! For a REG (the only other possibility), the entire value is ! being replaced so the old value is not used in this insn. */ if (GET_CODE (dest) == MEM) *************** *** 7644,7653 **** } ! /* Return 1 if REG is the target of a bit-field assignment in BODY, the ! pattern of an insn. */ static int ! reg_bitfield_target_p (reg, body) ! rtx reg; rtx body; { --- 7834,7843 ---- } ! /* Return 1 if X is the target of a bit-field assignment in BODY, the ! pattern of an insn. X must be a REG. */ static int ! reg_bitfield_target_p (x, body) ! rtx x; rtx body; { *************** *** 7655,7666 **** if (GET_CODE (body) == SET) ! return ((GET_CODE (SET_DEST (body)) == ZERO_EXTRACT ! && rtx_equal_p (reg, XEXP (SET_DEST (body), 0))) ! || (GET_CODE (SET_DEST (body)) == STRICT_LOW_PART ! && rtx_equal_p (reg, SUBREG_REG (XEXP (SET_DEST (body), 0))))); else if (GET_CODE (body) == PARALLEL) for (i = XVECLEN (body, 0) - 1; i >= 0; i--) ! if (reg_bitfield_target_p (reg, XVECEXP (body, 0, i))) return 1; --- 7845,7879 ---- if (GET_CODE (body) == SET) ! { ! rtx dest = SET_DEST (body); ! rtx target; ! int regno, tregno, endregno, endtregno; ! ! if (GET_CODE (dest) == ZERO_EXTRACT) ! target = XEXP (dest, 0); ! else if (GET_CODE (dest) == STRICT_LOW_PART) ! target = SUBREG_REG (XEXP (dest, 0)); ! else ! return 0; ! ! if (GET_CODE (target) == SUBREG) ! target = SUBREG_REG (target); ! ! if (GET_CODE (target) != REG) ! return 0; + tregno = REGNO (target), regno = REGNO (x); + if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) + return target == x; + + endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target)); + endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); + + return endregno > tregno && regno < endtregno; + } + else if (GET_CODE (body) == PARALLEL) for (i = XVECLEN (body, 0) - 1; i >= 0; i--) ! if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) return 1; *************** *** 7910,7921 **** { rtx piece = gen_rtx (REG, word_mode, i); ! rtx use_insn ! = emit_insn_before (gen_rtx (USE, VOIDmode, piece), ! place); all_used = 0; - REG_NOTES (use_insn) - = gen_rtx (EXPR_LIST, REG_DEAD, piece, - REG_NOTES (use_insn)); } --- 8123,8153 ---- { rtx piece = gen_rtx (REG, word_mode, i); ! rtx p; ! ! /* See if we already placed a USE note for this ! register in front of PLACE. */ ! for (p = place; ! GET_CODE (PREV_INSN (p)) == INSN ! && GET_CODE (PATTERN (PREV_INSN (p))) == USE; ! p = PREV_INSN (p)) ! if (rtx_equal_p (piece, ! XEXP (PATTERN (PREV_INSN (p)), 0))) ! { ! p = 0; ! break; ! } ! ! if (p) ! { ! rtx use_insn ! = emit_insn_before (gen_rtx (USE, VOIDmode, ! piece), ! p); ! REG_NOTES (use_insn) ! = gen_rtx (EXPR_LIST, REG_DEAD, piece, ! REG_NOTES (use_insn)); ! } all_used = 0; } diff -rc2N gcc-2.1/config/3b1.h gcc-2.2.1/config/3b1.h *** gcc-2.1/config/3b1.h Tue Mar 10 19:00:31 1992 --- gcc-2.2.1/config/3b1.h Fri Apr 24 23:13:15 1992 *************** *** 191,195 **** { if (lp > 60) \ { lp = 0; \ ! fprintf ((FILE), "\n%s ", ASCII_DATA_ASM_OP); } \ else \ putc (',', (FILE)); \ --- 191,195 ---- { if (lp > 60) \ { lp = 0; \ ! fprintf ((FILE), "\n\t%s ", ASCII_DATA_ASM_OP); } \ else \ putc (',', (FILE)); \ *************** *** 370,377 **** (PREFIX), (NUM), (PREFIX), (NUM)) ! /* At end of a switch table, define LD%n iff the symbol LI%n was defined. */ ! #define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \ ! if (RTX_INTEGRATED_P (TABLE)) \ ! fprintf (FILE, "\tset LD%%%d,L%%%d-LI%%%d\n", (NUM), (NUM), (NUM)) #define ASM_OUTPUT_OPCODE(FILE, PTR) \ --- 370,387 ---- (PREFIX), (NUM), (PREFIX), (NUM)) ! /* At end of a switch table, define LDnnn iff the symbol LInnn was defined. ! Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" ! fails to assemble. Luckily "LDnnn(pc,d0.l*2)" produces the results ! we want. This difference can be accommodated by making the assembler ! define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other ! string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END ! macro. */ ! ! #define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \ ! { if (switch_table_difference_label_flag) \ ! fprintf (FILE, "\tset LD%%%d,L%%%d-LI%%%d\n", (NUM), (NUM), (NUM)) \ ! switch_table_difference_label_flag = 0; } ! ! int switch_table_difference_label_flag; #define ASM_OUTPUT_OPCODE(FILE, PTR) \ diff -rc2N gcc-2.1/config/a29k.c gcc-2.2.1/config/a29k.c *** gcc-2.1/config/a29k.c Thu Feb 13 16:38:58 1992 --- gcc-2.2.1/config/a29k.c Wed Apr 22 18:46:41 1992 *************** *** 184,192 **** int ! gen_reg_or_float_constant_operand (op, mode) rtx op; enum machine_mode mode; { ! return float_const_operand (op, mode) || gen_reg_operand (op, mode); } --- 184,192 ---- int ! gpc_reg_or_float_constant_operand (op, mode) rtx op; enum machine_mode mode; { ! return float_const_operand (op, mode) || gpc_reg_operand (op, mode); } *************** *** 195,199 **** int ! gen_reg_or_integer_constant_operand (op, mode) rtx op; enum machine_mode mode; --- 195,199 ---- int ! gpc_reg_or_integer_constant_operand (op, mode) rtx op; enum machine_mode mode; *************** *** 201,205 **** return ((GET_MODE (op) == VOIDmode && (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)) ! || gen_reg_operand (op, mode)); } --- 201,205 ---- return ((GET_MODE (op) == VOIDmode && (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)) ! || gpc_reg_operand (op, mode)); } *************** *** 229,233 **** int ! gen_reg_operand (op, mode) rtx op; enum machine_mode mode; --- 229,233 ---- int ! gpc_reg_operand (op, mode) rtx op; enum machine_mode mode; *************** *** 268,272 **** return 0; ! return gen_reg_operand (op, mode); } --- 268,272 ---- return 0; ! return gpc_reg_operand (op, mode); } *************** *** 275,283 **** int ! gen_reg_or_immediate_operand (op, mode) rtx op; enum machine_mode; { ! return gen_reg_operand (op, mode) || immediate_operand (op, mode); } --- 275,283 ---- int ! gpc_reg_or_immediate_operand (op, mode) rtx op; enum machine_mode; { ! return gpc_reg_operand (op, mode) || immediate_operand (op, mode); } *************** *** 371,375 **** if (GET_CODE (op) == REG) ! return (mode == SImode || gen_reg_operand (orig_op, mode) || (GET_MODE_CLASS (mode) == MODE_FLOAT && accum_reg_operand (orig_op, mode))); --- 371,375 ---- if (GET_CODE (op) == REG) ! return (mode == SImode || gpc_reg_operand (orig_op, mode) || (GET_MODE_CLASS (mode) == MODE_FLOAT && accum_reg_operand (orig_op, mode))); *************** *** 877,885 **** case 'F': output_addr_const (file, x); ! if (! strcmp (XSTR (x, 0), current_function_name) ! && dbr_sequence_length () == 0) ! fprintf (file, "+4\n\t%s,%d", ! a29k_regstack_size >= 64 ? "const gr121" : "sub gr1,gr1", ! a29k_regstack_size * 4); return; --- 877,889 ---- case 'F': output_addr_const (file, x); ! if (dbr_sequence_length () == 0) ! { ! if (! strcmp (XSTR (x, 0), current_function_name)) ! fprintf (file, "+4\n\t%s,%d", ! a29k_regstack_size >= 64 ? "const gr121" : "sub gr1,gr1", ! a29k_regstack_size * 4); ! else ! fprintf (file, "\n\tnop"); ! } return; diff -rc2N gcc-2.1/config/a29k.h gcc-2.2.1/config/a29k.h *** gcc-2.1/config/a29k.h Mon Mar 16 04:39:35 1992 --- gcc-2.2.1/config/a29k.h Tue May 26 19:25:37 1992 *************** *** 387,390 **** --- 387,394 ---- hold integer values. + DImode and larger values should start at an even register just like + DFmode values, even though the instruction set doesn't require it, in order + to prevent reload from aborting due to a modes_equiv_for_class_p failure. + (I'd like to use the "?:" syntax to make this more readable, but Sun's compiler doesn't seem to accept it.) */ *************** *** 397,402 **** && GET_MODE_CLASS (MODE) != MODE_COMPLEX_FLOAT) \ || ((REGNO) < R_BP \ ! && ((((REGNO) & 1) == 0) || GET_MODE_CLASS (MODE) == MODE_INT \ ! || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT \ || GET_MODE_UNIT_SIZE (MODE) <= UNITS_PER_WORD))) --- 401,405 ---- && GET_MODE_CLASS (MODE) != MODE_COMPLEX_FLOAT) \ || ((REGNO) < R_BP \ ! && ((((REGNO) & 1) == 0) \ || GET_MODE_UNIT_SIZE (MODE) <= UNITS_PER_WORD))) *************** *** 1222,1226 **** only these need be expensive. */ ! #define CONST_COSTS(RTX,CODE) \ case CONST_INT: \ return 0; \ --- 1225,1229 ---- only these need be expensive. */ ! #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ return 0; \ *************** *** 1240,1244 **** The multiply cost depends on whether this is a 29050 or not. */ ! #define RTX_COSTS(X,CODE) \ case MULT: \ return TARGET_29050 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (40); \ --- 1243,1247 ---- The multiply cost depends on whether this is a 29050 or not. */ ! #define RTX_COSTS(X,CODE,OUTER_CODE) \ case MULT: \ return TARGET_29050 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (40); \ *************** *** 1275,1289 **** #define ASM_APP_OFF "" /* Output before instructions. */ ! #define TEXT_SECTION_ASM_OP ".text" /* Output before read-only data. */ ! #define READONLY_DATA_SECTION_ASM_OP ".use .lit" /* Output before writable data. */ ! #define DATA_SECTION_ASM_OP ".data" /* Define an extra section for read-only data, a routine to enter it, and --- 1278,1295 ---- #define ASM_APP_OFF "" + /* The next few macros don't have tabs on most machines, but + at least one 29K assembler wants them. */ + /* Output before instructions. */ ! #define TEXT_SECTION_ASM_OP "\t.text" /* Output before read-only data. */ ! #define READONLY_DATA_SECTION_ASM_OP "\t.use .lit" /* Output before writable data. */ ! #define DATA_SECTION_ASM_OP "\t.data" /* Define an extra section for read-only data, a routine to enter it, and *************** *** 1527,1533 **** {"const_24__operand", {CONST_INT, ASHIFT}}, \ {"float_const_operand", {CONST_DOUBLE}}, \ ! {"gen_reg_operand", {SUBREG, REG}}, \ ! {"gen_reg_or_float_constant_operand", {SUBREG, REG, CONST_DOUBLE}}, \ ! {"gen_reg_or_integer_constant_operand", {SUBREG, REG, \ CONST_INT, CONST_DOUBLE}}, \ {"spec_reg_operand", {REG}}, \ --- 1533,1539 ---- {"const_24__operand", {CONST_INT, ASHIFT}}, \ {"float_const_operand", {CONST_DOUBLE}}, \ ! {"gpc_reg_operand", {SUBREG, REG}}, \ ! {"gpc_reg_or_float_constant_operand", {SUBREG, REG, CONST_DOUBLE}}, \ ! {"gpc_reg_or_integer_constant_operand", {SUBREG, REG, \ CONST_INT, CONST_DOUBLE}}, \ {"spec_reg_operand", {REG}}, \ diff -rc2N gcc-2.1/config/a29k.md gcc-2.2.1/config/a29k.md *** gcc-2.1/config/a29k.md Sat Mar 14 00:15:21 1992 --- gcc-2.2.1/config/a29k.md Wed Apr 22 18:48:22 1992 *************** *** 71,76 **** ;; ADD (define_insn "addsi3" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") ! (plus:SI (match_operand:SI 1 "gen_reg_operand" "%r,r") (match_operand:SI 2 "add_operand" "rI,N")))] "" --- 71,76 ---- ;; ADD (define_insn "addsi3" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") (match_operand:SI 2 "add_operand" "rI,N")))] "" *************** *** 80,86 **** (define_insn "adddi3" ! [(set (match_operand:DI 0 "gen_reg_operand" "=r") ! (plus:DI (match_operand:DI 1 "gen_reg_operand" "%r") ! (match_operand:DI 2 "gen_reg_operand" "r")))] "" "add %L0,%L1,%L2\;addc %0,%1,%2" --- 80,86 ---- (define_insn "adddi3" ! [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r") ! (match_operand:DI 2 "gpc_reg_operand" "r")))] "" "add %L0,%L1,%L2\;addc %0,%1,%2" *************** *** 89,94 **** ;; AND/ANDN (define_insn "andsi3" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") ! (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r") (match_operand:SI 2 "and_operand" "rI,K")))] "" --- 89,94 ---- ;; AND/ANDN (define_insn "andsi3" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") (match_operand:SI 2 "and_operand" "rI,K")))] "" *************** *** 98,104 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (and:SI (not:SI (match_operand:SI 1 "srcb_operand" "rI")) ! (match_operand:SI 2 "gen_reg_operand" "r")))] "" "andn %0,%2,%1") --- 98,104 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (not:SI (match_operand:SI 1 "srcb_operand" "rI")) ! (match_operand:SI 2 "gpc_reg_operand" "r")))] "" "andn %0,%2,%1") *************** *** 160,164 **** (define_expand "call_value" ! [(parallel [(set (match_operand:SI 0 "gen_reg_operand" "") (call (match_operand:SI 1 "" "") (match_operand 2 "" ""))) --- 160,164 ---- (define_expand "call_value" ! [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") (call (match_operand:SI 1 "" "") (match_operand 2 "" ""))) *************** *** 180,184 **** (define_insn "" ! [(set (match_operand 0 "gen_reg_operand" "=r") (call (match_operand:SI 1 "memory_operand" "m") (match_operand 2 "" ""))) --- 180,184 ---- (define_insn "" ! [(set (match_operand 0 "gpc_reg_operand" "=r") (call (match_operand:SI 1 "memory_operand" "m") (match_operand 2 "" ""))) *************** *** 199,203 **** (define_insn "" ! [(set (match_operand 0 "gen_reg_operand" "=r") (call (mem:SI (match_operand:SI 1 "immediate_operand" "i")) (match_operand:SI 2 "general_operand" "g"))) --- 199,203 ---- (define_insn "" ! [(set (match_operand 0 "gpc_reg_operand" "=r") (call (mem:SI (match_operand:SI 1 "immediate_operand" "i")) (match_operand:SI 2 "general_operand" "g"))) *************** *** 228,232 **** ;; Many of these are generated from move insns. (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (and:SI (match_operand:SI 1 "immediate_operand" "i") (const_int 65535)))] --- 228,232 ---- ;; Many of these are generated from move insns. (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (match_operand:SI 1 "immediate_operand" "i") (const_int 65535)))] *************** *** 235,239 **** (define_insn "" ! [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") (const_int 16) (match_operand:SI 1 "const_0_operand" "")) --- 235,239 ---- (define_insn "" ! [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 16) (match_operand:SI 1 "const_0_operand" "")) *************** *** 244,248 **** (define_insn "" ! [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") (const_int 16) (match_operand:SI 1 "const_0_operand" "")) --- 244,248 ---- (define_insn "" ! [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 16) (match_operand:SI 1 "const_0_operand" "")) *************** *** 255,260 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (ior:SI (and:SI (match_operand:SI 1 "gen_reg_operand" "0") (const_int 65535)) (match_operand:SI 2 "const_int_operand" "n")))] --- 255,260 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (ior:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "0") (const_int 65535)) (match_operand:SI 2 "const_int_operand" "n")))] *************** *** 263,268 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (ior:SI (and:SI (match_operand:SI 1 "gen_reg_operand" "0") (const_int 65535)) (and:SI (match_operand:SI 2 "immediate_operand" "i") --- 263,268 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (ior:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "0") (const_int 65535)) (and:SI (match_operand:SI 2 "immediate_operand" "i") *************** *** 274,278 **** ;; CONVERT (define_insn "fix_truncsfsi2" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (fix:SI (match_operand:SF 1 "register_operand" "r")))] "" --- 274,278 ---- ;; CONVERT (define_insn "fix_truncsfsi2" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (fix:SI (match_operand:SF 1 "register_operand" "r")))] "" *************** *** 280,284 **** (define_insn "fix_truncdfsi2" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (fix:SI (match_operand:DF 1 "register_operand" "r")))] "" --- 280,284 ---- (define_insn "fix_truncdfsi2" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (fix:SI (match_operand:DF 1 "register_operand" "r")))] "" *************** *** 286,290 **** (define_insn "fixuns_truncsfsi2" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))] "" --- 286,290 ---- (define_insn "fixuns_truncsfsi2" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))] "" *************** *** 292,296 **** (define_insn "fixuns_truncdfsi2" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))] "" --- 292,296 ---- (define_insn "fixuns_truncdfsi2" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))] "" *************** *** 311,315 **** (define_insn "floatsisf2" [(set (match_operand:SF 0 "register_operand" "=r") ! (float:SF (match_operand:SI 1 "gen_reg_operand" "r")))] "" "convert %0,%1,0,4,1,0") --- 311,315 ---- (define_insn "floatsisf2" [(set (match_operand:SF 0 "register_operand" "=r") ! (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "convert %0,%1,0,4,1,0") *************** *** 317,321 **** (define_insn "floatsidf2" [(set (match_operand:DF 0 "register_operand" "=r") ! (float:DF (match_operand:SI 1 "gen_reg_operand" "r")))] "" "convert %0,%1,0,4,2,0") --- 317,321 ---- (define_insn "floatsidf2" [(set (match_operand:DF 0 "register_operand" "=r") ! (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "convert %0,%1,0,4,2,0") *************** *** 323,327 **** (define_insn "floatunssisf2" [(set (match_operand:SF 0 "register_operand" "=r") ! (unsigned_float:SF (match_operand:SI 1 "gen_reg_operand" "r")))] "" "convert %0,%1,1,4,1,0") --- 323,327 ---- (define_insn "floatunssisf2" [(set (match_operand:SF 0 "register_operand" "=r") ! (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "convert %0,%1,1,4,1,0") *************** *** 329,333 **** (define_insn "floatunssidf2" [(set (match_operand:DF 0 "register_operand" "=r") ! (unsigned_float:DF (match_operand:SI 1 "gen_reg_operand" "r")))] "" "convert %0,%1,1,4,2,0") --- 329,333 ---- (define_insn "floatunssidf2" [(set (match_operand:DF 0 "register_operand" "=r") ! (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "convert %0,%1,1,4,2,0") *************** *** 335,341 **** ;; CPxxx, DEQ, DGT, DGE, FEQ, FGT, FGE (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (match_operator 3 "comparison_operator" ! [(match_operand:SI 1 "gen_reg_operand" "r") (match_operand:SI 2 "srcb_operand" "rI")]))] "" --- 335,341 ---- ;; CPxxx, DEQ, DGT, DGE, FEQ, FGT, FGE (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_operator 3 "comparison_operator" ! [(match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "srcb_operand" "rI")]))] "" *************** *** 343,347 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (match_operator 3 "fp_comparison_operator" [(match_operand:SF 1 "register_operand" "r") --- 343,347 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_operator 3 "fp_comparison_operator" [(match_operand:SF 1 "register_operand" "r") *************** *** 352,356 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (match_operator 3 "fp_comparison_operator" [(match_operand:DF 1 "register_operand" "r") --- 352,356 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_operator 3 "fp_comparison_operator" [(match_operand:DF 1 "register_operand" "r") *************** *** 404,413 **** (define_expand "divmodsi4" [(set (match_dup 4) ! (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "") (const_int 31))) ! (parallel [(set (match_operand:SI 0 "gen_reg_operand" "") (div:SI (match_dup 1) ! (match_operand:SI 2 "gen_reg_operand" ""))) ! (set (match_operand:SI 3 "gen_reg_operand" "") (mod:SI (match_dup 1) (match_dup 2))) --- 404,413 ---- (define_expand "divmodsi4" [(set (match_dup 4) ! (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") (const_int 31))) ! (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") (div:SI (match_dup 1) ! (match_operand:SI 2 "gpc_reg_operand" ""))) ! (set (match_operand:SI 3 "gpc_reg_operand" "") (mod:SI (match_dup 1) (match_dup 2))) *************** *** 420,426 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (div:SI (match_operand:SI 1 "gen_reg_operand" "r") ! (match_operand:SI 2 "gen_reg_operand" "r"))) (set (match_operand:SI 3 "register_operand" "=q") (mod:SI (match_dup 1) --- 420,426 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! (match_operand:SI 2 "gpc_reg_operand" "r"))) (set (match_operand:SI 3 "register_operand" "=q") (mod:SI (match_dup 1) *************** *** 434,441 **** ;; Similar to DIVIDE. (define_expand "udivmodsi4" ! [(parallel [(set (match_operand:SI 0 "gen_reg_operand" "") ! (udiv:SI (match_operand:SI 1 "gen_reg_operand" "") ! (match_operand:SI 2 "gen_reg_operand" ""))) ! (set (match_operand:SI 3 "gen_reg_operand" "") (umod:SI (match_dup 1) (match_dup 2))) --- 434,441 ---- ;; Similar to DIVIDE. (define_expand "udivmodsi4" ! [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") ! (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") ! (match_operand:SI 2 "gpc_reg_operand" ""))) ! (set (match_operand:SI 3 "gpc_reg_operand" "") (umod:SI (match_dup 1) (match_dup 2))) *************** *** 445,451 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (udiv:SI (match_operand:SI 1 "gen_reg_operand" "r") ! (match_operand:SI 2 "gen_reg_operand" "r"))) (set (match_operand:SI 3 "register_operand" "=q") (umod:SI (match_dup 1) --- 445,451 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! (match_operand:SI 2 "gpc_reg_operand" "r"))) (set (match_operand:SI 3 "register_operand" "=q") (umod:SI (match_dup 1) *************** *** 584,591 **** ;; EXBYTE (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI") (const_int -256)) ! (zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r") (const_int 8) (ashift:SI (match_operand:SI 3 "register_operand" "b") --- 584,591 ---- ;; EXBYTE (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI") (const_int -256)) ! (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") (const_int 8) (ashift:SI (match_operand:SI 3 "register_operand" "b") *************** *** 595,600 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r") (const_int 8) (ashift:SI (match_operand:SI 2 "register_operand" "b") --- 595,600 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 8) (ashift:SI (match_operand:SI 2 "register_operand" "b") *************** *** 604,611 **** (define_insn "" ! [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") (const_int 8) (match_operand:SI 1 "const_24_operand" "")) ! (zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r") (const_int 8) (ashift:SI (match_operand:SI 3 "register_operand" "b") --- 604,611 ---- (define_insn "" ! [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 8) (match_operand:SI 1 "const_24_operand" "")) ! (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") (const_int 8) (ashift:SI (match_operand:SI 3 "register_operand" "b") *************** *** 615,620 **** (define_expand "extzv" ! [(set (match_operand:SI 0 "gen_reg_operand" "") ! (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "") (match_operand:SI 2 "general_operand" "") (match_operand:SI 3 "general_operand" "")))] --- 615,620 ---- (define_expand "extzv" ! [(set (match_operand:SI 0 "gpc_reg_operand" "") ! (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "general_operand" "") (match_operand:SI 3 "general_operand" "")))] *************** *** 640,645 **** (define_expand "extv" ! [(set (match_operand:SI 0 "gen_reg_operand" "") ! (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "") (match_operand:SI 2 "general_operand" "") (match_operand:SI 3 "general_operand" "")))] --- 640,645 ---- (define_expand "extv" ! [(set (match_operand:SI 0 "gpc_reg_operand" "") ! (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "general_operand" "") (match_operand:SI 3 "general_operand" "")))] *************** *** 665,672 **** ;; EXHW (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI") (const_int -65536)) ! (zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r") (const_int 16) (ashift:SI (match_operand:SI 3 "register_operand" "b") --- 665,672 ---- ;; EXHW (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI") (const_int -65536)) ! (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") (const_int 16) (ashift:SI (match_operand:SI 3 "register_operand" "b") *************** *** 676,681 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r") (const_int 16) (ashift:SI (match_operand:SI 2 "register_operand" "b") --- 676,681 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 16) (ashift:SI (match_operand:SI 2 "register_operand" "b") *************** *** 685,692 **** (define_insn "" ! [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") (const_int 16) (match_operand:SI 1 "const_16_operand" "")) ! (zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r") (const_int 16) (ashift:SI (match_operand:SI 3 "register_operand" "b") --- 685,692 ---- (define_insn "" ! [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 16) (match_operand:SI 1 "const_16_operand" "")) ! (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") (const_int 16) (ashift:SI (match_operand:SI 3 "register_operand" "b") *************** *** 697,702 **** ;; EXHWS (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (sign_extract:SI (match_operand:SI 1 "gen_reg_operand" "r") (const_int 16) (ashift:SI (match_operand:SI 2 "register_operand" "b") --- 697,702 ---- ;; EXHWS (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (sign_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 16) (ashift:SI (match_operand:SI 2 "register_operand" "b") *************** *** 707,712 **** ;; EXTRACT (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") (reg:QI 178)))] "" --- 707,712 ---- ;; EXTRACT (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (reg:QI 178)))] "" *************** *** 715,721 **** (define_expand "rotlsi3" [(set (reg:QI 178) ! (match_operand: SI 2 "gen_reg_or_immediate_operand" "")) ! (set (match_operand:SI 0 "gen_reg_operand" "") ! (rotate:SI (match_operand:SI 1 "gen_reg_operand" "") (reg:QI 178)))] "" --- 715,721 ---- (define_expand "rotlsi3" [(set (reg:QI 178) ! (match_operand: SI 2 "gpc_reg_or_immediate_operand" "")) ! (set (match_operand:SI 0 "gpc_reg_operand" "") ! (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") (reg:QI 178)))] "" *************** *** 894,898 **** ;; INBYTE (define_insn "" ! [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") (const_int 8) (ashift:SI (match_operand:SI 2 "register_operand" "b") --- 894,898 ---- ;; INBYTE (define_insn "" ! [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 8) (ashift:SI (match_operand:SI 2 "register_operand" "b") *************** *** 903,911 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (ior:SI (and:SI (not:SI (ashift:SI (const_int 255) (ashift:SI (match_operand:SI 3 "register_operand" "b") (const_int 3)))) ! (match_operand:SI 1 "gen_reg_operand" "r")) (ashift:SI (and:SI (match_operand:SI 2 "srcb_operand" "rI") (const_int 255)) --- 903,911 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (not:SI (ashift:SI (const_int 255) (ashift:SI (match_operand:SI 3 "register_operand" "b") (const_int 3)))) ! (match_operand:SI 1 "gpc_reg_operand" "r")) (ashift:SI (and:SI (match_operand:SI 2 "srcb_operand" "rI") (const_int 255)) *************** *** 915,923 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (ior:SI (and:SI (not:SI (ashift:SI (const_int 255) (ashift:SI (match_operand:SI 3 "register_operand" "b") (const_int 3)))) ! (match_operand:SI 1 "gen_reg_operand" "r")) (ashift:SI (match_operand:SI 2 "srcb_operand" "rI") (match_operand:SI 4 "const_24_operand" ""))))] --- 915,923 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (not:SI (ashift:SI (const_int 255) (ashift:SI (match_operand:SI 3 "register_operand" "b") (const_int 3)))) ! (match_operand:SI 1 "gpc_reg_operand" "r")) (ashift:SI (match_operand:SI 2 "srcb_operand" "rI") (match_operand:SI 4 "const_24_operand" ""))))] *************** *** 927,931 **** ;; INHW (define_insn "" ! [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") (const_int 16) (ashift:SI (match_operand:SI 2 "register_operand" "b") --- 927,931 ---- ;; INHW (define_insn "" ! [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 16) (ashift:SI (match_operand:SI 2 "register_operand" "b") *************** *** 936,944 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (ior:SI (and:SI (not:SI (ashift:SI (const_int 65535) (ashift:SI (match_operand:SI 3 "register_operand" "b") (const_int 3)))) ! (match_operand:SI 1 "gen_reg_operand" "r")) (ashift:SI (and:SI (match_operand:SI 2 "srcb_operand" "rI") (const_int 65535)) --- 936,944 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (not:SI (ashift:SI (const_int 65535) (ashift:SI (match_operand:SI 3 "register_operand" "b") (const_int 3)))) ! (match_operand:SI 1 "gpc_reg_operand" "r")) (ashift:SI (and:SI (match_operand:SI 2 "srcb_operand" "rI") (const_int 65535)) *************** *** 948,956 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (ior:SI (and:SI (not:SI (ashift:SI (const_int 65535) (ashift:SI (match_operand:SI 3 "register_operand" "b") (const_int 3)))) ! (match_operand:SI 1 "gen_reg_operand" "r")) (ashift:SI (match_operand:SI 2 "srcb_operand" "rI") (match_operand:SI 4 "const_24_operand" ""))))] --- 948,956 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (not:SI (ashift:SI (const_int 65535) (ashift:SI (match_operand:SI 3 "register_operand" "b") (const_int 3)))) ! (match_operand:SI 1 "gpc_reg_operand" "r")) (ashift:SI (match_operand:SI 2 "srcb_operand" "rI") (match_operand:SI 4 "const_24_operand" ""))))] *************** *** 959,963 **** (define_expand "insv" ! [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "") (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" "")) --- 959,963 ---- (define_expand "insv" ! [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "") (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" "")) *************** *** 985,990 **** ;; LOAD (also used by move insn). (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (mem:SI (and:SI (match_operand:SI 1 "gen_reg_operand" "r") (const_int -4)))) (set (reg:SI 177) --- 985,990 ---- ;; LOAD (also used by move insn). (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int -4)))) (set (reg:SI 177) *************** *** 996,1001 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (mem:SI (and:SI (match_operand:SI 1 "gen_reg_operand" "r") (const_int -4)))) (set (reg:SI 177) --- 996,1001 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int -4)))) (set (reg:SI 177) *************** *** 1007,1011 **** (define_insn "" ! [(set (match_operand 0 "gen_reg_operand" "=r") (match_operator 2 "extend_operator" [(match_operand 1 "memory_operand" "m")]))] --- 1007,1011 ---- (define_insn "" ! [(set (match_operand 0 "gpc_reg_operand" "=r") (match_operator 2 "extend_operator" [(match_operand 1 "memory_operand" "m")]))] *************** *** 1060,1064 **** ;; Indicate that CR is used and is then clobbered. (define_insn "" ! [(set (match_operand 0 "gen_reg_operand" "=r") (match_operand 1 "memory_operand" "m")) (use (reg:SI 179)) --- 1060,1064 ---- ;; Indicate that CR is used and is then clobbered. (define_insn "" ! [(set (match_operand 0 "gpc_reg_operand" "=r") (match_operand 1 "memory_operand" "m")) (use (reg:SI 179)) *************** *** 1071,1075 **** (define_insn "" ! [(set (match_operand 0 "gen_reg_operand" "=&r") (match_operand 1 "memory_operand" "m")) (use (reg:SI 179)) --- 1071,1075 ---- (define_insn "" ! [(set (match_operand 0 "gpc_reg_operand" "=&r") (match_operand 1 "memory_operand" "m")) (use (reg:SI 179)) *************** *** 1083,1087 **** (define_insn "" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "gen_reg_operand" "=r") (match_operand:SI 2 "memory_operand" "m")) (use (reg:SI 179)) --- 1083,1087 ---- (define_insn "" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "gpc_reg_operand" "=r") (match_operand:SI 2 "memory_operand" "m")) (use (reg:SI 179)) *************** *** 1093,1097 **** (define_insn "" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "gen_reg_operand" "=&r") (match_operand:SI 2 "memory_operand" "m")) (use (reg:SI 179)) --- 1093,1097 ---- (define_insn "" [(match_parallel 0 "load_multiple_operation" ! [(set (match_operand:SI 1 "gpc_reg_operand" "=&r") (match_operand:SI 2 "memory_operand" "m")) (use (reg:SI 179)) *************** *** 1104,1108 **** (define_insn "" [(set (match_operand:SI 0 "spec_reg_operand" "=*h,*h") ! (and:SI (match_operand:SI 1 "gen_reg_or_immediate_operand" "r,i") (match_operand:SI 2 "const_int_operand" "n,n")))] "masks_bits_for_special (operands[0], operands[2])" --- 1104,1108 ---- (define_insn "" [(set (match_operand:SI 0 "spec_reg_operand" "=*h,*h") ! (and:SI (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i") (match_operand:SI 2 "const_int_operand" "n,n")))] "masks_bits_for_special (operands[0], operands[2])" *************** *** 1113,1119 **** ;; MULTIPLY, MULTM, MULTMU (define_insn "mulsi3" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (mult:SI (match_operand:SI 1 "gen_reg_operand" "%r") ! (match_operand:SI 2 "gen_reg_operand" "r")))] "" "multiply %0,%1,%2") --- 1113,1119 ---- ;; MULTIPLY, MULTM, MULTMU (define_insn "mulsi3" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") ! (match_operand:SI 2 "gpc_reg_operand" "r")))] "" "multiply %0,%1,%2") *************** *** 1120,1128 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (subreg:SI (mult:DI ! (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "%r")) ! (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))) 0))] "" "multm %0,%1,%2") --- 1120,1128 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (subreg:SI (mult:DI ! (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) ! (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))] "" "multm %0,%1,%2") *************** *** 1129,1137 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") (subreg:SI (mult:DI ! (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "%r")) ! (zero_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))) 0))] "" "multmu %0,%1,%2") --- 1129,1137 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (subreg:SI (mult:DI ! (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) ! (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))] "" "multmu %0,%1,%2") *************** *** 1138,1144 **** (define_insn "mulsidi3" ! [(set (match_operand:DI 0 "gen_reg_operand" "=r") ! (mult:DI (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "r")) ! (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))))] "" "multiply %L0,%1,%2\;multm %0,%1,%2" --- 1138,1144 ---- (define_insn "mulsidi3" ! [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) ! (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] "" "multiply %L0,%1,%2\;multm %0,%1,%2" *************** *** 1146,1152 **** (define_split ! [(set (match_operand:DI 0 "gen_reg_operand" "") ! (mult:DI (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "")) ! (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" ""))))] "reload_completed" [(set (match_dup 3) --- 1146,1152 ---- (define_split ! [(set (match_operand:DI 0 "gpc_reg_operand" "") ! (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) ! (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] "reload_completed" [(set (match_dup 3) *************** *** 1161,1167 **** (define_insn "umulsidi3" ! [(set (match_operand:DI 0 "gen_reg_operand" "=r") ! (mult:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r")) ! (zero_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))))] "" "multiplu %L0,%1,%2\;multmu %0,%1,%2" --- 1161,1167 ---- (define_insn "umulsidi3" ! [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) ! (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] "" "multiplu %L0,%1,%2\;multmu %0,%1,%2" *************** *** 1169,1175 **** (define_split ! [(set (match_operand:DI 0 "gen_reg_operand" "") ! (mult:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "")) ! (zero_extend:DI (match_operand:SI 2 "gen_reg_operand" ""))))] "reload_completed" [(set (match_dup 3) --- 1169,1175 ---- (define_split ! [(set (match_operand:DI 0 "gpc_reg_operand" "") ! (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) ! (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] "reload_completed" [(set (match_dup 3) *************** *** 1184,1189 **** ;; NAND (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "%r")) (not:SI (match_operand:SI 2 "srcb_operand" "rI"))))] "" --- 1184,1189 ---- ;; NAND (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) (not:SI (match_operand:SI 2 "srcb_operand" "rI"))))] "" *************** *** 1191,1196 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) (match_operand:SI 2 "const_int_operand" "K")))] "((unsigned) ~ INTVAL (operands[2])) < 256" --- 1191,1196 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (match_operand:SI 2 "const_int_operand" "K")))] "((unsigned) ~ INTVAL (operands[2])) < 256" *************** *** 1199,1204 **** ;; NOR (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "%r")) (not:SI (match_operand:SI 2 "srcb_operand" "rI"))))] "" --- 1199,1204 ---- ;; NOR (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) (not:SI (match_operand:SI 2 "srcb_operand" "rI"))))] "" *************** *** 1206,1211 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) (match_operand:SI 2 "const_int_operand" "K")))] "((unsigned) ~ INTVAL (operands[2])) < 256" --- 1206,1211 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (match_operand:SI 2 "const_int_operand" "K")))] "((unsigned) ~ INTVAL (operands[2])) < 256" *************** *** 1213,1218 **** (define_insn "one_cmplsi2" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (not:SI (match_operand:SI 1 "gen_reg_operand" "r")))] "" "nor %0,%1,0") --- 1213,1218 ---- (define_insn "one_cmplsi2" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "nor %0,%1,0") *************** *** 1220,1225 **** ;; OR/ORN (define_expand "iorsi3" ! [(set (match_operand:SI 0 "gen_reg_operand" "") ! (ior:SI (match_operand:SI 1 "gen_reg_operand" "") (match_operand:SI 2 "srcb_operand" "")))] "" --- 1220,1225 ---- ;; OR/ORN (define_expand "iorsi3" ! [(set (match_operand:SI 0 "gpc_reg_operand" "") ! (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "srcb_operand" "")))] "" *************** *** 1227,1232 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (ior:SI (match_operand:SI 1 "gen_reg_operand" "%r") (match_operand:SI 2 "srcb_operand" "rI")))] "! TARGET_29050" --- 1227,1232 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "srcb_operand" "rI")))] "! TARGET_29050" *************** *** 1234,1239 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") ! (ior:SI (match_operand:SI 1 "gen_reg_operand" "%r,r") (match_operand:SI 2 "srcb_operand" "rI,K")))] "TARGET_29050" --- 1234,1239 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") (match_operand:SI 2 "srcb_operand" "rI,K")))] "TARGET_29050" *************** *** 1250,1255 **** (define_insn "ashlsi3" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r") (match_operand:QI 2 "srcb_operand" "rn")))] "" --- 1250,1255 ---- (define_insn "ashlsi3" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:QI 2 "srcb_operand" "rn")))] "" *************** *** 1258,1263 **** ;; SRA (define_insn "ashrsi3" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") (match_operand:QI 2 "srcb_operand" "rn")))] "" --- 1258,1263 ---- ;; SRA (define_insn "ashrsi3" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:QI 2 "srcb_operand" "rn")))] "" *************** *** 1266,1271 **** ;; SRL (define_insn "lshrsi3" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") (match_operand:QI 2 "srcb_operand" "rn")))] "" --- 1266,1271 ---- ;; SRL (define_insn "lshrsi3" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:QI 2 "srcb_operand" "rn")))] "" *************** *** 1277,1283 **** ;; stores on systems with DW not set. (define_insn "" ! [(set (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "r") (const_int -4))) ! (match_operand:SI 1 "gen_reg_operand" "r"))] "! TARGET_DW_ENABLE" "store 0,1,%1,%0" --- 1277,1283 ---- ;; stores on systems with DW not set. (define_insn "" ! [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r") (const_int -4))) ! (match_operand:SI 1 "gpc_reg_operand" "r"))] "! TARGET_DW_ENABLE" "store 0,1,%1,%0" *************** *** 1285,1291 **** (define_insn "" ! [(set (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "r") (const_int -3))) ! (match_operand:SI 1 "gen_reg_operand" "r"))] "! TARGET_DW_ENABLE" "store 0,2,%1,%0" --- 1285,1291 ---- (define_insn "" ! [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r") (const_int -3))) ! (match_operand:SI 1 "gpc_reg_operand" "r"))] "! TARGET_DW_ENABLE" "store 0,2,%1,%0" *************** *** 1397,1401 **** (define_insn "" [(set (match_operand 0 "memory_operand" "=m") ! (match_operand 1 "gen_reg_operand" "r")) (clobber (reg:SI 179))] "!TARGET_NO_STOREM_BUG --- 1397,1401 ---- (define_insn "" [(set (match_operand 0 "memory_operand" "=m") ! (match_operand 1 "gpc_reg_operand" "r")) (clobber (reg:SI 179))] "!TARGET_NO_STOREM_BUG *************** *** 1408,1412 **** [(match_parallel 0 "store_multiple_operation" [(set (match_operand:SI 1 "memory_operand" "=m") ! (match_operand:SI 2 "gen_reg_operand" "r")) (clobber (reg:SI 179))])] "!TARGET_NO_STOREM_BUG" --- 1408,1412 ---- [(match_parallel 0 "store_multiple_operation" [(set (match_operand:SI 1 "memory_operand" "=m") ! (match_operand:SI 2 "gpc_reg_operand" "r")) (clobber (reg:SI 179))])] "!TARGET_NO_STOREM_BUG" *************** *** 1416,1420 **** (define_insn "" [(set (match_operand 0 "memory_operand" "=m") ! (match_operand 1 "gen_reg_operand" "r")) (use (reg:SI 179)) (clobber (reg:SI 179))] --- 1416,1420 ---- (define_insn "" [(set (match_operand 0 "memory_operand" "=m") ! (match_operand 1 "gpc_reg_operand" "r")) (use (reg:SI 179)) (clobber (reg:SI 179))] *************** *** 1428,1432 **** [(match_parallel 0 "store_multiple_operation" [(set (match_operand:SI 1 "memory_operand" "=m") ! (match_operand:SI 2 "gen_reg_operand" "r")) (use (reg:SI 179)) (clobber (reg:SI 179))])] --- 1428,1432 ---- [(match_parallel 0 "store_multiple_operation" [(set (match_operand:SI 1 "memory_operand" "=m") ! (match_operand:SI 2 "gpc_reg_operand" "r")) (use (reg:SI 179)) (clobber (reg:SI 179))])] *************** *** 1440,1444 **** ;; constants (can't usually occur anyway). (define_expand "subsi3" ! [(set (match_operand:SI 0 "gen_reg_operand" "") (minus:SI (match_operand:SI 1 "srcb_operand" "") (match_operand:SI 2 "srcb_operand" "")))] --- 1440,1444 ---- ;; constants (can't usually occur anyway). (define_expand "subsi3" ! [(set (match_operand:SI 0 "gpc_reg_operand" "") (minus:SI (match_operand:SI 1 "srcb_operand" "") (match_operand:SI 2 "srcb_operand" "")))] *************** *** 1452,1456 **** (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") (minus:SI (match_operand:SI 1 "srcb_operand" "r,I") (match_operand:SI 2 "srcb_operand" "rI,r")))] --- 1452,1456 ---- (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (minus:SI (match_operand:SI 1 "srcb_operand" "r,I") (match_operand:SI 2 "srcb_operand" "rI,r")))] *************** *** 1462,1468 **** (define_insn "subdi3" ! [(set (match_operand:DI 0 "gen_reg_operand" "=r") ! (minus:DI (match_operand:DI 1 "gen_reg_operand" "r") ! (match_operand:DI 2 "gen_reg_operand" "r")))] "" "sub %L0,%L1,%L2\;subc %0,%1,%2" --- 1462,1468 ---- (define_insn "subdi3" ! [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") ! (match_operand:DI 2 "gpc_reg_operand" "r")))] "" "sub %L0,%L1,%L2\;subc %0,%1,%2" *************** *** 1471,1476 **** ;; SUBR (also used above in SUB) (define_insn "negdi2" ! [(set (match_operand:DI 0 "gen_reg_operand" "=r") ! (neg:DI (match_operand:DI 1 "gen_reg_operand" "r")))] "" "subr %L0,%L1,0\;subrc %0,%1,0" --- 1471,1476 ---- ;; SUBR (also used above in SUB) (define_insn "negdi2" ! [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] "" "subr %L0,%L1,0\;subrc %0,%1,0" *************** *** 1478,1483 **** (define_insn "negsi2" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (neg:SI (match_operand:SI 1 "gen_reg_operand" "r")))] "" "subr %0,%1,0") --- 1478,1483 ---- (define_insn "negsi2" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "subr %0,%1,0") *************** *** 1485,1490 **** ;; XNOR (define_insn "" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r") (match_operand:SI 2 "srcb_operand" "rI"))))] "" --- 1485,1490 ---- ;; XNOR (define_insn "" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "srcb_operand" "rI"))))] "" *************** *** 1493,1498 **** ;; XOR (define_insn "xorsi3" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r") (match_operand:SI 2 "srcb_operand" "rI")))] "" --- 1493,1498 ---- ;; XOR (define_insn "xorsi3" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "srcb_operand" "rI")))] "" *************** *** 1568,1573 **** ;; Sign extend and truncation operations. (define_insn "zero_extendqihi2" ! [(set (match_operand:HI 0 "gen_reg_operand" "=r") ! (zero_extend:HI (match_operand:QI 1 "gen_reg_operand" "r")))] "" "and %0,%1,255") --- 1568,1573 ---- ;; Sign extend and truncation operations. (define_insn "zero_extendqihi2" ! [(set (match_operand:HI 0 "gpc_reg_operand" "=r") ! (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] "" "and %0,%1,255") *************** *** 1574,1579 **** (define_insn "zero_extendqisi2" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r")))] "" "and %0,%1,255") --- 1574,1579 ---- (define_insn "zero_extendqisi2" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] "" "and %0,%1,255") *************** *** 1580,1585 **** (define_insn "zero_extendhisi2" ! [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "0")))] "" "consth %0,0") --- 1580,1585 ---- (define_insn "zero_extendhisi2" ! [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")))] "" "consth %0,0") *************** *** 1587,1593 **** (define_expand "extendqihi2" [(set (match_dup 2) ! (ashift:SI (match_operand:QI 1 "gen_reg_operand" "") (const_int 24))) ! (set (match_operand:HI 0 "gen_reg_operand" "") (ashiftrt:SI (match_dup 2) (const_int 24)))] --- 1587,1593 ---- (define_expand "extendqihi2" [(set (match_dup 2) ! (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") (const_int 24))) ! (set (match_operand:HI 0 "gpc_reg_operand" "") (ashiftrt:SI (match_dup 2) (const_int 24)))] *************** *** 1600,1606 **** (define_expand "extendqisi2" [(set (match_dup 2) ! (ashift:SI (match_operand:QI 1 "gen_reg_operand" "") (const_int 24))) ! (set (match_operand:SI 0 "gen_reg_operand" "") (ashiftrt:SI (match_dup 2) (const_int 24)))] --- 1600,1606 ---- (define_expand "extendqisi2" [(set (match_dup 2) ! (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") (const_int 24))) ! (set (match_operand:SI 0 "gpc_reg_operand" "") (ashiftrt:SI (match_dup 2) (const_int 24)))] *************** *** 1612,1618 **** (define_expand "extendhisi2" [(set (match_dup 2) ! (ashift:SI (match_operand:HI 1 "gen_reg_operand" "") (const_int 16))) ! (set (match_operand:SI 0 "gen_reg_operand" "") (ashiftrt:SI (match_dup 2) (const_int 16)))] --- 1612,1618 ---- (define_expand "extendhisi2" [(set (match_dup 2) ! (ashift:SI (match_operand:HI 1 "gpc_reg_operand" "") (const_int 16))) ! (set (match_operand:SI 0 "gpc_reg_operand" "") (ashiftrt:SI (match_dup 2) (const_int 16)))] *************** *** 1633,1637 **** " { ! if (GET_CODE (operands[0]) == MEM && ! gen_reg_operand (operands[1], SImode)) operands[1] = copy_to_mode_reg (SImode, operands[1]); else if (spec_reg_operand (operands[0], SImode) --- 1633,1637 ---- " { ! if (GET_CODE (operands[0]) == MEM && ! gpc_reg_operand (operands[1], SImode)) operands[1] = copy_to_mode_reg (SImode, operands[1]); else if (spec_reg_operand (operands[0], SImode) *************** *** 1642,1646 **** (define_split ! [(set (match_operand:SI 0 "gen_reg_operand" "") (match_operand:SI 1 "long_const_operand" ""))] "" --- 1642,1646 ---- (define_split ! [(set (match_operand:SI 0 "gpc_reg_operand" "") (match_operand:SI 1 "long_const_operand" ""))] "" *************** *** 1660,1664 **** (define_expand "loadhi" [(parallel [(set (match_dup 2) ! (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "") (const_int -4)))) (set (reg:SI 177) --- 1660,1664 ---- (define_expand "loadhi" [(parallel [(set (match_dup 2) ! (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "") (const_int -4)))) (set (reg:SI 177) *************** *** 1665,1669 **** (and:SI (match_dup 0) (const_int 2)))]) ! (set (match_operand:HI 1 "gen_reg_operand" "") (zero_extract:SI (match_dup 2) (const_int 16) --- 1665,1669 ---- (and:SI (match_dup 0) (const_int 2)))]) ! (set (match_operand:HI 1 "gpc_reg_operand" "") (zero_extract:SI (match_dup 2) (const_int 16) *************** *** 1682,1686 **** (define_expand "storehinhww" [(parallel [(set (match_dup 2) ! (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "") (const_int -4)))) (set (reg:SI 177) --- 1682,1686 ---- (define_expand "storehinhww" [(parallel [(set (match_dup 2) ! (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "") (const_int -4)))) (set (reg:SI 177) *************** *** 1691,1695 **** (ashift:SI (reg:SI 177) (const_int 3))) ! (match_operand:HI 1 "gen_reg_operand" "")) (set (mem:SI (match_dup 0)) (match_dup 2))] --- 1691,1695 ---- (ashift:SI (reg:SI 177) (const_int 3))) ! (match_operand:HI 1 "gpc_reg_operand" "")) (set (mem:SI (match_dup 0)) (match_dup 2))] *************** *** 1706,1710 **** (define_expand "storehihww" [(set (reg:SI 177) ! (and:SI (match_operand:SI 0 "gen_reg_operand" "") (const_int 3))) (set (match_dup 2) --- 1706,1710 ---- (define_expand "storehihww" [(set (reg:SI 177) ! (and:SI (match_operand:SI 0 "gpc_reg_operand" "") (const_int 3))) (set (match_dup 2) *************** *** 1712,1716 **** (ashift:SI (reg:SI 177) (const_int 3)))) ! (match_operand:HI 1 "gen_reg_operand" "")) (ashift:SI (and:SI (match_dup 1) (const_int 65535)) --- 1712,1716 ---- (ashift:SI (reg:SI 177) (const_int 3)))) ! (match_operand:HI 1 "gpc_reg_operand" "")) (ashift:SI (and:SI (match_dup 1) (const_int 65535)) *************** *** 1737,1741 **** { if (GET_CODE (operands[0]) == MEM) { ! if (! gen_reg_operand (operands[1], HImode)) operands[1] = copy_to_mode_reg (HImode, operands[1]); if (! TARGET_DW_ENABLE) --- 1737,1741 ---- { if (GET_CODE (operands[0]) == MEM) { ! if (! gpc_reg_operand (operands[1], HImode)) operands[1] = copy_to_mode_reg (HImode, operands[1]); if (! TARGET_DW_ENABLE) *************** *** 1761,1765 **** (define_expand "loadqi" [(parallel [(set (match_dup 2) ! (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "") (const_int -4)))) (set (reg:SI 177) --- 1761,1765 ---- (define_expand "loadqi" [(parallel [(set (match_dup 2) ! (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "") (const_int -4)))) (set (reg:SI 177) *************** *** 1766,1770 **** (and:SI (match_dup 0) (const_int 3)))]) ! (set (match_operand:QI 1 "gen_reg_operand" "") (zero_extract:SI (match_dup 2) (const_int 8) --- 1766,1770 ---- (and:SI (match_dup 0) (const_int 3)))]) ! (set (match_operand:QI 1 "gpc_reg_operand" "") (zero_extract:SI (match_dup 2) (const_int 8) *************** *** 1783,1787 **** (define_expand "storeqinhww" [(parallel [(set (match_dup 2) ! (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "") (const_int -4)))) (set (reg:SI 177) --- 1783,1787 ---- (define_expand "storeqinhww" [(parallel [(set (match_dup 2) ! (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "") (const_int -4)))) (set (reg:SI 177) *************** *** 1792,1796 **** (ashift:SI (reg:SI 177) (const_int 3))) ! (match_operand:QI 1 "gen_reg_operand" "")) (set (mem:SI (match_dup 0)) (match_dup 2))] --- 1792,1796 ---- (ashift:SI (reg:SI 177) (const_int 3))) ! (match_operand:QI 1 "gpc_reg_operand" "")) (set (mem:SI (match_dup 0)) (match_dup 2))] *************** *** 1807,1811 **** (define_expand "storeqihww" [(set (reg:SI 177) ! (and:SI (match_operand:SI 0 "gen_reg_operand" "") (const_int 3))) (set (match_dup 2) --- 1807,1811 ---- (define_expand "storeqihww" [(set (reg:SI 177) ! (and:SI (match_operand:SI 0 "gpc_reg_operand" "") (const_int 3))) (set (match_dup 2) *************** *** 1813,1817 **** (ashift:SI (reg:SI 177) (const_int 3)))) ! (match_operand:HI 1 "gen_reg_operand" "")) (ashift:SI (and:SI (match_dup 1) (const_int 255)) --- 1813,1817 ---- (ashift:SI (reg:SI 177) (const_int 3)))) ! (match_operand:HI 1 "gpc_reg_operand" "")) (ashift:SI (and:SI (match_dup 1) (const_int 255)) *************** *** 1838,1842 **** { if (GET_CODE (operands[0]) == MEM) { ! if (! gen_reg_operand (operands[1], QImode)) operands[1] = copy_to_mode_reg (QImode, operands[1]); if (! TARGET_DW_ENABLE) --- 1838,1842 ---- { if (GET_CODE (operands[0]) == MEM) { ! if (! gpc_reg_operand (operands[1], QImode)) operands[1] = copy_to_mode_reg (QImode, operands[1]); if (! TARGET_DW_ENABLE) *************** *** 1866,1871 **** [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m") (match_operand:SF 1 "in_operand" "r,E,F,m,r"))] ! "(gen_reg_operand (operands[0], SFmode) ! || gen_reg_operand (operands[1], SFmode)) && ! TARGET_29050" "@ --- 1866,1871 ---- [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m") (match_operand:SF 1 "in_operand" "r,E,F,m,r"))] ! "(gpc_reg_operand (operands[0], SFmode) ! || gpc_reg_operand (operands[1], SFmode)) && ! TARGET_29050" "@ *************** *** 1880,1885 **** [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m,*a,r") (match_operand:SF 1 "in_operand" "r,E,F,m,r,r,*a"))] ! "(gen_reg_operand (operands[0], SFmode) ! || gen_reg_operand (operands[1], SFmode)) && TARGET_29050" "@ --- 1880,1885 ---- [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m,*a,r") (match_operand:SF 1 "in_operand" "r,E,F,m,r,r,*a"))] ! "(gpc_reg_operand (operands[0], SFmode) ! || gpc_reg_operand (operands[1], SFmode)) && TARGET_29050" "@ *************** *** 1912,1917 **** (match_operand:DF 1 "in_operand" "rE,F,m,r")) (clobber (reg:SI 179))] ! "(gen_reg_operand (operands[0], DFmode) ! || gen_reg_operand (operands[1], DFmode)) && ! TARGET_29050" "@ --- 1912,1917 ---- (match_operand:DF 1 "in_operand" "rE,F,m,r")) (clobber (reg:SI 179))] ! "(gpc_reg_operand (operands[0], DFmode) ! || gpc_reg_operand (operands[1], DFmode)) && ! TARGET_29050" "@ *************** *** 1926,1931 **** (match_operand:DF 1 "in_operand" "rE,F,m,r,r,*a")) (clobber (reg:SI 179))] ! "(gen_reg_operand (operands[0], DFmode) ! || gen_reg_operand (operands[1], DFmode)) && TARGET_29050" "@ --- 1926,1931 ---- (match_operand:DF 1 "in_operand" "rE,F,m,r,r,*a")) (clobber (reg:SI 179))] ! "(gpc_reg_operand (operands[0], DFmode) ! || gpc_reg_operand (operands[1], DFmode)) && TARGET_29050" "@ *************** *** 1946,1951 **** ;; second operand. (define_split ! [(set (match_operand:DF 0 "gen_reg_operand" "") ! (match_operand:DF 1 "gen_reg_or_float_constant_operand" "")) (clobber (reg:SI 179))] "reload_completed" --- 1946,1951 ---- ;; second operand. (define_split ! [(set (match_operand:DF 0 "gpc_reg_operand" "") ! (match_operand:DF 1 "gpc_reg_or_float_constant_operand" "")) (clobber (reg:SI 179))] "reload_completed" *************** *** 1993,1998 **** (match_operand:DI 1 "in_operand" "rn,m,r")) (clobber (reg:SI 179))] ! "(gen_reg_operand (operands[0], DImode) ! || gen_reg_operand (operands[1], DImode)) && ! TARGET_29050" "@ --- 1993,1998 ---- (match_operand:DI 1 "in_operand" "rn,m,r")) (clobber (reg:SI 179))] ! "(gpc_reg_operand (operands[0], DImode) ! || gpc_reg_operand (operands[1], DImode)) && ! TARGET_29050" "@ *************** *** 2006,2011 **** (match_operand:DI 1 "in_operand" "rn,m,r")) (clobber (reg:SI 179))] ! "(gen_reg_operand (operands[0], DImode) ! || gen_reg_operand (operands[1], DImode)) && TARGET_29050" "@ --- 2006,2011 ---- (match_operand:DI 1 "in_operand" "rn,m,r")) (clobber (reg:SI 179))] ! "(gpc_reg_operand (operands[0], DImode) ! || gpc_reg_operand (operands[1], DImode)) && TARGET_29050" "@ *************** *** 2016,2021 **** (define_split ! [(set (match_operand:DI 0 "gen_reg_operand" "") ! (match_operand:DI 1 "gen_reg_or_integer_constant_operand" "")) (clobber (reg:SI 179))] "reload_completed" --- 2016,2021 ---- (define_split ! [(set (match_operand:DI 0 "gpc_reg_operand" "") ! (match_operand:DI 1 "gpc_reg_or_integer_constant_operand" "")) (clobber (reg:SI 179))] "reload_completed" *************** *** 2059,2064 **** (match_operand:TI 1 "in_operand" "r,m,r")) (clobber (reg:SI 179))] ! "(gen_reg_operand (operands[0], TImode) ! || gen_reg_operand (operands[1], TImode)) && ! TARGET_29050" "@ --- 2059,2064 ---- (match_operand:TI 1 "in_operand" "r,m,r")) (clobber (reg:SI 179))] ! "(gpc_reg_operand (operands[0], TImode) ! || gpc_reg_operand (operands[1], TImode)) && ! TARGET_29050" "@ *************** *** 2072,2077 **** (match_operand:TI 1 "in_operand" "r,m,r")) (clobber (reg:SI 179))] ! "(gen_reg_operand (operands[0], TImode) ! || gen_reg_operand (operands[1], TImode)) && TARGET_29050" "@ --- 2072,2077 ---- (match_operand:TI 1 "in_operand" "r,m,r")) (clobber (reg:SI 179))] ! "(gpc_reg_operand (operands[0], TImode) ! || gpc_reg_operand (operands[1], TImode)) && TARGET_29050" "@ *************** *** 2082,2087 **** (define_split ! [(set (match_operand:TI 0 "gen_reg_operand" "") ! (match_operand:TI 1 "gen_reg_operand" "")) (clobber (reg:SI 179))] "reload_completed" --- 2082,2087 ---- (define_split ! [(set (match_operand:TI 0 "gpc_reg_operand" "") ! (match_operand:TI 1 "gpc_reg_operand" "")) (clobber (reg:SI 179))] "reload_completed" *************** *** 2133,2138 **** [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h") (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))] ! "(gen_reg_operand (operands[0], SImode) ! || gen_reg_operand (operands[1], SImode) || (spec_reg_operand (operands[0], SImode) && cint_16_operand (operands[1], SImode))) --- 2133,2138 ---- [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h") (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))] ! "(gpc_reg_operand (operands[0], SImode) ! || gpc_reg_operand (operands[1], SImode) || (spec_reg_operand (operands[0], SImode) && cint_16_operand (operands[1], SImode))) *************** *** 2154,2159 **** [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h") (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))] ! "(gen_reg_operand (operands[0], SImode) ! || gen_reg_operand (operands[1], SImode) || (spec_reg_operand (operands[0], SImode) && cint_16_operand (operands[1], SImode))) --- 2154,2159 ---- [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h") (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))] ! "(gpc_reg_operand (operands[0], SImode) ! || gpc_reg_operand (operands[1], SImode) || (spec_reg_operand (operands[0], SImode) && cint_16_operand (operands[1], SImode))) *************** *** 2175,2180 **** [(set (match_operand:HI 0 "out_operand" "=r,r,r,m,r,*h,*h") (match_operand:HI 1 "in_operand" "r,i,m,r,*h,r,i"))] ! "gen_reg_operand (operands[0], HImode) ! || gen_reg_operand (operands[1], HImode)" "@ sll %0,%1,0 --- 2175,2180 ---- [(set (match_operand:HI 0 "out_operand" "=r,r,r,m,r,*h,*h") (match_operand:HI 1 "in_operand" "r,i,m,r,*h,r,i"))] ! "gpc_reg_operand (operands[0], HImode) ! || gpc_reg_operand (operands[1], HImode)" "@ sll %0,%1,0 *************** *** 2190,2195 **** [(set (match_operand:QI 0 "out_operand" "=r,r,r,m,r,*h,*h") (match_operand:QI 1 "in_operand" "r,i,m,r,*h,r,i"))] ! "gen_reg_operand (operands[0], QImode) ! || gen_reg_operand (operands[1], QImode)" "@ sll %0,%1,0 --- 2190,2195 ---- [(set (match_operand:QI 0 "out_operand" "=r,r,r,m,r,*h,*h") (match_operand:QI 1 "in_operand" "r,i,m,r,*h,r,i"))] ! "gpc_reg_operand (operands[0], QImode) ! || gpc_reg_operand (operands[1], QImode)" "@ sll %0,%1,0 *************** *** 2258,2262 **** (define_expand "cmpsi" [(set (cc0) ! (compare (match_operand:SI 0 "gen_reg_operand" "") (match_operand:SI 1 "srcb_operand" "")))] "" --- 2258,2262 ---- (define_expand "cmpsi" [(set (cc0) ! (compare (match_operand:SI 0 "gpc_reg_operand" "") (match_operand:SI 1 "srcb_operand" "")))] "" *************** *** 2271,2276 **** (define_expand "cmpsf" [(set (cc0) ! (compare (match_operand:SF 0 "gen_reg_operand" "") ! (match_operand:SF 1 "gen_reg_operand" "")))] "" " --- 2271,2276 ---- (define_expand "cmpsf" [(set (cc0) ! (compare (match_operand:SF 0 "gpc_reg_operand" "") ! (match_operand:SF 1 "gpc_reg_operand" "")))] "" " *************** *** 2284,2289 **** (define_expand "cmpdf" [(set (cc0) ! (compare (match_operand:DF 0 "gen_reg_operand" "") ! (match_operand:DF 1 "gen_reg_operand" "")))] "" " --- 2284,2289 ---- (define_expand "cmpdf" [(set (cc0) ! (compare (match_operand:DF 0 "gpc_reg_operand" "") ! (match_operand:DF 1 "gpc_reg_operand" "")))] "" " *************** *** 2488,2492 **** (define_expand "seq" ! [(set (match_operand:SI 0 "gen_reg_operand" "") (eq:SI (match_dup 1) (match_dup 2)))] "" --- 2488,2492 ---- (define_expand "seq" ! [(set (match_operand:SI 0 "gpc_reg_operand" "") (eq:SI (match_dup 1) (match_dup 2)))] "" *************** *** 2502,2508 **** (define_expand "sne_fp" [(set (match_dup 3) ! (eq:SI (match_operand 1 "gen_reg_operand" "") ! (match_operand 2 "gen_reg_operand" ""))) ! (set (match_operand:SI 0 "gen_reg_operand" "") (ge:SI (match_dup 3) (const_int 0)))] "" --- 2502,2508 ---- (define_expand "sne_fp" [(set (match_dup 3) ! (eq:SI (match_operand 1 "gpc_reg_operand" "") ! (match_operand 2 "gpc_reg_operand" ""))) ! (set (match_operand:SI 0 "gpc_reg_operand" "") (ge:SI (match_dup 3) (const_int 0)))] "" *************** *** 2512,2516 **** (define_expand "sne" ! [(set (match_operand:SI 0 "gen_reg_operand" "") (ne:SI (match_dup 1) (match_dup 2)))] "" --- 2512,2516 ---- (define_expand "sne" ! [(set (match_operand:SI 0 "gpc_reg_operand" "") (ne:SI (match_dup 1) (match_dup 2)))] "" *************** *** 2530,2534 **** ;; operands, the same as we do "blt". (define_expand "slt" ! [(set (match_operand:SI 0 "gen_reg_operand" "") (match_dup 1))] "" --- 2530,2534 ---- ;; operands, the same as we do "blt". (define_expand "slt" ! [(set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] "" *************** *** 2543,2547 **** ;; Similarly for "le" (define_expand "sle" ! [(set (match_operand:SI 0 "gen_reg_operand" "") (match_dup 1))] "" --- 2543,2547 ---- ;; Similarly for "le" (define_expand "sle" ! [(set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] "" *************** *** 2555,2559 **** (define_expand "sltu" ! [(set (match_operand:SI 0 "gen_reg_operand" "") (ltu:SI (match_dup 1) (match_dup 2)))] "" --- 2555,2559 ---- (define_expand "sltu" ! [(set (match_operand:SI 0 "gpc_reg_operand" "") (ltu:SI (match_dup 1) (match_dup 2)))] "" *************** *** 2565,2569 **** (define_expand "sleu" ! [(set (match_operand:SI 0 "gen_reg_operand" "") (leu:SI (match_dup 1) (match_dup 2)))] "" --- 2565,2569 ---- (define_expand "sleu" ! [(set (match_operand:SI 0 "gpc_reg_operand" "") (leu:SI (match_dup 1) (match_dup 2)))] "" *************** *** 2575,2579 **** (define_expand "sgt" ! [(set (match_operand:SI 0 "gen_reg_operand" "") (gt:SI (match_dup 1) (match_dup 2)))] "" --- 2575,2579 ---- (define_expand "sgt" ! [(set (match_operand:SI 0 "gpc_reg_operand" "") (gt:SI (match_dup 1) (match_dup 2)))] "" *************** *** 2585,2589 **** (define_expand "sge" ! [(set (match_operand:SI 0 "gen_reg_operand" "") (ge:SI (match_dup 1) (match_dup 2)))] "" --- 2585,2589 ---- (define_expand "sge" ! [(set (match_operand:SI 0 "gpc_reg_operand" "") (ge:SI (match_dup 1) (match_dup 2)))] "" *************** *** 2595,2599 **** (define_expand "sgtu" ! [(set (match_operand:SI 0 "gen_reg_operand" "") (gtu:SI (match_dup 1) (match_dup 2)))] "" --- 2595,2599 ---- (define_expand "sgtu" ! [(set (match_operand:SI 0 "gpc_reg_operand" "") (gtu:SI (match_dup 1) (match_dup 2)))] "" *************** *** 2605,2609 **** (define_expand "sgeu" ! [(set (match_operand:SI 0 "gen_reg_operand" "") (geu:SI (match_dup 1) (match_dup 2)))] "" --- 2605,2609 ---- (define_expand "sgeu" ! [(set (match_operand:SI 0 "gpc_reg_operand" "") (geu:SI (match_dup 1) (match_dup 2)))] "" *************** *** 2618,2622 **** [(set (pc) (if_then_else (match_operator 0 "branch_operator" ! [(match_operand:SI 1 "gen_reg_operand" "r") (const_int 0)]) (label_ref (match_operand 2 "" "")) --- 2618,2622 ---- [(set (pc) (if_then_else (match_operator 0 "branch_operator" ! [(match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)]) (label_ref (match_operand 2 "" "")) *************** *** 2629,2633 **** [(set (pc) (if_then_else (match_operator 0 "branch_operator" ! [(match_operand:SI 1 "gen_reg_operand" "r") (const_int 0)]) (return) --- 2629,2633 ---- [(set (pc) (if_then_else (match_operator 0 "branch_operator" ! [(match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)]) (return) *************** *** 2640,2644 **** [(set (pc) (if_then_else (match_operator 0 "branch_operator" ! [(match_operand:SI 1 "gen_reg_operand" "r") (const_int 0)]) (pc) --- 2640,2644 ---- [(set (pc) (if_then_else (match_operator 0 "branch_operator" ! [(match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)]) (pc) *************** *** 2651,2655 **** [(set (pc) (if_then_else (match_operator 0 "branch_operator" ! [(match_operand:SI 1 "gen_reg_operand" "r") (const_int 0)]) (pc) --- 2651,2655 ---- [(set (pc) (if_then_else (match_operator 0 "branch_operator" ! [(match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)]) (pc) *************** *** 2674,2678 **** (define_insn "indirect_jump" [(set (pc) ! (match_operand:SI 0 "gen_reg_operand" "r"))] "" "jmpi %0%#" --- 2674,2678 ---- (define_insn "indirect_jump" [(set (pc) ! (match_operand:SI 0 "gpc_reg_operand" "r"))] "" "jmpi %0%#" *************** *** 2681,2685 **** (define_insn "tablejump" [(set (pc) ! (match_operand:SI 0 "gen_reg_operand" "r")) (use (label_ref (match_operand 1 "" "")))] "" --- 2681,2685 ---- (define_insn "tablejump" [(set (pc) ! (match_operand:SI 0 "gpc_reg_operand" "r")) (use (label_ref (match_operand 1 "" "")))] "" *************** *** 2690,2694 **** (define_insn "" [(set (pc) ! (if_then_else (ge (match_operand:SI 0 "gen_reg_operand" "r") (const_int 0)) (label_ref (match_operand 1 "" "")) --- 2690,2694 ---- (define_insn "" [(set (pc) ! (if_then_else (ge (match_operand:SI 0 "gpc_reg_operand" "r") (const_int 0)) (label_ref (match_operand 1 "" "")) diff -rc2N gcc-2.1/config/a29kunix.h gcc-2.2.1/config/a29kunix.h *** gcc-2.1/config/a29kunix.h Thu Feb 13 18:46:18 1992 --- gcc-2.2.1/config/a29kunix.h Fri May 15 01:02:54 1992 *************** *** 49,50 **** --- 49,63 ---- #undef BIGGEST_ALIGNMENT #define BIGGEST_ALIGNMENT 64 + + #if 0 /* This would be needed except that the 29k doesn't have strict + alignment requirements. */ + + #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ + (((TYPE) != 0) \ + ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \ + ? PARM_BOUNDARY \ + : TYPE_ALIGN(TYPE)) \ + : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \ + ? PARM_BOUNDARY \ + : GET_MODE_ALIGNMENT(MODE))) + #endif diff -rc2N gcc-2.1/config/amix.h gcc-2.2.1/config/amix.h *** gcc-2.1/config/amix.h Mon Jan 20 01:29:14 1992 --- gcc-2.2.1/config/amix.h Fri Apr 24 21:13:59 1992 *************** *** 22,25 **** --- 22,29 ---- #include "m68kv4.h" + /* Alter assembler syntax for fsgldiv. */ + + #define FSGLDIV_USE_S + /* Names to predefine in the preprocessor for this target machine. For the Amiga, these definitions match those of the native AT&T compiler. Note *************** *** 40,44 **** Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results ! we want. This difference can be accommodated by using an assembler define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END --- 44,48 ---- Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results ! we want. This difference can be accommodated by making the assembler define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END *************** *** 48,55 **** #define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \ do { \ ! if (RTX_INTEGRATED_P (TABLE)) \ asm_fprintf ((FILE), "%s %LLD%d,%LL%d\n", SET_ASM_OP, (NUM), (NUM));\ } while (0) /* This says how to output assembler code to declare an uninitialized external linkage data object. Under SVR4, --- 52,62 ---- #define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \ do { \ ! if (switch_table_difference_label_flag) \ asm_fprintf ((FILE), "%s %LLD%d,%LL%d\n", SET_ASM_OP, (NUM), (NUM));\ + switch_table_difference_label_flag = 0; \ } while (0) + int switch_table_difference_label_flag; + /* This says how to output assembler code to declare an uninitialized external linkage data object. Under SVR4, *************** *** 92,96 **** { \ register int sp = 0, lp = 0, ch; \ ! fprintf ((FILE), "%s ", BYTE_ASM_OP); \ do { \ ch = (PTR)[sp]; \ --- 99,103 ---- { \ register int sp = 0, lp = 0, ch; \ ! fprintf ((FILE), "\t%s ", BYTE_ASM_OP); \ do { \ ch = (PTR)[sp]; \ *************** *** 107,111 **** if ((sp % 10) == 0) \ { \ ! fprintf ((FILE), "\n%s ", BYTE_ASM_OP); \ } \ else \ --- 114,118 ---- if ((sp % 10) == 0) \ { \ ! fprintf ((FILE), "\n\t%s ", BYTE_ASM_OP); \ } \ else \ diff -rc2N gcc-2.1/config/apollo68.h gcc-2.2.1/config/apollo68.h *** gcc-2.1/config/apollo68.h Sat Nov 30 23:57:16 1991 --- gcc-2.2.1/config/apollo68.h Tue Mar 31 17:46:17 1992 *************** *** 1,4 **** /* Definitions of target machine for GNU compiler. Apollo 680X0 version. ! Copyright (C) 1989 Free Software Foundation, Inc. This file is part of GNU CC. --- 1,4 ---- /* Definitions of target machine for GNU compiler. Apollo 680X0 version. ! Copyright (C) 1989,1992 Free Software Foundation, Inc. This file is part of GNU CC. *************** *** 91,101 **** #define DOLLARS_IN_IDENTIFIERS 2 ! /* -m68000 requires special flags to the assembler. ! The -C flag is passed to a modified GNU assembler to cause COFF ! modules to be produced. Remove it if you're not using this. ! (See vasta@apollo.com.) */ #define ASM_SPEC \ ! "-C %{m68000:-mc68010}%{mc68000:-mc68010}%{!mc68000:%{!m68000:-mc68020}}" /* STARTFILE_SPEC --- 91,98 ---- #define DOLLARS_IN_IDENTIFIERS 2 ! /* -m68000 requires special flags to the assembler. */ #define ASM_SPEC \ ! "%{m68000:-mc68010}%{mc68000:-mc68010}%{!mc68000:%{!m68000:-mc68020}}" /* STARTFILE_SPEC *************** *** 123,126 **** --- 120,127 ---- #undef SDB_DEBUGGING_INFO + /* We have atexit(2). So C++ can use it for global destructors. */ + + #define HAVE_ATEXIT + /* Every structure or union's size must be a multiple of 2 bytes. */ *************** *** 127,147 **** #define STRUCTURE_SIZE_BOUNDARY 16 /* Functions which return large structures get the address ! to place the wanted value at offset 8 from the frame. */ #undef PCC_STATIC_STRUCT_RETURN #undef STRUCT_VALUE_REGNUM - - /* Caller treats address of return area like a parm. */ #define STRUCT_VALUE 0 ! ! #define STRUCT_VALUE_INCOMING \ ! gen_rtx (MEM, Pmode, \ ! gen_rtx (PLUS, SImode, frame_pointer_rtx, \ ! gen_rtx (CONST_INT, VOIDmode, 8))) ! ! /* Boundary (in *bits*) on which stack pointer should be aligned. */ ! #undef STACK_BOUNDARY ! #define STACK_BOUNDARY 32 /* Specify how to pad function arguments. --- 128,142 ---- #define STRUCTURE_SIZE_BOUNDARY 16 + /* Boundary (in *bits*) on which stack pointer should be aligned. */ + #undef STACK_BOUNDARY + #define STACK_BOUNDARY 32 + /* Functions which return large structures get the address ! to place the wanted value from a hidden parameter. */ #undef PCC_STATIC_STRUCT_RETURN #undef STRUCT_VALUE_REGNUM #define STRUCT_VALUE 0 ! #define STRUCT_VALUE_INCOMING 0 /* Specify how to pad function arguments. *************** *** 151,161 **** #define FUNCTION_ARG_PADDING(mode, size) none - /* Short integral argument prototype promotion is not done */ - - #undef PROMOTE_PROTOTYPES - /* The definition of this macro imposes a limit on the size of an aggregate object which can be treated as if it were a scalar ! object. */ #define MAX_FIXED_MODE_SIZE BITS_PER_WORD --- 146,152 ---- #define FUNCTION_ARG_PADDING(mode, size) none /* The definition of this macro imposes a limit on the size of an aggregate object which can be treated as if it were a scalar ! object. */ #define MAX_FIXED_MODE_SIZE BITS_PER_WORD *************** *** 170,180 **** (GET_MODE_SIZE (TYPE_MODE (type)) > UNITS_PER_WORD) ! /* This is how to output a reference to a user-level label named NAME. ! In order to link to Apollo libraries, no underscore is prepended to names. ! `assemble_name' uses this. */ ! ! #undef ASM_OUTPUT_LABELREF ! #define ASM_OUTPUT_LABELREF(FILE,NAME) \ ! fprintf (FILE, "%s", NAME) --- 161,208 ---- (GET_MODE_SIZE (TYPE_MODE (type)) > UNITS_PER_WORD) ! /* In order to link with Apollo libraries, we can't prefix external ! symbols with an underscore. */ ! ! #undef USER_LABEL_PREFIX ! ! /* Use a prefix for local labels, just to be on the save side. */ ! ! #undef LOCAL_LABEL_PREFIX ! #define LOCAL_LABEL_PREFIX "." ! ! /* Use a register prefix to avoid clashes with external symbols (classic ! example: `extern char PC;' in termcap). */ ! ! #undef REGISTER_PREFIX ! #define REGISTER_PREFIX "%" ! ! /* In the machine description we can't use %R, because it will not be seen ! by ASM_FPRINTF. (Isn't that a design bug?). */ ! ! #undef REGISTER_PREFIX_MD ! #define REGISTER_PREFIX_MD "%%" ! ! /* config/m68k.md has an explicit reference to the program counter, ! prefix this by the register prefix. */ ! ! #define ASM_RETURN_CASE_JUMP return "jmp %%pc@(2,%0:w)" ! + /* Here are the new register names. */ + #undef REGISTER_NAMES + #ifndef SUPPORT_SUN_FPA + #define REGISTER_NAMES \ + {"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \ + "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp", \ + "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7" } + #else /* SUPPORTED_SUN_FPA */ + #define REGISTER_NAMES \ + {"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \ + "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp", \ + "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7", \ + "%fpa0", "%fpa1", "%fpa2", "%fpa3", "%fpa4", "%fpa5", "%fpa6", "%fpa7", \ + "%fpa8", "%fpa9", "%fpa10", "%fpa11", "%fpa12", "%fpa13", "%fpa14", "%fpa15", \ + "%fpa16", "%fpa17", "%fpa18", "%fpa19", "%fpa20", "%fpa21", "%fpa22", "%fpa23", \ + "%fpa24", "%fpa25", "%fpa26", "%fpa27", "%fpa28", "%fpa29", "%fpa30", "%fpa31" } + #endif /* defined SUPPORT_SUN_FPA */ diff -rc2N gcc-2.1/config/arm.h gcc-2.2.1/config/arm.h *** gcc-2.1/config/arm.h Mon Mar 16 04:40:11 1992 --- gcc-2.2.1/config/arm.h Sat Apr 18 15:55:11 1992 *************** *** 892,896 **** /* The relative costs of various types of constants. Note that cse.c defines REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ ! #define CONST_COSTS(RTX, CODE) \ case CONST_INT: \ if (const_ok_for_arm (INTVAL (RTX))) \ --- 892,896 ---- /* The relative costs of various types of constants. Note that cse.c defines REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ ! #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ case CONST_INT: \ if (const_ok_for_arm (INTVAL (RTX))) \ diff -rc2N gcc-2.1/config/att386.h gcc-2.2.1/config/att386.h *** gcc-2.1/config/att386.h Tue Jan 21 21:56:47 1992 --- gcc-2.2.1/config/att386.h Tue May 5 23:54:41 1992 *************** *** 85,88 **** --- 85,89 ---- This is suitable for output with `assemble_name'. */ + #undef ASM_GENERATE_INTERNAL_LABEL #define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ sprintf ((BUF), ".%s%d", (PREFIX), (NUMBER)) *************** *** 91,94 **** --- 92,96 ---- PREFIX is the class of label and NUM is the number within the class. */ + #undef ASM_OUTPUT_INTERNAL_LABEL #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, ".%s%d:\n", PREFIX, NUM) diff -rc2N gcc-2.1/config/convex.h gcc-2.2.1/config/convex.h *** gcc-2.1/config/convex.h Sat Mar 14 00:15:29 1992 --- gcc-2.2.1/config/convex.h Wed May 6 23:58:23 1992 *************** *** 608,615 **** /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ ! #define REG_OK_FOR_INDEX_P(X) (REGNO (X) > 8) /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ ! #define REG_OK_FOR_BASE_P(X) (REGNO (X) > 8) #else --- 608,619 ---- /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ ! #define REG_OK_FOR_INDEX_P(X) \ ! (REGNO (X) > 8 \ ! && REGNO (X) != VIRTUAL_STACK_VARS_REGNUM \ ! && REGNO (X) != VIRTUAL_STACK_DYNAMIC_REGNUM \ ! && REGNO (X) != VIRTUAL_OUTGOING_ARGS_REGNUM) /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ ! #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X) #else *************** *** 752,756 **** return it with a return statement. Otherwise, break from the switch. */ ! #define CONST_COSTS(RTX,CODE) \ case CONST: \ case LABEL_REF: \ --- 756,760 ---- return it with a return statement. Otherwise, break from the switch. */ ! #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST: \ case LABEL_REF: \ *************** *** 765,769 **** On C1 and C2, multiply is faster than shift. */ ! #define RTX_COSTS(RTX,CODE) \ case MULT: \ total = COSTS_N_INSNS (4); \ --- 769,773 ---- On C1 and C2, multiply is faster than shift. */ ! #define RTX_COSTS(RTX,CODE,OUTER_CODE) \ case MULT: \ total = COSTS_N_INSNS (4); \ *************** *** 1165,1168 **** --- 1169,1173 ---- (DECL_VINDEX (DECL) = (INDEX)) + #if 0 /* collect2.c should no longer need these. */ /* Defs for compiling collect2.c in -pcc mode during bootstrap. */ *************** *** 1169,1179 **** #ifdef COLLECT ! #ifdef __STDC__ - #define HAVE_STRERROR - - #else - - #define vfprintf(file,fmt,args) _doprnt (fmt, args, file) #define WTERMSIG(x) (((union wait *) &(x))->w_termsig) #define WEXITSTATUS(x) (((union wait *) &(x))->w_retcode) --- 1174,1179 ---- #ifdef COLLECT ! #ifndef __STDC__ #define WTERMSIG(x) (((union wait *) &(x))->w_termsig) #define WEXITSTATUS(x) (((union wait *) &(x))->w_retcode) *************** *** 1182,1183 **** --- 1182,1184 ---- #endif /* COLLECT */ + #endif /* 0 */ diff -rc2N gcc-2.1/config/dec-osf1.h gcc-2.2.1/config/dec-osf1.h *** gcc-2.1/config/dec-osf1.h --- gcc-2.2.1/config/dec-osf1.h Tue Jun 2 15:27:38 1992 *************** *** 0 **** --- 1,26 ---- + /* Definitions of target machine for GNU compiler. DECstation (OSF/1) version. + Copyright (C) 1992 Free Software Foundation, Inc. + + This file is part of GNU CC. + + GNU CC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GNU CC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GNU CC; see the file COPYING. If not, write to + the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + #define DECSTATION + #define DEC_OSF1 + + #define CPP_PREDEFINES "-D__ANSI_COMPAT \ + -DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD -Dbsd4_2 -Dhost_mips -Dmips -Dosf -Dunix" + + #include "decstatn.h" diff -rc2N gcc-2.1/config/decrose.h gcc-2.2.1/config/decrose.h *** gcc-2.1/config/decrose.h Sat Mar 21 12:03:44 1992 --- gcc-2.2.1/config/decrose.h Thu May 7 06:07:32 1992 *************** *** 21,24 **** --- 21,27 ---- #define OSF_OS + #define HALF_PIC_DEBUG TARGET_DEBUG_B_MODE + #define HALF_PIC_PREFIX "$Lp." + #include "halfpic.h" *************** *** 47,56 **** #define CPP_SPEC "\ ! %{.S: -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ ! %{.cc: -D__LANGUAGE_C_PLUS_PLUS} \ ! %{.cxx: -D__LANGUAGE_C_PLUS_PLUS} \ ! %{.C: -D__LANGUAGE_C_PLUS_PLUS} \ ! %{.m: -D__LANGUAGE_OBJECTIVE_C} \ ! %{!.S: -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}}" #define LINK_SPEC "\ --- 50,60 ---- #define CPP_SPEC "\ ! %{.S: -D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY} \ ! -ULANGUAGE_C -U__LANGUAGE_C__} \ ! %{.cc: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS} \ ! %{.cxx: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS} \ ! %{.C: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS} \ ! %{.m: -D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C} \ ! %{!.S: -D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}}" #define LINK_SPEC "\ *************** *** 63,73 **** %{!mmips-as: \ %{v*: -v} \ ! %{pic-none: -noshrlib} %{noshrlib} \ ! %{!pic-none: -warn_nopic} \ ! %{nostdlib} %{glue}}" ! ! /* For now, force static libraries instead of shared, but do so that ! does not use -noshrlib, since the old linker does not provide it. */ ! #define LIB_SPEC "%{!pic-none: %{!pic-lib: -L/usr/ccs/lib }} -lc" #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}" --- 67,74 ---- %{!mmips-as: \ %{v*: -v} \ ! %{!noshrlib: %{pic-none: -noshrlib} %{!pic-none: -warn_nopic}} \ ! %{nostdlib} %{noshrlib} %{glue}}" ! ! #define LIB_SPEC "-lc" #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}" *************** *** 108,111 **** --- 109,134 ---- our own exit function. */ #define HAVE_ATEXIT + + /* Generate calls to memcpy, etc., not bcopy, etc. */ + #define TARGET_MEM_FUNCTIONS + + /* A C statement to output assembler commands which will identify + the object file as having been compiled with GNU CC (or another + GNU compiler). + + If you don't define this macro, the string `gcc2_compiled.:' is + output. This string is calculated to define a symbol which, on + BSD systems, will never be defined for any other reason. GDB + checks for the presence of this symbol when reading the symbol + table of an executable. + + On non-BSD systems, you must arrange communication with GDB in + some other fashion. If GDB is not used on your system, you can + define this macro with an empty body. + + On OSF/1, gcc2_compiled. confuses the kernel debugger, so don't + put it out. */ + + #define ASM_IDENTIFY_GCC(STREAM) #include "mips.h" diff -rc2N gcc-2.1/config/decstatn.h gcc-2.2.1/config/decstatn.h *** gcc-2.1/config/decstatn.h Sat Mar 21 12:01:55 1992 --- gcc-2.2.1/config/decstatn.h Tue Jun 2 15:30:38 1992 *************** *** 20,25 **** #define DECSTATION #define CPP_PREDEFINES "-D__ANSI_COMPAT \ ! -DMIPSEL -DR3000 -DSYSTYPE_BSD -Dbsd4_2 -Dhost_mips -Dmips -Dultrix -Dunix" #define ASM_SPEC "\ --- 20,27 ---- #define DECSTATION + #ifndef CPP_PREDEFINES #define CPP_PREDEFINES "-D__ANSI_COMPAT \ ! -DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD -Dbsd4_2 -Dhost_mips -Dmips -Dultrix -Dunix" ! #endif #define ASM_SPEC "\ *************** *** 35,44 **** #define CPP_SPEC "\ ! %{.S: -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ ! %{.cc: -D__LANGUAGE_C_PLUS_PLUS} \ ! %{.cxx: -D__LANGUAGE_C_PLUS_PLUS} \ ! %{.C: -D__LANGUAGE_C_PLUS_PLUS} \ ! %{.m: -D__LANGUAGE_OBJECTIVE_C} \ ! %{!.S: -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}}" #define LINK_SPEC "\ --- 37,46 ---- #define CPP_SPEC "\ ! %{.S: -D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ ! %{.cc: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS} \ ! %{.cxx: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS} \ ! %{.C: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS} \ ! %{.m: -D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C} \ ! %{!.S: -D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}}" #define LINK_SPEC "\ *************** *** 62,65 **** --- 64,70 ---- our own exit function. Ultrix 4.x has this, 3.x probably does not. */ #define HAVE_ATEXIT + + /* Generate calls to memcpy, etc., not bcopy, etc. */ + #define TARGET_MEM_FUNCTIONS #include "mips.h" diff -rc2N gcc-2.1/config/dpx2.h gcc-2.2.1/config/dpx2.h *** gcc-2.1/config/dpx2.h --- gcc-2.2.1/config/dpx2.h Thu May 21 04:04:22 1992 *************** *** 0 **** --- 1,159 ---- + /* + * dpx2.h - Bull DPX/2 200 and 300 systems (m68k, SysVr3) + * + * $Id: dpx2.h,v 1.1 1992/03/11 04:21:30 sjg Exp sjg $ + */ + + #include "m68k.h" + #undef SELECT_RTX_SECTION + #include "svr3.h" + + /* See m68k.h. 7 means 68020 with 68881. + * We really have 68030, but this will get us going. + */ + #ifndef TARGET_DEFAULT + #define TARGET_DEFAULT 7 + #endif + + #define OBJECT_FORMAT_COFF + #define NO_SYS_SIGLIST + + #ifdef CPP_PREDEFINES + #undef CPP_PREDEFINES + #endif + /* + * define all the things the compiler should + */ + #ifdef ncl_mr + # define CPP_PREDEFINES "-Dunix -Dbull -DDPX2 -DSVR3 -Dmc68000 -Dmc68020 -Dncl_mr=1" + #else + # ifdef ncl_el + # define CPP_PREDEFINES "-Dunix -Dbull -DDPX2 -DSVR3 -Dmc68000 -Dmc68020 -Dncl_el" + # else + # define CPP_PREDEFINES "-Dunix -Dbull -DDPX2 -DSVR3 -Dmc68000 -Dmc68020" + # endif + #endif + + #undef CPP_SPEC + /* + * use -ansi to imply POSIX and XOPEN and BULL source + * no -ansi implies _SYSV + */ + # define CPP_SPEC "%{ansi:-D_POSIX_SOURCE -D_XOPEN_SOURCE -D_BULL_SOURCE}\ + %{!ansi:-D_SYSV}" + + #undef ASM_LONG + #define ASM_LONG "\t.long" + + #define HAVE_ATEXIT + #undef DO_GLOBAL_CTORS_BODY /* don't use svr3.h version */ + #undef DO_GLOBAL_DTORS_BODY + + #if 0 /* def DEBUG */ + /* + * find out where cc1 aborts + */ + #define abort() do { fprintf(stderr, "%s: aborting at line %d\n", \ + __FILE__, __LINE__); \ + kill(getpid(), 6); } while (0) + #endif + + /* + * svr3.h says to use BSS_SECTION_FUNCTION + * but no one appears to, and there is + * no definition for m68k. + */ + #ifndef BSS_SECTION_FUNCTION + # undef EXTRA_SECTION_FUNCTIONS + # define EXTRA_SECTION_FUNCTIONS \ + CONST_SECTION_FUNCTION \ + INIT_SECTION_FUNCTION \ + FINI_SECTION_FUNCTION + #endif + + #ifndef USE_GAS + /* + * handle the native assembler. + * this does NOT yet work, there is much left to do. + * use GAS for now... + */ + #undef ASM_OUTPUT_SOURCE_FILENAME + #define ASM_OUTPUT_SOURCE_FILENAME(FILE, NA) \ + do { fprintf ((FILE), "\t.file\t'%s'\n", (NA)); } while (0) + + /* + * we don't seem to support any of: + * .globl + * .even + * .align + * .ascii + */ + #undef ASM_GLOBALIZE_LABEL + #define ASM_GLOBALIZE_LABEL(FILE,NAME) while (0) + #undef ASM_OUTPUT_ALIGN + #define ASM_OUTPUT_ALIGN(asm_out_file, align) while (0) + #define STRING_LIMIT (0) + #undef ASM_APP_ON + #define ASM_APP_ON "" + #undef ASM_APP_OFF + #define ASM_APP_OFF "" + /* + * dc.b 'hello, world!' + * dc.b 10,0 + * is how we have to output "hello, world!\n" + */ + #undef ASM_OUTPUT_ASCII + #define ASM_OUTPUT_ASCII(asm_out_file, p, thissize) \ + do { register int i, c, f=0; \ + for (i = 0; i < thissize; i++) { \ + c = p[i]; \ + if (c == '\'' || c < ' ' || c > 127) { \ + switch(f) { \ + case 0: /* need to output dc.b etc */ \ + fprintf(asm_out_file, "\tdc.b %d", c); \ + f=1; \ + break; \ + case 1: \ + fprintf(asm_out_file, ",%d", c); \ + break; \ + default: \ + /* close a string */ \ + fprintf(asm_out_file, "'\n\tdc.b %d", c); \ + f=1; \ + break; \ + } \ + } else { \ + switch(f) { \ + case 0: \ + fprintf(asm_out_file, "\tdc.b '%c", c); \ + f=2; \ + break; \ + case 2: \ + fprintf(asm_out_file, "%c", c); \ + break; \ + default: \ + fprintf(asm_out_file, "\n\tdc.b '%c", c); \ + f=2; \ + break; \ + } \ + } \ + } \ + if (f==2) \ + putc('\'', asm_out_file); \ + putc('\n', asm_out_file); } while (0) + + /* This is how to output an insn to push a register on the stack. + It need not be very fast code. */ + + #undef ASM_OUTPUT_REG_PUSH + #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ + fprintf (FILE, "\tmove.l %s,-(sp)\n", reg_names[REGNO]) + + /* This is how to output an insn to pop a register from the stack. + It need not be very fast code. */ + + #undef ASM_OUTPUT_REG_POP + #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ + fprintf (FILE, "\tmove.l (sp)+,%s\n", reg_names[REGNO]) + + #endif /* ! use gas */ diff -rc2N gcc-2.1/config/dpx2g.h gcc-2.2.1/config/dpx2g.h *** gcc-2.1/config/dpx2g.h --- gcc-2.2.1/config/dpx2g.h Fri Mar 27 16:26:48 1992 *************** *** 0 **** --- 1,42 ---- + /* + * dpx2g.h - Bull DPX/2 200 and 300 systems (m68k, SysVr3) with gas + * + * $Id: dpx2g.h,v 1.1 1992/03/11 04:21:58 sjg Exp sjg $ + */ + + #define USE_GAS + #include "dpx2.h" + + + /* GAS want's DBX debugging information. */ + #undef SDB_DEBUGGING_INFO + #ifndef DBX_DEBUGGING_INFO + #define DBX_DEBUGGING_INFO + #endif + + /* + * we are using GAS + */ + #undef EXTRA_SECTION_FUNCTIONS + #undef EXTRA_SECTIONS + + /* + * put const's in the text section + */ + #define const_section() text_section() + #define fini_section() while (0) + + #if 0 /* this is fixed in 2.1 */ + #undef ASM_OUTPUT_ALIGN + #define ASM_OUTPUT_ALIGN(FILE,LOG) \ + if ((LOG) >= 1) \ + fprintf (FILE, "\t.even\n"); + #endif + + #undef CTORS_SECTION_ASM_OP + #define CTORS_SECTION_ASM_OP "\t.data" + #undef DTORS_SECTION_ASM_OP + #define DTORS_SECTION_ASM_OP "\t.data" + #undef INIT_SECTION_ASM_OP + + /* end of dpx2g.h */ diff -rc2N gcc-2.1/config/encore.h gcc-2.2.1/config/encore.h *** gcc-2.1/config/encore.h Fri Mar 13 17:34:08 1992 --- gcc-2.2.1/config/encore.h Fri Apr 17 20:04:05 1992 *************** *** 145,207 **** } ! #define NO_ABSOLUTE_PREFIX_IF_SYMBOLIC ! /* ! * Dollar signs are required before immediate operands, double ! * floating point constants use $0f syntax, and external addresses ! * should be prefixed with a question mark to avoid assembler warnings ! * about undefined symbols. ! */ ! #define PRINT_OPERAND(FILE, X, CODE) \ ! { if (CODE == '$') putc ('$', FILE); \ ! else if (CODE == '?') fputc ('?', FILE); \ ! else if (GET_CODE (X) == REG) \ ! fprintf (FILE, "%s", reg_names[REGNO (X)]); \ ! else if (GET_CODE (X) == MEM) \ ! { \ ! rtx xfoo; \ ! xfoo = XEXP (X, 0); \ ! switch (GET_CODE (xfoo)) \ ! { \ ! case MEM: \ ! if (GET_CODE (XEXP (xfoo, 0)) == REG) \ ! if (REGNO (XEXP (xfoo, 0)) == STACK_POINTER_REGNUM) \ ! fprintf (FILE, "0(0(sp))"); \ ! else fprintf (FILE, "0(0(%s))", \ ! reg_names[REGNO (XEXP (xfoo, 0))]); \ ! else \ ! { \ ! fprintf (FILE, "0("); \ ! output_address (xfoo); \ ! putc (')', FILE); \ ! } \ ! break; \ ! case REG: \ ! fprintf (FILE, "0(%s)", reg_names[REGNO (xfoo)]); \ ! break; \ ! case PRE_DEC: \ ! case POST_INC: \ ! fprintf (FILE, "tos"); \ ! break; \ ! case CONST_INT: \ ! fprintf (FILE, "@%d", INTVAL (xfoo)); \ ! break; \ ! default: \ ! output_address (xfoo); \ ! break; \ ! } \ ! } \ ! else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != DImode) \ ! if (GET_MODE (X) == DFmode) \ ! { union { double d; int i[2]; } u; \ ! u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \ ! fprintf (FILE, "$0f%.20e", u.d); } \ ! else { union { double d; int i[2]; } u; \ ! u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \ ! fprintf (FILE, "$0f%.20e", u.d); } \ ! else if (GET_CODE (X) == CONST) \ ! output_addr_const (FILE, X); \ ! else { putc ('$', FILE); output_addr_const (FILE, X); }} #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address(FILE, ADDR) --- 145,154 ---- } ! /* Modify syntax of jsr instructions. */ ! #define CALL_MEMREF_IMPLICIT ! #define NO_ABSOLUTE_PREFIX_IF_SYMBOLIC ! #define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE) #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address(FILE, ADDR) diff -rc2N gcc-2.1/config/encrose.h gcc-2.2.1/config/encrose.h *** gcc-2.1/config/encrose.h Fri Feb 21 17:08:26 1992 --- gcc-2.2.1/config/encrose.h Tue Apr 28 16:34:27 1992 *************** *** 260,261 **** --- 260,283 ---- our own exit function. */ #define HAVE_ATEXIT + + /* Generate calls to memcpy, etc., not bcopy, etc. */ + #define TARGET_MEM_FUNCTIONS + + /* A C statement to output assembler commands which will identify + the object file as having been compiled with GNU CC (or another + GNU compiler). + + If you don't define this macro, the string `gcc2_compiled.:' is + output. This string is calculated to define a symbol which, on + BSD systems, will never be defined for any other reason. GDB + checks for the presence of this symbol when reading the symbol + table of an executable. + + On non-BSD systems, you must arrange communication with GDB in + some other fashion. If GDB is not used on your system, you can + define this macro with an empty body. + + On OSF/1, gcc2_compiled. confuses the kernel debugger, so don't + put it out. */ + + #define ASM_IDENTIFY_GCC(STREAM) diff -rc2N gcc-2.1/config/fx2800.h gcc-2.2.1/config/fx2800.h *** gcc-2.1/config/fx2800.h Fri Jan 3 00:56:36 1992 --- gcc-2.2.1/config/fx2800.h Sat Jun 6 17:38:44 1992 *************** *** 1,6 **** ! /* Target definitions for GNU compiler for Alliant FX/2800 w/Concentrix 2.x Copyright (C) 1991 Free Software Foundation, Inc. ! Written by Ron Guilmette (rfg@ncd.com). This file is part of GNU CC. --- 1,8 ---- ! /* Target definitions for GNU compiler for Alliant FX/2800 ! running Concentrix 2.2 ! Copyright (C) 1991 Free Software Foundation, Inc. ! Written by Howard Chu (hyc@hanauma.jpl.nasa.gov). This file is part of GNU CC. *************** *** 20,46 **** the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ ! /* The Alliant fx2800 running Concentrix 2.1 is weird. This is basically ! a BSD 4.3 based operating system, but it runs svr4 ELF format object ! files and it somehow puts BSD stabs records into the ELF files for ! symbolic debug information. It also seems to use the assembler from ! the svr4 reference port, but that assembler has probably been hacked ! slightly to allow the BSD stabs to be smuggled in. ! ! Given that we need to use svr4-style pseudo-ops, and given that the ! target object file format is ELF, we just include "i860v4.h" here so ! as to pick-up a set of defines appropriate for for an svr4/ELF target ! and then we just override the few things that are special for the FX/2800 ! and Concentrix. */ #include "i860v4.h" ! #undef DWARF_DEBUGGING_INFO ! #define DBX_DEBUGGING_INFO ! /* Provide a set of pre-definitions and pre-assertions appropriate for ! the i860 running Concentrix 2.1. */ ! #undef CPP_PREDEFINES ! #define CPP_PREDEFINES "-Di860 -Dunix -DBSD4_3 -Dalliant -Asystem(unix) -Acpu(i860) -Amachine(i860)" /* Undefine some things defined in i860.h because the native C compiler --- 22,234 ---- the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ ! #define OUTPUT_TDESC #include "i860v4.h" ! /* The Alliant fx2800 running Concentrix 2.x is weird. This is basically ! a BSD 4.3 based operating system, but it uses svr4 ELF format object ! files and it somehow puts BSD stabs records into the ELF files for ! symbolic debug information. The assembler is "mostly an SVR4 assembler ! with some Alliant additions. We based it on the `Intel 80860 Assembly ! Language Specification' from AT&T." */ ! ! /* This file consists of three sections. The first section establishes ! definitions unique to the Alliant FX/2800. The next section reconciles ! differences between Alliant and i860v4.h, and the last overrides the ! remaining differences with svr4.h */ ! ! #undef TARGET_VERSION ! #define TARGET_VERSION fprintf (stderr, " (i860 Alliant)"); ! ! /* atexit is not present prior to Concentrix 2.2. Uncomment the following ! if you're on 2.1 or older. */ ! ! /* #undef HAVE_ATEXIT */ ! #define I860_STRICT_ABI_PROLOGUES ! /* Most of the Alliant-specific definitions here are to get stab info that ! Alliant's dbx can understand. */ ! ! #define DBX_DEBUGGING_INFO ! #define DEFAULT_GDB_EXTENSIONS 0 ! #define DBX_NO_XREFS ! #define DBX_NO_EXTRA_TAGS ! ! /* Alliant dbx also needs to see the function stab before anything ! else in the function. */ ! ! #define DBX_FUNCTION_FIRST ! #define DBX_LBRAC_FIRST ! ! /* Alliant dbx also needs to see the end of a function somewhere. */ ! ! #define DBX_OUTPUT_FUNCTION_END(file,decl) \ ! fprintf (file, ".stab \"\",.,0x%x,0,0\n", N_EFUN) ! ! /* Alliant dbx has predefined types, so they must be emitted with the ! proper type numbers. The defined types are: ! ! Type # C, Fortran, Pascal Types ! -- ------------------------ ! 1 char, integer*1 ! 2 short, integer*2 ! 3 int, long, integer*4, integer ! 4 logical*1, byte ! 5 logical*2 ! 6 logical*4, logical ! 7 float, real*4, real ! 8 double, real*8, double ! 9 single complex, complex*8, complex ! 10 double complex, doublecomplex ! 11 character ! 12 void ! 13 nil ! 14 boolean ! 15 unsigned char, ubyte ! 16 unsigned short, uword ! 17 unsigned, unsigned int, unsigned long, ulong ! 18 quad, logical*8 ! 19 long long, integer*8 ! 20 unsigned long long, uquad*8 ! 21-100 reserved for future predefined types ! 100 long redefine same as 3 ! 101 unsigned long same as 17 ! -- -------------------- ! 102 First user program type ! ! Since long and unsigned long are int references, they must be handled ! as special cases. The Alliant compiler doesn't use types 18-20, so it ! sets long & unsigned long in 18 & 19, not in 100 & 101 as shown above. */ ! ! #define DBX_OUTPUT_STANDARD_TYPES(syms) \ ! { char *dtyps[]={"", "char", "short int", "int", "logical*1", \ ! "logical*2", "logical*4", "float", "double", "complex", \ ! "doublecomplex", "character", "void", "nil", "boolean", \ ! "unsigned char", "short unsigned int", "unsigned int", \ ! "logical*8", "long long int", "long long unsigned int",""}; \ ! \ ! tree decl; \ ! int i; \ ! \ ! for (i=1;*dtyps[i];i++) \ ! for (decl = syms; decl; decl = TREE_CHAIN(decl)) \ ! if ((TREE_CODE (decl) == TYPE_DECL) && \ ! !strcmp(IDENTIFIER_POINTER(DECL_NAME(decl)), dtyps[i])) { \ ! TYPE_SYMTAB_ADDRESS (TREE_TYPE (decl)) = i; \ ! typevec[i] = TYPE_DEFINED; \ ! dbxout_symbol (decl, 0); \ ! break; \ ! } \ ! \ ! for (decl = syms; decl; decl = TREE_CHAIN(decl)) \ ! if ((TREE_CODE (decl) == TYPE_DECL) && \ ! !strcmp(IDENTIFIER_POINTER(DECL_NAME(decl)),"long int")) { \ ! TYPE_SYMTAB_ADDRESS (TREE_TYPE (decl)) = i; \ ! typevec[i] = TYPE_DEFINED; \ ! fprintf(asmfile,".stab \"long int:t%d=3\",0,0x%x,0,0\n", \ ! i++,N_LSYM); \ ! TREE_ASM_WRITTEN (decl) = 1; \ ! break; \ ! } \ ! \ ! for (decl = syms; decl; decl = TREE_CHAIN(decl)) \ ! if ((TREE_CODE (decl) == TYPE_DECL) && !strcmp( \ ! IDENTIFIER_POINTER(DECL_NAME(decl)),"long unsigned int")) { \ ! TYPE_SYMTAB_ADDRESS (TREE_TYPE (decl)) = i; \ ! typevec[i] = TYPE_DEFINED; \ ! fprintf(asmfile,".stab \"long unsigned int:t%d=17\",0,0x%x,0,0\n",\ ! i++,N_LSYM); \ ! TREE_ASM_WRITTEN (decl) = 1; \ ! break; \ ! } \ ! next_type_number = i; }; ! ! /* Alliant dbx doesn't understand split names... */ ! ! #define DBX_CONTIN_LENGTH 0 ! ! /* The syntax for stabs records is also different; there is only a single ! ".stab" directive instead of the 3 directives in BSD, and the order of ! arguments is slightly changed. */ ! ! #define ASM_STABS_OP ".stab" ! #define ASM_STABN_OP ".stab" ! #define ASM_STABD_OP ".stab" ! ! #define DBX_MEMPARM_STABS_LETTER 'k' ! #define DBX_REGPARM_STABS_LETTER 'r' ! ! #define ASM_OUTPUT_SOURCE_LINE(file,num) \ ! fprintf (file, "\t.stab \"\",.,0x%x,0,%d\n", \ ! N_SLINE,num) ! ! #if 0 /* Alliant dbx only reads first N_SO, so it ! ignores the filename if dir is present. */ ! #define DBX_OUTPUT_MAIN_SOURCE_DIRECTORY(file,name) \ ! fprintf (file, ".stab \"%s/\",.Ltext0,0x%x,0,0\n", \ ! name, N_SO) ! #else ! #define DBX_OUTPUT_MAIN_SOURCE_DIRECTORY(file,name) ! #endif ! ! #define DBX_OUTPUT_MAIN_SOURCE_FILENAME(file,name) \ ! fprintf (file, ".stab \"%s\",.Ltext0,0x%x,0,0\n", \ ! name, N_SO); \ ! text_section (); \ ! ASM_OUTPUT_INTERNAL_LABEL (file, "Ltext", 0) ! ! #define DBX_OUTPUT_SOURCE_FILENAME(file,name) \ ! fprintf (file, ".stab \"%s\",.Ltext0,0x%x,0,0\n", \ ! name, N_SOL); ! ! #define DBX_OUTPUT_CONSTANT_SYMBOL(file,name,ival) \ ! fprintf (file, ".stab \"%s:c=i%d\",0,0x%x,0,0\n", \ ! name, ival, N_LSYM) ! ! #define DBX_FINISH_SYMBOL(decl) \ ! int line = 0; \ ! fprintf (asmfile, "\","); \ ! if (current_sym_addr) \ ! output_addr_const (asmfile, current_sym_addr); \ ! else \ ! fprintf (asmfile, "%d", current_sym_value); \ ! if (decl != 0 && TREE_CODE(decl) == FUNCTION_DECL) \ ! line=DECL_SOURCE_LINE (decl); \ ! fprintf (asmfile, ",0x%x,%d,%d\n", current_sym_code, \ ! line!=0?64:0,line) ! ! #define DBX_OUTPUT_CATCH(file,decl,name) \ ! fprintf (file, ".stab \"%s:C1\",", \ ! IDENTIFIER_POINTER (DECL_NAME (decl))); \ ! assemble_name (file, name); \ ! fprintf (file, ",0x%x,0,0\n", N_CATCH) ! ! #define DBX_OUTPUT_LBRAC(file,name) \ ! if (depth > 1) { \ ! fprintf (file, ".stab \"\","); \ ! assemble_name (file, name); \ ! fprintf (file, ",0x%x,0,%d\n", N_LBRAC, depth); } ! ! #define DBX_OUTPUT_RBRAC(file,name) \ ! if (depth > 1) { \ ! fprintf (file, ".stab \"\","); \ ! assemble_name (file, name); \ ! fprintf (file, ",0x%x,0,%d\n", N_RBRAC, depth); } ! ! #define DBX_OUTPUT_ENUM(file,type) \ ! fprintf (file, "e3"); \ ! CHARS(2); \ ! for (tem = TYPE_VALUES (type); tem; tem = TREE_CHAIN (tem)) \ ! { \ ! fprintf (asmfile, "%s:%d,", \ ! IDENTIFIER_POINTER (TREE_PURPOSE (tem)), \ ! TREE_INT_CST_LOW (TREE_VALUE (tem))); \ ! CHARS (11 + IDENTIFIER_LENGTH (TREE_PURPOSE (tem))); \ ! if (TREE_CHAIN (tem) != 0) \ ! CONTIN; \ ! } \ ! putc (';', asmfile); \ ! CHARS (1); /* Undefine some things defined in i860.h because the native C compiler *************** *** 47,51 **** on the FX/2800 emits code to do these operations inline. For GCC, we will use the default implementation of these things... i.e. ! generating calls to libgcc1.c routines. */ #undef DIVSI3_LIBCALL --- 235,239 ---- on the FX/2800 emits code to do these operations inline. For GCC, we will use the default implementation of these things... i.e. ! generating calls to libgcc1 routines. */ #undef DIVSI3_LIBCALL *************** *** 53,54 **** --- 241,337 ---- #undef REMSI3_LIBCALL #undef UREMSI3_LIBCALL + + /* The Alliant compiler's mod function gives the wrong result after a + shift operation. This bug typically hits in hash functions. */ + + #define perform_umodsi3(a, b) a %= b; if (a == b) a=0; return a + #define perform_modsi3(a, b) a %= b; if (a == b) a=0; return a + + /* Global pointer needs to be 8 byte aligned? Link error if not... */ + + #define DATA_ALIGNMENT(dummy,align) \ + ((TREE_PUBLIC (decl) && \ + (TREE_CODE (TREE_TYPE (decl))==POINTER_TYPE)) ? 64:align) + + #undef FUNCTION_PROFILER + #define FUNCTION_PROFILER(FILE, LABELNO) \ + fprintf (FILE, "\tcall __mcount_\n\tnop\n") + + /* Overrides for i860v4.h begin here */ + + /* Provide a set of pre-definitions and pre-assertions appropriate for + the i860 running Concentrix 2.x. */ + + #undef CPP_PREDEFINES + #define CPP_PREDEFINES "-Di860 -Dunix -DBSD4_3 -Dalliant -Asystem(unix) -Acpu(i860) -Amachine(i860)" + + #undef I860_REG_PREFIX + #undef ASM_COMMENT_START + #define ASM_COMMENT_START "//" + + /* Use definitions of ASM_OUTPUT_{DOUBLE,FLOAT} as given in i860.h */ + + #undef ASM_OUTPUT_DOUBLE + #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ + fprintf(FILE, "\t.double %.20e\n", (VALUE)) + #undef ASM_OUTPUT_FLOAT + #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ + fprintf(FILE, "\t.float %.12e\n", (VALUE)) + + #undef ASM_FILE_START + #define ASM_FILE_START(FILE) + #undef ASM_OUTPUT_FUNCTION_PREFIX + #define ASM_OUTPUT_FUNCTION_PREFIX(FILE,NAME) \ + fputs("\tnop\n", (FILE)); \ + current_function_original_name = (NAME) + #undef ASM_OUTPUT_PROLOGUE_SUFFIX + + /* Overrides for svr4.h begin here */ + + #undef SVR4 + + #undef SWITCH_TAKES_ARG + #undef WORD_SWITCH_TAKES_ARG + + #undef ASM_SPEC + #undef ASM_FINAL_SPEC + #undef MD_STARTFILE_PREFIX + #undef MD_EXEC_PREFIX + + /* Generate an error message if -p option is selected. Concentrix 2.x + does not support prof format profiling, only gprof is supported. */ + + #define CPP_SPEC "%{p:%e-p option not supported: use -pg instead}" + + /* Provide an appropriate LIB_SPEC. The crtend.o file provides part of the + support for getting C++ file-scope static objects constructed before + entering `main'. */ + + #undef LIB_SPEC + #define LIB_SPEC \ + "%{g*:-lg} %{!pg:-lc}%{pg:-lc_p} crtend.o%s" + + /* Tell linker to strip local symbols, since assembler may not. */ + + #undef LINK_SPEC + #define LINK_SPEC "-X" + + /* Get the correct startup file for regular or profiled code. Also + use the crtbegin.o file for C++ ... */ + + #undef STARTFILE_SPEC + #define STARTFILE_SPEC \ + "%{!pg:crt0.o%s}%{pg:gcrt0.o%s} crtbegin.o%s" + + #undef SCCS_DIRECTIVE + #undef NO_DOLLAR_IN_LABEL + #undef TARGET_MEM_FUNCTIONS + + #undef DWARF_DEBUGGING_INFO + + #undef ASM_OUTPUT_LABELREF + #define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "_%s", NAME) + #undef ASM_OUTPUT_EXTERNAL_LIBCALL + + #undef BSS_ASM_OP + #define BSS_ASM_OP "\t.lcomm" diff -rc2N gcc-2.1/config/fx80.h gcc-2.2.1/config/fx80.h *** gcc-2.1/config/fx80.h Mon Mar 16 04:40:39 1992 --- gcc-2.2.1/config/fx80.h Sat Apr 18 15:54:56 1992 *************** *** 871,875 **** return it with a return statement. Otherwise, break from the switch. */ ! #define CONST_COSTS(RTX,CODE) \ case CONST_INT: \ /* Constant zero is super cheap due to clr instruction. */ \ --- 871,875 ---- return it with a return statement. Otherwise, break from the switch. */ ! #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ /* Constant zero is super cheap due to clr instruction. */ \ diff -rc2N gcc-2.1/config/genix.h gcc-2.2.1/config/genix.h *** gcc-2.1/config/genix.h Sat Nov 30 23:56:52 1991 --- gcc-2.2.1/config/genix.h Mon May 11 20:48:14 1992 *************** *** 107,110 **** --- 107,113 ---- * Output `(sb)' in certain indirect refs. */ + #error this has not been updated since version 1. + #error it is certainly wrong. + #undef PRINT_OPERAND #define PRINT_OPERAND(FILE, X, CODE) \ diff -rc2N gcc-2.1/config/gmicro.h gcc-2.2.1/config/gmicro.h *** gcc-2.1/config/gmicro.h Mon Mar 16 04:41:03 1992 --- gcc-2.2.1/config/gmicro.h Sat Apr 18 15:54:59 1992 *************** *** 1178,1182 **** return it with a return statement. Otherwise, break from the switch. */ ! #define CONST_COSTS(RTX,CODE) \ case CONST_INT: \ if ((unsigned) INTVAL (RTX) < 8) return 0; \ --- 1178,1182 ---- return it with a return statement. Otherwise, break from the switch. */ ! #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ if ((unsigned) INTVAL (RTX) < 8) return 0; \ diff -rc2N gcc-2.1/config/hp320.h gcc-2.2.1/config/hp320.h *** gcc-2.1/config/hp320.h Fri Mar 20 14:10:00 1992 --- gcc-2.2.1/config/hp320.h Tue Mar 31 04:03:20 1992 *************** *** 165,170 **** #undef PRINT_OPERAND_ADDRESS #undef FUNCTION_PROFILER - #undef ASM_GLOBALIZE_LABEL #undef ASM_OUTPUT_INTERNAL_LABEL #define TARGET_VERSION fprintf (stderr, " (68k, SGS/hpux syntax)"); --- 165,170 ---- #undef PRINT_OPERAND_ADDRESS #undef FUNCTION_PROFILER #undef ASM_OUTPUT_INTERNAL_LABEL + #undef GLOBAL_ASM_OP #define TARGET_VERSION fprintf (stderr, " (68k, SGS/hpux syntax)"); *************** *** 294,297 **** --- 294,302 ---- #define ASCII_DATA_ASM_OP "byte" + + /* This is the command to make the user-level label named NAME + defined for reference from other files. */ + + #define GLOBAL_ASM_OP "global" /* This says how to output an assembler line *************** *** 318,327 **** ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12), \ sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO))) - - /* This is how to output a command to make the user-level label named NAME - defined for reference from other files. */ - - #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ - do { fputs ("\tglobal ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ --- 323,326 ---- diff -rc2N gcc-2.1/config/i386.c gcc-2.2.1/config/i386.c *** gcc-2.1/config/i386.c Thu Mar 19 01:13:20 1992 --- gcc-2.2.1/config/i386.c Fri May 15 13:11:23 1992 *************** *** 46,49 **** --- 46,50 ---- char *singlemove_string (); char *output_move_const_single (); + char *output_fp_cc0_set (); static char *hi_reg_name[] = HI_REGISTER_NAMES; *************** *** 66,69 **** --- 67,76 ---- INDEX_REGS }; + + /* Test and compare insns in i386.md store the information needed to + generate branch and scc insns here. */ + + struct rtx_def *i386_compare_op0, *i386_compare_op1; + struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); /* Output an insn whose source is a 386 integer register. SRC is the *************** *** 615,618 **** --- 622,627 ---- int limit; rtx xops[4]; + int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table + || current_function_uses_const_pool); xops[0] = stack_pointer_rtx; *************** *** 640,645 **** for (regno = limit - 1; regno >= 0; regno--) if ((regs_ever_live[regno] && ! call_used_regs[regno]) ! || (current_function_uses_pic_offset_table ! && regno == PIC_OFFSET_TABLE_REGNUM)) { xops[0] = gen_rtx (REG, SImode, regno); --- 649,653 ---- for (regno = limit - 1; regno >= 0; regno--) if ((regs_ever_live[regno] && ! call_used_regs[regno]) ! || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) { xops[0] = gen_rtx (REG, SImode, regno); *************** *** 647,651 **** } ! if (current_function_uses_pic_offset_table) { xops[0] = pic_offset_table_rtx; --- 655,659 ---- } ! if (pic_reg_used) { xops[0] = pic_offset_table_rtx; *************** *** 676,679 **** --- 684,689 ---- int reglimit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); + int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table + || current_function_uses_const_pool); #ifdef NON_SAVING_SETJMP *************** *** 687,692 **** for (regno = reglimit - 1; regno >= 0; regno--) if ((regs_ever_live[regno] && ! call_used_regs[regno]) ! || (current_function_uses_pic_offset_table ! && regno == PIC_OFFSET_TABLE_REGNUM)) nregs++; --- 697,701 ---- for (regno = reglimit - 1; regno >= 0; regno--) if ((regs_ever_live[regno] && ! call_used_regs[regno]) ! || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) nregs++; *************** *** 707,710 **** --- 716,721 ---- int offset; rtx xops[3]; + int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table + || current_function_uses_const_pool); /* Compute the number of registers to pop */ *************** *** 718,723 **** for (regno = limit - 1; regno >= 0; regno--) if ((regs_ever_live[regno] && ! call_used_regs[regno]) ! || (current_function_uses_pic_offset_table ! && regno == PIC_OFFSET_TABLE_REGNUM)) nregs++; --- 729,733 ---- for (regno = limit - 1; regno >= 0; regno--) if ((regs_ever_live[regno] && ! call_used_regs[regno]) ! || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) nregs++; *************** *** 745,750 **** for (regno = 0; regno < limit; regno++) if ((regs_ever_live[regno] && ! call_used_regs[regno]) ! || (current_function_uses_pic_offset_table ! && regno == PIC_OFFSET_TABLE_REGNUM)) { xops[0] = gen_rtx (REG, SImode, regno); --- 755,759 ---- for (regno = 0; regno < limit; regno++) if ((regs_ever_live[regno] && ! call_used_regs[regno]) ! || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) { xops[0] = gen_rtx (REG, SImode, regno); *************** *** 755,760 **** for (regno = 0; regno < limit; regno++) if ((regs_ever_live[regno] && ! call_used_regs[regno]) ! || (current_function_uses_pic_offset_table ! && regno == PIC_OFFSET_TABLE_REGNUM)) { xops[0] = gen_rtx (REG, SImode, regno); --- 764,768 ---- for (regno = 0; regno < limit; regno++) if ((regs_ever_live[regno] && ! call_used_regs[regno]) ! || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) { xops[0] = gen_rtx (REG, SImode, regno); *************** *** 976,981 **** return; - case 'D': - PUT_OP_SIZE (code, 'l', file); case 'L': PUT_OP_SIZE (code, 'l', file); --- 984,987 ---- *************** *** 998,1005 **** return; - case 'R': - fprintf (file, "%s", RP); - return; - case 'z': /* 387 opcodes don't get size suffixes if the operands are --- 1004,1007 ---- *************** *** 1032,1036 **** case 8: if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) ! PUT_OP_SIZE ('Q', 'l', file); PUT_OP_SIZE ('Q', 'l', file); --- 1034,1045 ---- case 8: if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) ! { ! #ifdef GAS_MNEMONICS ! PUT_OP_SIZE ('Q', 'q', file); ! return; ! #else ! PUT_OP_SIZE ('Q', 'l', file); /* Fall through */ ! #endif ! } PUT_OP_SIZE ('Q', 'l', file); *************** *** 1037,1040 **** --- 1046,1060 ---- return; } + + case 'b': + case 'w': + case 'k': + case 'h': + case 'y': + case 'P': + break; + + default: + abort (); } } *************** *** 1063,1073 **** u.i[1] = CONST_DOUBLE_HIGH (x); u1.f = u.d; ! if (code == 'f') ! fprintf (file, "%.22e", u1.f); ! else ! { ! PRINT_IMMED_PREFIX (file); ! fprintf (file, "0x%x", u1.i); ! } } else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) --- 1083,1088 ---- u.i[1] = CONST_DOUBLE_HIGH (x); u1.f = u.d; ! PRINT_IMMED_PREFIX (file); ! fprintf (file, "0x%x", u1.i); } else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) *************** *** 1080,1086 **** else { ! if (code != 'c' && code != 'P') { ! if (GET_CODE (x) == CONST_INT) PRINT_IMMED_PREFIX (file); else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF --- 1095,1101 ---- else { ! if (code != 'P') { ! if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) PRINT_IMMED_PREFIX (file); else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF *************** *** 1353,1356 **** --- 1368,1373 ---- if (! stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0)))) cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0)); + + cc_status.flags |= CC_IN_80387; return; } *************** *** 1679,1683 **** /* Output code for INSN to compare OPERANDS. The two operands might not have the same mode: one might be within a FLOAT or FLOAT_EXTEND ! expression. */ char * --- 1696,1701 ---- /* Output code for INSN to compare OPERANDS. The two operands might not have the same mode: one might be within a FLOAT or FLOAT_EXTEND ! expression. If the compare is in mode CCFPEQmode, use an opcode that ! will not fault if a qNaN is present. */ char * *************** *** 1687,1690 **** --- 1705,1710 ---- { int stack_top_dies; + rtx body = XVECEXP (PATTERN (insn), 0, 0); + int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode; if (! STACK_TOP_P (operands[0])) *************** *** 1702,1706 **** `fcompp' float compare */ ! output_asm_insn ("fcompp", operands); } else --- 1722,1729 ---- `fcompp' float compare */ ! if (unordered_compare) ! output_asm_insn ("fucompp", operands); ! else ! output_asm_insn ("fcompp", operands); } else *************** *** 1708,1714 **** static char buf[100]; ! /* Decide if this is the integer or float compare opcode. */ ! if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT) strcpy (buf, "fcom"); else --- 1731,1740 ---- static char buf[100]; ! /* Decide if this is the integer or float compare opcode, or the ! unordered float compare. */ ! if (unordered_compare) ! strcpy (buf, "fucom"); ! else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT) strcpy (buf, "fcom"); else *************** *** 1728,1735 **** /* Now retrieve the condition code. */ ! output_asm_insn (AS1 (fnsts%W2,%2), operands); ! cc_status.flags |= CC_IN_80387; ! return "sahf"; } --- 1754,1853 ---- /* Now retrieve the condition code. */ ! return output_fp_cc0_set (insn); ! } ! ! /* Output opcodes to transfer the results of FP compare or test INSN ! from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the ! result of the compare or test is unordered, no comparison operator ! succeeds except NE. Return an output template, if any. */ ! ! char * ! output_fp_cc0_set (insn) ! rtx insn; ! { ! rtx xops[3]; ! rtx unordered_label; ! rtx next; ! enum rtx_code code; ! ! xops[0] = gen_rtx (REG, HImode, 0); ! output_asm_insn (AS1 (fnsts%W0,%0), xops); ! ! if (! TARGET_IEEE_FP) ! return "sahf"; ! ! next = next_cc0_user (insn); ! if (GET_CODE (next) == JUMP_INSN ! && GET_CODE (PATTERN (next)) == SET ! && SET_DEST (PATTERN (next)) == pc_rtx ! && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) ! { ! code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); ! } ! else if (GET_CODE (PATTERN (next)) == SET) ! { ! code = GET_CODE (SET_SRC (PATTERN (next))); ! } ! else ! abort (); ! ! xops[0] = gen_rtx (REG, QImode, 0); ! ! switch (code) ! { ! case GT: ! xops[1] = gen_rtx (CONST_INT, VOIDmode, 0x45); ! output_asm_insn (AS2 (and%B0,%1,%h0), xops); ! /* je label */ ! break; ! ! case LT: ! xops[1] = gen_rtx (CONST_INT, VOIDmode, 0x45); ! xops[2] = gen_rtx (CONST_INT, VOIDmode, 0x01); ! output_asm_insn (AS2 (and%B0,%1,%h0), xops); ! output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); ! /* je label */ ! break; ! ! case GE: ! xops[1] = gen_rtx (CONST_INT, VOIDmode, 0x05); ! output_asm_insn (AS2 (and%B0,%1,%h0), xops); ! /* je label */ ! break; ! ! case LE: ! xops[1] = gen_rtx (CONST_INT, VOIDmode, 0x45); ! xops[2] = gen_rtx (CONST_INT, VOIDmode, 0x40); ! output_asm_insn (AS2 (and%B0,%1,%h0), xops); ! output_asm_insn (AS1 (dec%B0,%h0), xops); ! output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); ! /* jb label */ ! break; ! ! case EQ: ! xops[1] = gen_rtx (CONST_INT, VOIDmode, 0x45); ! xops[2] = gen_rtx (CONST_INT, VOIDmode, 0x40); ! output_asm_insn (AS2 (and%B0,%1,%h0), xops); ! output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); ! /* je label */ ! break; ! ! case NE: ! xops[1] = gen_rtx (CONST_INT, VOIDmode, 0x44); ! xops[2] = gen_rtx (CONST_INT, VOIDmode, 0x40); ! output_asm_insn (AS2 (and%B0,%1,%h0), xops); ! output_asm_insn (AS2 (xor%B0,%2,%h0), xops); ! /* jne label */ ! break; ! ! case GTU: ! case LTU: ! case GEU: ! case LEU: ! default: ! abort (); ! } ! RET; } *************** *** 1788,1792 **** if (state == ps_value) { ! fprintf (asm_out_file, "\t%s\t", DEF_ASM_OP); ASM_OUTPUT_LABELREF (asm_out_file, name); fputc (',', asm_out_file); --- 1906,1910 ---- if (state == ps_value) { ! fprintf (asm_out_file, "\t%s\t", SET_ASM_OP); ASM_OUTPUT_LABELREF (asm_out_file, name); fputc (',', asm_out_file); diff -rc2N gcc-2.1/config/i386.h gcc-2.2.1/config/i386.h *** gcc-2.1/config/i386.h Sat Mar 14 00:15:41 1992 --- gcc-2.2.1/config/i386.h Sun May 3 22:40:28 1992 *************** *** 58,61 **** --- 58,70 ---- #define TARGET_REGPARM (target_flags & 020) + /* Put uninitialized locals into bss, not data. + Meaningful only on svr3. */ + #define TARGET_SVR3_SHLIB (target_flags & 040) + + /* Use IEEE floating point comparisons. These handle correctly the cases + where the result of a comparison is unordered. Normally SIGFPE is + generated in such cases, in which case this isn't needed. */ + #define TARGET_IEEE_FP (target_flags & 0100) + /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, *************** *** 74,77 **** --- 83,90 ---- { "regparm", 020}, \ { "noregparm", -020}, \ + { "svr3-shlib", 040}, \ + { "nosvr3-shlib", -040}, \ + { "ieee-fp", 0100}, \ + { "noieee-fp", -0100}, \ { "", TARGET_DEFAULT}} *************** *** 1088,1092 **** switch on CODE. */ ! #define RTX_COSTS(X,CODE) \ case MULT: \ return COSTS_N_INSNS (10); \ --- 1101,1105 ---- switch on CODE. */ ! #define RTX_COSTS(X,CODE,OUTER_CODE) \ case MULT: \ return COSTS_N_INSNS (10); \ *************** *** 1095,1099 **** case MOD: \ case UMOD: \ ! return COSTS_N_INSNS (40); --- 1108,1117 ---- case MOD: \ case UMOD: \ ! return COSTS_N_INSNS (40); \ ! case PLUS: \ ! if (GET_CODE (XEXP (X, 0)) == REG \ ! && GET_CODE (XEXP (X, 1)) == CONST_INT) \ ! return 1; \ ! break; *************** *** 1103,1107 **** return it with a return statement. Otherwise, break from the switch. */ ! #define CONST_COSTS(RTX,CODE) \ case CONST_INT: \ case CONST: \ --- 1121,1125 ---- return it with a return statement. Otherwise, break from the switch. */ ! #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ case CONST: \ *************** *** 1115,1123 **** code == 2 ? 1 : \ 2; \ ! } \ ! case PLUS: \ ! if (GET_CODE (XEXP (RTX, 0)) == REG \ ! && GET_CODE (XEXP (RTX, 1)) == CONST_INT) \ ! return 1; /* Compute the cost of an address. This is meant to approximate the size --- 1133,1137 ---- code == 2 ? 1 : \ 2; \ ! } /* Compute the cost of an address. This is meant to approximate the size *************** *** 1141,1144 **** --- 1155,1185 ---- : 2) + /* Add any extra modes needed to represent the condition code. + + For the i386, we need separate modes when floating-point equality + comparisons are being done. */ + + #define EXTRA_CC_MODES CCFPEQmode + + /* Define the names for the modes specified above. */ + #define EXTRA_CC_NAMES "CCFPEQ" + + /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, + return the mode to be used for the comparison. + + For floating-point equality comparisons, CCFPEQmode should be used. + VOIDmode should be used in all other cases. */ + + #define SELECT_CC_MODE(OP,X) \ + (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ + && ((OP) == EQ || (OP) == NE) ? CCFPEQmode : CCmode) + + /* Define the information needed to generate branch and scc insns. This is + stored from the compare operation. Note that we can't use "rtx" here + since it hasn't been defined! */ + + extern struct rtx_def *i386_compare_op0, *i386_compare_op1; + extern struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); + /* Tell final.c how to eliminate redundant test instructions. */ diff -rc2N gcc-2.1/config/i386.md gcc-2.2.1/config/i386.md *** gcc-2.1/config/i386.md Sat Mar 14 00:15:43 1992 --- gcc-2.2.1/config/i386.md Wed May 27 13:53:14 1992 *************** *** 20,54 **** ! ;;- instruction definitions ! ;;- @@The original PO technology requires these to be ordered by speed, ! ;;- @@ so that assigner will pick the fastest. ! ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ! ;;- When naming insn's (operand 0 of define_insn) be careful about using ! ;;- names from other targets machine descriptions. ! ! ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code ! ;;- updates for most instructions. ! ! ;;- Operand classes for the register allocator: ! ;;- 'a' for eax ! ;;- 'd' for edx ! ;;- 'c' for ecx ! ;;- 'b' for ebx ! ;;- 'f' for anything in FLOAT_REGS ! ;;- 'r' any (non-floating-point) register ! ;;- 'q' regs that allow byte operations (A, B, C and D) ! ;;- 'A' A and D registers ;; the special asm out single letter directives following a '%' are: ! ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of operands[1] ! ;; 's' output a '*' ! ;; 'w' If the operand is a REG, it uses the mode size to determine the ! ;; printing of the reg - ;; "movl MEM,REG / testl REG,REG" is faster on a 486 than "cmpl $0,MEM". ;; But restricting MEM here would mean that gcc could not remove a redundant --- 20,58 ---- ! ;; The original PO technology requires these to be ordered by speed, ! ;; so that assigner will pick the fastest. ! ;; See file "rtl.def" for documentation on define_insn, match_*, et. al. ! ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code ! ;; updates for most instructions. ! ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register ! ;; constraint letters. ;; the special asm out single letter directives following a '%' are: ! ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of ! ;; operands[1]. ! ;; 'L' Print the opcode suffix for a 32-bit integer opcode. ! ;; 'W' Print the opcode suffix for a 16-bit integer opcode. ! ;; 'B' Print the opcode suffix for an 8-bit integer opcode. ! ;; 'S' Print the opcode suffix for a 32-bit float opcode. ! ;; 'Q' Print the opcode suffix for a 64-bit float opcode. ! ! ;; 'b' Print the QImode name of the register for the indicated operand. ! ;; %b0 would print %al if operands[0] is reg 0. ! ;; 'w' Likewise, print the HImode name of the register. ! ;; 'k' Likewise, print the SImode name of the register. ! ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh. ! ;; 'y' Print "st(0)" instead of "st" as a register. ! ! ;; UNSPEC usage: ! ;; 0 This is a `scas' operation. The mode of the UNSPEC is always SImode. ! ;; operand 0 is the memory address to scan. ! ;; operand 1 is a register containing the value to scan for. The mode ! ;; of the scas opcode will be the same as the mode of this operand. ! ;; operand 2 is the known alignment of operand 0. ;; "movl MEM,REG / testl REG,REG" is faster on a 486 than "cmpl $0,MEM". ;; But restricting MEM here would mean that gcc could not remove a redundant *************** *** 59,63 **** ;; be folded while optimizing anyway. ! (define_insn "tstsi" [(set (cc0) (match_operand:SI 0 "nonimmediate_operand" "rm"))] --- 63,71 ---- ;; be folded while optimizing anyway. ! ;; All test insns have expanders that save the operands away without ! ;; actually generating RTL. The bCOND or sCOND (emitted immediately ! ;; after the tstM or cmp) will actually emit the tstM or cmpM. ! ! (define_insn "tstsi_cc" [(set (cc0) (match_operand:SI 0 "nonimmediate_operand" "rm"))] *************** *** 72,76 **** }") ! (define_insn "tsthi" [(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "rm"))] --- 80,95 ---- }") ! (define_expand "tstsi" ! [(set (cc0) ! (match_operand:SI 0 "nonimmediate_operand" ""))] ! "" ! " ! { ! i386_compare_gen = gen_tstsi_cc; ! i386_compare_op0 = operands[0]; ! DONE; ! }") ! ! (define_insn "tsthi_cc" [(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "rm"))] *************** *** 85,89 **** }") ! (define_insn "tstqi" [(set (cc0) (match_operand:QI 0 "nonimmediate_operand" "qm"))] --- 104,119 ---- }") ! (define_expand "tsthi" ! [(set (cc0) ! (match_operand:HI 0 "nonimmediate_operand" ""))] ! "" ! " ! { ! i386_compare_gen = gen_tsthi_cc; ! i386_compare_op0 = operands[0]; ! DONE; ! }") ! ! (define_insn "tstqi_cc" [(set (cc0) (match_operand:QI 0 "nonimmediate_operand" "qm"))] *************** *** 98,106 **** }") ! (define_insn "tstsf" [(set (cc0) (match_operand:SF 0 "register_operand" "f")) (clobber (match_scratch:HI 1 "=a"))] ! "TARGET_80387" "* { --- 128,147 ---- }") ! (define_expand "tstqi" ! [(set (cc0) ! (match_operand:QI 0 "nonimmediate_operand" ""))] ! "" ! " ! { ! i386_compare_gen = gen_tstqi_cc; ! i386_compare_op0 = operands[0]; ! DONE; ! }") ! ! (define_insn "tstsf_cc" [(set (cc0) (match_operand:SF 0 "register_operand" "f")) (clobber (match_scratch:HI 1 "=a"))] ! "TARGET_80387 && ! TARGET_IEEE_FP" "* { *************** *** 109,113 **** output_asm_insn (\"ftst\", operands); - cc_status.flags |= CC_IN_80387; if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) --- 150,153 ---- *************** *** 114,127 **** output_asm_insn (AS1 (fstp,%y0), operands); ! output_asm_insn (AS1 (fnsts%W1,%1), operands); ! return \"sahf\"; }") ! (define_insn "tstdf" [(set (cc0) (match_operand:DF 0 "register_operand" "f")) (clobber (match_scratch:HI 1 "=a"))] ! "TARGET_80387" "* { --- 154,180 ---- output_asm_insn (AS1 (fstp,%y0), operands); ! return (char *) output_fp_cc0_set (insn); ! }") ! ! ;; Don't generate tstsf if generating IEEE code, since the `ftst' opcode ! ;; isn't IEEE compliant. ! (define_expand "tstsf" ! [(parallel [(set (cc0) ! (match_operand:SF 0 "register_operand" "")) ! (clobber (match_scratch:HI 1 ""))])] ! "TARGET_80387 && ! TARGET_IEEE_FP" ! " ! { ! i386_compare_gen = gen_tstsf_cc; ! i386_compare_op0 = operands[0]; ! DONE; }") ! (define_insn "tstdf_cc" [(set (cc0) (match_operand:DF 0 "register_operand" "f")) (clobber (match_scratch:HI 1 "=a"))] ! "TARGET_80387 && ! TARGET_IEEE_FP" "* { *************** *** 130,134 **** output_asm_insn (\"ftst\", operands); - cc_status.flags |= CC_IN_80387; if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) --- 183,186 ---- *************** *** 135,149 **** output_asm_insn (AS1 (fstp,%y0), operands); ! output_asm_insn (AS1 (fnsts%W1,%1), operands); ! return \"sahf\"; }") ! ;;- compare instructions ! (define_insn "cmpsi" [(set (cc0) ! (compare (match_operand:SI 0 "nonimmediate_operand" "mr,ri") ! (match_operand:SI 1 "general_operand" "ri,mr")))] "" "* --- 187,215 ---- output_asm_insn (AS1 (fstp,%y0), operands); ! return (char *) output_fp_cc0_set (insn); ! }") ! ! ;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode ! ;; isn't IEEE compliant. ! (define_expand "tstdf" ! [(parallel [(set (cc0) ! (match_operand:DF 0 "register_operand" "")) ! (clobber (match_scratch:HI 1 ""))])] ! "TARGET_80387 && ! TARGET_IEEE_FP" ! " ! { ! i386_compare_gen = gen_tstdf_cc; ! i386_compare_op0 = operands[0]; ! DONE; }") ! ;;- compare instructions. See comments above tstM patterns about ! ;; expansion of these insns. ! (define_insn "cmpsi_cc" [(set (cc0) ! (compare:CC (match_operand:SI 0 "nonimmediate_operand" "mr,ri") ! (match_operand:SI 1 "general_operand" "ri,mr")))] "" "* *************** *** 157,164 **** }") ! (define_insn "cmphi" [(set (cc0) ! (compare (match_operand:HI 0 "nonimmediate_operand" "mr,ri") ! (match_operand:HI 1 "general_operand" "ri,mr")))] "" "* --- 223,243 ---- }") ! (define_expand "cmpsi" ! [(set (cc0) ! (compare:CC (match_operand:SI 0 "nonimmediate_operand" "") ! (match_operand:SI 1 "general_operand" "")))] ! "" ! " ! { ! i386_compare_gen = gen_cmpsi_cc; ! i386_compare_op0 = operands[0]; ! i386_compare_op1 = operands[1]; ! DONE; ! }") ! ! (define_insn "cmphi_cc" [(set (cc0) ! (compare:CC (match_operand:HI 0 "nonimmediate_operand" "mr,ri") ! (match_operand:HI 1 "general_operand" "ri,mr")))] "" "* *************** *** 172,179 **** }") ! (define_insn "cmpqi" [(set (cc0) ! (compare (match_operand:QI 0 "nonimmediate_operand" "qn,mq") ! (match_operand:QI 1 "general_operand" "qm,nq")))] "" "* --- 251,271 ---- }") ! (define_expand "cmphi" ! [(set (cc0) ! (compare:CC (match_operand:HI 0 "nonimmediate_operand" "") ! (match_operand:HI 1 "general_operand" "")))] ! "" ! " ! { ! i386_compare_gen = gen_cmphi_cc; ! i386_compare_op0 = operands[0]; ! i386_compare_op1 = operands[1]; ! DONE; ! }") ! ! (define_insn "cmpqi_cc" [(set (cc0) ! (compare:CC (match_operand:QI 0 "nonimmediate_operand" "qn,mq") ! (match_operand:QI 1 "general_operand" "qm,nq")))] "" "* *************** *** 187,190 **** --- 279,295 ---- }") + (define_expand "cmpqi" + [(set (cc0) + (compare:CC (match_operand:QI 0 "nonimmediate_operand" "") + (match_operand:QI 1 "general_operand" "")))] + "" + " + { + i386_compare_gen = gen_cmpqi_cc; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; + }") + ;; These implement float point compares. For each of DFmode and ;; SFmode, there is the normal insn, and an insn where the second operand *************** *** 191,217 **** ;; is converted to the desired mode. ! (define_expand "cmpdf" ! [(parallel [(set (cc0) ! (compare (match_operand:DF 0 "nonimmediate_operand" "") ! (match_operand:DF 1 "nonimmediate_operand" ""))) ! (clobber (match_scratch:HI 2 ""))])] "TARGET_80387" ! "") ! (define_expand "cmpsf" ! [(parallel [(set (cc0) ! (compare (match_operand:SF 0 "nonimmediate_operand" "") ! (match_operand:SF 1 "nonimmediate_operand" ""))) ! (clobber (match_scratch:HI 2 ""))])] "TARGET_80387" ! "") ! ;; The `ble' and `blt' patterns can reverse a compare, so we must allow ! ;; an immediate operand as operand 0 in the recognizers below. (define_insn "" [(set (cc0) ! (compare (match_operand:DF 0 "general_operand" "f") ! (match_operand:DF 1 "general_operand" "fm"))) (clobber (match_scratch:HI 2 "=a"))] "TARGET_80387" --- 296,329 ---- ;; is converted to the desired mode. ! (define_insn "cmpdf_cc" ! [(set (cc0) ! (compare:CC (match_operand:DF 0 "register_operand" "f") ! (match_operand:DF 1 "nonimmediate_operand" "fm"))) ! (clobber (match_scratch:HI 2 "=a"))] "TARGET_80387" ! "* return (char *) output_float_compare (insn, operands);") ! (define_insn "" ! [(set (cc0) ! (compare:CC (match_operand:DF 0 "register_operand" "f,f") ! (float:DF ! (match_operand:SI 1 "nonimmediate_operand" "m,!*r")))) ! (clobber (match_scratch:HI 2 "=a,a"))] "TARGET_80387" ! "* return (char *) output_float_compare (insn, operands);") ! (define_insn "" ! [(set (cc0) ! (compare:CC (match_operand:DF 0 "register_operand" "f,f") ! (float_extend:DF ! (match_operand:SF 1 "nonimmediate_operand" "fm,!*r")))) ! (clobber (match_scratch:HI 2 "=a,a"))] ! "TARGET_80387" ! "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) ! (compare:CCFPEQ (match_operand:DF 0 "register_operand" "f") ! (match_operand:DF 1 "register_operand" "f"))) (clobber (match_scratch:HI 2 "=a"))] "TARGET_80387" *************** *** 220,226 **** (define_insn "" [(set (cc0) ! (compare (match_operand:DF 0 "general_operand" "f,f") ! (float:DF (match_operand:SI 1 "general_operand" "m,!*r")))) ! (clobber (match_scratch:HI 2 "=a,a"))] "TARGET_80387" "* return (char *) output_float_compare (insn, operands);") --- 332,347 ---- (define_insn "" [(set (cc0) ! (compare:CCFPEQ (match_operand:DF 0 "register_operand" "f") ! (float_extend:DF ! (match_operand:SF 1 "register_operand" "f")))) ! (clobber (match_scratch:HI 2 "=a"))] ! "TARGET_80387" ! "* return (char *) output_float_compare (insn, operands);") ! ! (define_insn "cmpsf_cc" ! [(set (cc0) ! (compare:CC (match_operand:SF 0 "register_operand" "f") ! (match_operand:SF 1 "nonimmediate_operand" "fm"))) ! (clobber (match_scratch:HI 2 "=a"))] "TARGET_80387" "* return (char *) output_float_compare (insn, operands);") *************** *** 228,234 **** (define_insn "" [(set (cc0) ! (compare (match_operand:DF 0 "general_operand" "f,f") ! (float_extend:DF ! (match_operand:SF 1 "general_operand" "fm,!*r")))) (clobber (match_scratch:HI 2 "=a,a"))] "TARGET_80387" --- 349,355 ---- (define_insn "" [(set (cc0) ! (compare:CC (match_operand:SF 0 "register_operand" "f,f") ! (float:SF ! (match_operand:SI 1 "nonimmediate_operand" "m,!*r")))) (clobber (match_scratch:HI 2 "=a,a"))] "TARGET_80387" *************** *** 237,242 **** (define_insn "" [(set (cc0) ! (compare (match_operand:SF 0 "general_operand" "f") ! (match_operand:SF 1 "general_operand" "fm"))) (clobber (match_scratch:HI 2 "=a"))] "TARGET_80387" --- 358,363 ---- (define_insn "" [(set (cc0) ! (compare:CCFPEQ (match_operand:SF 0 "register_operand" "f") ! (match_operand:SF 1 "register_operand" "f"))) (clobber (match_scratch:HI 2 "=a"))] "TARGET_80387" *************** *** 243,253 **** "* return (char *) output_float_compare (insn, operands);") ! (define_insn "" [(set (cc0) ! (compare (match_operand:SF 0 "general_operand" "f,f") ! (float:SF (match_operand:SI 1 "general_operand" "m,!*r")))) ! (clobber (match_scratch:HI 2 "=a,a"))] "TARGET_80387" ! "* return (char *) output_float_compare (insn, operands);") ;; logical compare --- 364,418 ---- "* return (char *) output_float_compare (insn, operands);") ! (define_expand "cmpdf" [(set (cc0) ! (compare:CC (match_operand:DF 0 "register_operand" "") ! (match_operand:DF 1 "nonimmediate_operand" "")))] "TARGET_80387" ! " ! { ! i386_compare_gen = gen_cmpdf_cc; ! i386_compare_gen_eq = gen_cmpdf_ccfpeq; ! i386_compare_op0 = operands[0]; ! i386_compare_op1 = operands[1]; ! DONE; ! }") ! ! (define_expand "cmpsf" ! [(set (cc0) ! (compare:CC (match_operand:SF 0 "register_operand" "") ! (match_operand:SF 1 "nonimmediate_operand" "")))] ! "TARGET_80387" ! " ! { ! i386_compare_gen = gen_cmpsf_cc; ! i386_compare_gen_eq = gen_cmpsf_ccfpeq; ! i386_compare_op0 = operands[0]; ! i386_compare_op1 = operands[1]; ! DONE; ! }") ! ! (define_expand "cmpdf_ccfpeq" ! [(parallel [(set (cc0) ! (compare:CCFPEQ (match_operand:DF 0 "register_operand" "") ! (match_operand:DF 1 "register_operand" ""))) ! (clobber (match_scratch:HI 2 ""))])] ! "TARGET_80387" ! " ! { ! if (! register_operand (operands[1], DFmode)) ! operands[1] = copy_to_mode_reg (DFmode, operands[1]); ! }") ! ! (define_expand "cmpsf_ccfpeq" ! [(parallel [(set (cc0) ! (compare:CCFPEQ (match_operand:SF 0 "register_operand" "") ! (match_operand:SF 1 "register_operand" ""))) ! (clobber (match_scratch:HI 2 ""))])] ! "TARGET_80387" ! " ! { ! if (! register_operand (operands[1], SFmode)) ! operands[1] = copy_to_mode_reg (SFmode, operands[1]); ! }") ;; logical compare *************** *** 1000,1008 **** (define_expand "fixuns_truncdfsi2" ! [(parallel [(set (match_dup 3) ! (fix:DI ! (fix:DF (match_operand:DF 1 "register_operand" "")))) (clobber (match_scratch:HI 2 "")) ! (clobber (match_dup 1))]) (set (match_operand:SI 0 "general_operand" "") (match_dup 4))] --- 1165,1174 ---- (define_expand "fixuns_truncdfsi2" ! [(set (match_dup 5) ! (match_operand:DF 1 "register_operand" "")) ! (parallel [(set (match_dup 3) ! (fix:DI (fix:DF (match_dup 5)))) (clobber (match_scratch:HI 2 "")) ! (clobber (match_dup 5))]) (set (match_operand:SI 0 "general_operand" "") (match_dup 4))] *************** *** 1012,1023 **** operands[3] = gen_reg_rtx (DImode); operands[4] = gen_lowpart (SImode, operands[3]); }") (define_expand "fixuns_truncsfsi2" ! [(parallel [(set (match_dup 3) ! (fix:DI ! (fix:SF (match_operand:SF 1 "register_operand" "")))) (clobber (match_scratch:HI 2 "")) ! (clobber (match_dup 1))]) (set (match_operand:SI 0 "general_operand" "") (match_dup 4))] --- 1178,1191 ---- operands[3] = gen_reg_rtx (DImode); operands[4] = gen_lowpart (SImode, operands[3]); + operands[5] = gen_reg_rtx (DFmode); }") (define_expand "fixuns_truncsfsi2" ! [(set (match_dup 5) ! (match_operand:SF 1 "register_operand" "")) ! (parallel [(set (match_dup 3) ! (fix:DI (fix:SF (match_dup 5)))) (clobber (match_scratch:HI 2 "")) ! (clobber (match_dup 5))]) (set (match_operand:SI 0 "general_operand" "") (match_dup 4))] *************** *** 1027,1030 **** --- 1195,1199 ---- operands[3] = gen_reg_rtx (DImode); operands[4] = gen_lowpart (SImode, operands[3]); + operands[5] = gen_reg_rtx (SFmode); }") *************** *** 1032,1040 **** (define_expand "fix_truncdfdi2" ! [(parallel [(set (match_operand:DI 0 "general_operand" "") ! (fix:DI ! (fix:DF (match_operand:DF 1 "register_operand" "")))) (clobber (match_scratch:HI 2 "")) ! (clobber (match_dup 1))])] "TARGET_80387" " --- 1201,1210 ---- (define_expand "fix_truncdfdi2" ! [(set (match_dup 3) ! (match_operand:DF 1 "register_operand" "")) ! (parallel [(set (match_operand:DI 0 "general_operand" "") ! (fix:DI (fix:DF (match_dup 3)))) (clobber (match_scratch:HI 2 "")) ! (clobber (match_dup 3))])] "TARGET_80387" " *************** *** 1041,1052 **** { operands[1] = copy_to_mode_reg (DFmode, operands[1]); }") (define_expand "fix_truncsfdi2" ! [(parallel [(set (match_operand:DI 0 "general_operand" "") ! (fix:DI ! (fix:SF (match_operand:SF 1 "register_operand" "")))) (clobber (match_scratch:HI 2 "")) ! (clobber (match_dup 1))])] "TARGET_80387" " --- 1211,1224 ---- { operands[1] = copy_to_mode_reg (DFmode, operands[1]); + operands[3] = gen_reg_rtx (DFmode); }") (define_expand "fix_truncsfdi2" ! [(set (match_dup 3) ! (match_operand:SF 1 "register_operand" "")) ! (parallel [(set (match_operand:DI 0 "general_operand" "") ! (fix:DI (fix:SF (match_dup 3)))) (clobber (match_scratch:HI 2 "")) ! (clobber (match_dup 3))])] "TARGET_80387" " *************** *** 1053,1056 **** --- 1225,1229 ---- { operands[1] = copy_to_mode_reg (SFmode, operands[1]); + operands[3] = gen_reg_rtx (SFmode); }") *************** *** 1443,1447 **** }") ! (define_insn "mulqihi3_1" [(set (match_operand:HI 0 "general_operand" "=a") (mult:SI (zero_extend:HI --- 1616,1620 ---- }") ! (define_insn "" [(set (match_operand:HI 0 "general_operand" "=a") (mult:SI (zero_extend:HI *************** *** 2069,2077 **** ;; than 31. ! (define_insn "ashldi3" ! [(set (match_operand:DI 0 "general_operand" "=&r") ! (ashift:DI (match_operand:DI 1 "general_operand" "0") ! (match_operand:QI 2 "general_operand" "cJ"))) ! (clobber (match_dup 2))] "" "* --- 2242,2269 ---- ;; than 31. ! (define_expand "ashldi3" ! [(set (match_operand:DI 0 "register_operand" "") ! (ashift:DI (match_operand:DI 1 "register_operand" "") ! (match_operand:QI 2 "nonmemory_operand" "")))] ! "" ! " ! { ! if (GET_CODE (operands[2]) != CONST_INT ! || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) ! { ! operands[2] = copy_to_mode_reg (QImode, operands[2]); ! emit_insn (gen_ashldi3_non_const_int (operands[0], operands[1], ! operands[2])); ! } ! else ! emit_insn (gen_ashldi3_const_int (operands[0], operands[1], operands[2])); ! ! DONE; ! }") ! ! (define_insn "ashldi3_const_int" ! [(set (match_operand:DI 0 "register_operand" "=&r") ! (ashift:DI (match_operand:DI 1 "register_operand" "0") ! (match_operand:QI 2 "const_int_operand" "J")))] "" "* *************** *** 2087,2126 **** xops[3] = high[0]; ! if (REG_P (xops[0])) /* If shift count in %cl */ { ! output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ ! output_asm_insn (AS2 (shld%L3,%2,%3), xops); ! output_asm_insn (AS2 (sal%L2,%0,%2), xops); ! output_asm_insn (AS2 (shld%L3,%2,%3), xops); output_asm_insn (AS2 (sal%L2,%0,%2), xops); ! xops[1] = gen_rtx (CONST_INT, VOIDmode, 7); /* shift count & 1 */ ! output_asm_insn (AS2 (shr%B0,%1,%0), xops); ! output_asm_insn (AS2 (shld%L3,%2,%3), xops); ! output_asm_insn (AS2 (sal%L2,%0,%2), xops); ! } ! else if (GET_CODE (xops[0]) == CONST_INT) ! { ! if (INTVAL (xops[0]) > 31) ! { ! output_asm_insn (AS2 (mov%L3,%2,%3), xops); /* Fast shift by 32 */ ! output_asm_insn (AS2 (xor%L2,%2,%2), xops); ! if (INTVAL (xops[0]) > 32) ! { ! xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xops[0]) - 32); ! output_asm_insn (AS2 (sal%3,%0,%3), xops); /* Remaining shift */ ! } ! } ! else ! { ! output_asm_insn (AS3 (shld%L3,%0,%2,%3), xops); ! output_asm_insn (AS2 (sal%L2,%0,%2), xops); ! } ! } RET; }") --- 2279,2334 ---- xops[3] = high[0]; ! if (INTVAL (xops[0]) > 31) { ! output_asm_insn (AS2 (mov%L3,%2,%3), xops); /* Fast shift by 32 */ ! output_asm_insn (AS2 (xor%L2,%2,%2), xops); ! if (INTVAL (xops[0]) > 32) ! { ! xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xops[0]) - 32); ! ! output_asm_insn (AS2 (sal%L3,%0,%3), xops); /* Remaining shift */ ! } ! } ! else ! { ! output_asm_insn (AS3 (shld%L3,%0,%2,%3), xops); output_asm_insn (AS2 (sal%L2,%0,%2), xops); + } + RET; + }") ! (define_insn "ashldi3_non_const_int" ! [(set (match_operand:DI 0 "register_operand" "=&r") ! (ashift:DI (match_operand:DI 1 "register_operand" "0") ! (match_operand:QI 2 "register_operand" "c"))) ! (clobber (match_dup 2))] ! "" ! "* ! { ! rtx xops[4], low[1], high[1]; ! CC_STATUS_INIT; ! split_di (operands, 1, low, high); ! xops[0] = operands[2]; ! xops[1] = const1_rtx; ! xops[2] = low[0]; ! xops[3] = high[0]; ! output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ ! output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); ! output_asm_insn (AS2 (sal%L2,%0,%2), xops); ! output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); ! output_asm_insn (AS2 (sal%L2,%0,%2), xops); ! ! xops[1] = gen_rtx (CONST_INT, VOIDmode, 7); /* shift count & 1 */ ! ! output_asm_insn (AS2 (shr%B0,%1,%0), xops); ! ! output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); ! output_asm_insn (AS2 (sal%L2,%0,%2), xops); ! RET; }") *************** *** 2133,2137 **** [(set (match_operand:SI 0 "general_operand" "=r,rm") (ashift:SI (match_operand:SI 1 "general_operand" "r,0") ! (match_operand:SI 2 "general_operand" "M,cI")))] "" "* --- 2341,2345 ---- [(set (match_operand:SI 0 "general_operand" "=r,rm") (ashift:SI (match_operand:SI 1 "general_operand" "r,0") ! (match_operand:SI 2 "nonmemory_operand" "M,cI")))] "" "* *************** *** 2166,2170 **** [(set (match_operand:HI 0 "general_operand" "=rm") (ashift:HI (match_operand:HI 1 "general_operand" "0") ! (match_operand:HI 2 "general_operand" "cI")))] "" "* --- 2374,2378 ---- [(set (match_operand:HI 0 "general_operand" "=rm") (ashift:HI (match_operand:HI 1 "general_operand" "0") ! (match_operand:HI 2 "nonmemory_operand" "cI")))] "" "* *************** *** 2182,2186 **** [(set (match_operand:QI 0 "general_operand" "=qm") (ashift:QI (match_operand:QI 1 "general_operand" "0") ! (match_operand:QI 2 "general_operand" "cI")))] "" "* --- 2390,2394 ---- [(set (match_operand:QI 0 "general_operand" "=qm") (ashift:QI (match_operand:QI 1 "general_operand" "0") ! (match_operand:QI 2 "nonmemory_operand" "cI")))] "" "* *************** *** 2197,2209 **** ;; See comment above `ashldi3' about how this works. ! (define_insn "ashrdi3" ! [(set (match_operand:DI 0 "general_operand" "=&r") ! (ashiftrt:DI (match_operand:DI 1 "general_operand" "0") ! (match_operand:QI 2 "general_operand" "cJ"))) ! (clobber (match_dup 2))] "" "* { ! rtx xops[5], low[1], high[1]; CC_STATUS_INIT; --- 2405,2436 ---- ;; See comment above `ashldi3' about how this works. ! (define_expand "ashrdi3" ! [(set (match_operand:DI 0 "register_operand" "") ! (ashiftrt:DI (match_operand:DI 1 "register_operand" "") ! (match_operand:QI 2 "nonmemory_operand" "")))] ! "" ! " ! { ! if (GET_CODE (operands[2]) != CONST_INT ! || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) ! { ! operands[2] = copy_to_mode_reg (QImode, operands[2]); ! emit_insn (gen_ashrdi3_non_const_int (operands[0], operands[1], ! operands[2])); ! } ! else ! emit_insn (gen_ashrdi3_const_int (operands[0], operands[1], operands[2])); ! ! DONE; ! }") ! ! (define_insn "ashrdi3_const_int" ! [(set (match_operand:DI 0 "register_operand" "=&r") ! (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") ! (match_operand:QI 2 "const_int_operand" "J")))] "" "* { ! rtx xops[4], low[1], high[1]; CC_STATUS_INIT; *************** *** 2215,2255 **** xops[3] = high[0]; ! if (REG_P (xops[0])) /* If shift count in %cl */ { ! output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ ! output_asm_insn (AS2 (shrd%L2,%3,%2), xops); ! output_asm_insn (AS2 (sar%L3,%0,%3), xops); ! output_asm_insn (AS2 (shrd%L2,%3,%2), xops); output_asm_insn (AS2 (sar%L3,%0,%3), xops); ! xops[1] = gen_rtx (CONST_INT, VOIDmode, 7); /* shift count & 1 */ ! output_asm_insn (AS2 (shr%B0,%1,%0), xops); ! output_asm_insn (AS2 (shrd%L2,%3,%2), xops); ! output_asm_insn (AS2 (sar%L3,%0,%3), xops); ! } ! else if (GET_CODE (xops[0]) == CONST_INT) ! { ! if (INTVAL (xops[0]) > 31) ! { ! xops[1] = gen_rtx (CONST_INT, VOIDmode, 31); ! output_asm_insn (AS2 (mov%L2,%3,%2), xops); ! output_asm_insn (AS2 (sar%L3,%1,%3), xops); /* shift by 32 */ ! if (INTVAL (xops[0]) > 32) ! { ! xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xops[0]) - 32); ! output_asm_insn (AS2 (sar%2,%0,%2), xops); /* Remaining shift */ ! } ! } ! else ! { ! output_asm_insn (AS3 (shrd%L2,%0,%3,%2), xops); ! output_asm_insn (AS2 (sar%L3,%0,%3), xops); ! } ! } RET; }") --- 2442,2499 ---- xops[3] = high[0]; ! if (INTVAL (xops[0]) > 31) { ! xops[1] = gen_rtx (CONST_INT, VOIDmode, 31); ! output_asm_insn (AS2 (mov%L2,%3,%2), xops); ! output_asm_insn (AS2 (sar%L3,%1,%3), xops); /* shift by 32 */ ! if (INTVAL (xops[0]) > 32) ! { ! xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xops[0]) - 32); ! ! output_asm_insn (AS2 (sar%2,%0,%2), xops); /* Remaining shift */ ! } ! } ! else ! { ! output_asm_insn (AS3 (shrd%L2,%0,%3,%2), xops); output_asm_insn (AS2 (sar%L3,%0,%3), xops); + } ! RET; ! }") ! (define_insn "ashrdi3_non_const_int" ! [(set (match_operand:DI 0 "register_operand" "=&r") ! (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") ! (match_operand:QI 2 "register_operand" "c"))) ! (clobber (match_dup 2))] ! "" ! "* ! { ! rtx xops[4], low[1], high[1]; ! CC_STATUS_INIT; ! split_di (operands, 1, low, high); ! xops[0] = operands[2]; ! xops[1] = const1_rtx; ! xops[2] = low[0]; ! xops[3] = high[0]; ! output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ ! ! output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); ! output_asm_insn (AS2 (sar%L3,%0,%3), xops); ! output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); ! output_asm_insn (AS2 (sar%L3,%0,%3), xops); ! ! xops[1] = gen_rtx (CONST_INT, VOIDmode, 7); /* shift count & 1 */ ! ! output_asm_insn (AS2 (shr%B0,%1,%0), xops); ! ! output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); ! output_asm_insn (AS2 (sar%L3,%0,%3), xops); ! RET; }") *************** *** 2258,2262 **** [(set (match_operand:SI 0 "general_operand" "=rm") (ashiftrt:SI (match_operand:SI 1 "general_operand" "0") ! (match_operand:SI 2 "general_operand" "cI")))] "" "* --- 2502,2506 ---- [(set (match_operand:SI 0 "general_operand" "=rm") (ashiftrt:SI (match_operand:SI 1 "general_operand" "0") ! (match_operand:SI 2 "nonmemory_operand" "cI")))] "" "* *************** *** 2271,2275 **** [(set (match_operand:HI 0 "general_operand" "=rm") (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") ! (match_operand:HI 2 "general_operand" "cI")))] "" "* --- 2515,2519 ---- [(set (match_operand:HI 0 "general_operand" "=rm") (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") ! (match_operand:HI 2 "nonmemory_operand" "cI")))] "" "* *************** *** 2284,2288 **** [(set (match_operand:QI 0 "general_operand" "=qm") (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") ! (match_operand:QI 2 "general_operand" "cI")))] "" "* --- 2528,2532 ---- [(set (match_operand:QI 0 "general_operand" "=qm") (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") ! (match_operand:QI 2 "nonmemory_operand" "cI")))] "" "* *************** *** 2298,2310 **** ;; See comment above `ashldi3' about how this works. ! (define_insn "lshrdi3" ! [(set (match_operand:DI 0 "general_operand" "=&r") ! (lshiftrt:DI (match_operand:DI 1 "general_operand" "0") ! (match_operand:QI 2 "general_operand" "cJ"))) ! (clobber (match_dup 2))] "" "* { ! rtx xops[5], low[1], high[1]; CC_STATUS_INIT; --- 2542,2573 ---- ;; See comment above `ashldi3' about how this works. ! (define_expand "lshrdi3" ! [(set (match_operand:DI 0 "register_operand" "") ! (lshiftrt:DI (match_operand:DI 1 "register_operand" "") ! (match_operand:QI 2 "nonmemory_operand" "")))] ! "" ! " ! { ! if (GET_CODE (operands[2]) != CONST_INT ! || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) ! { ! operands[2] = copy_to_mode_reg (QImode, operands[2]); ! emit_insn (gen_lshrdi3_non_const_int (operands[0], operands[1], ! operands[2])); ! } ! else ! emit_insn (gen_lshrdi3_const_int (operands[0], operands[1], operands[2])); ! ! DONE; ! }") ! ! (define_insn "lshrdi3_const_int" ! [(set (match_operand:DI 0 "register_operand" "=&r") ! (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") ! (match_operand:QI 2 "const_int_operand" "J")))] "" "* { ! rtx xops[4], low[1], high[1]; CC_STATUS_INIT; *************** *** 2316,2355 **** xops[3] = high[0]; ! if (REG_P (xops[0])) /* If shift count in %cl */ { ! output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ ! output_asm_insn (AS2 (shrd%L2,%3,%2), xops); ! output_asm_insn (AS2 (shr%L3,%0,%3), xops); ! output_asm_insn (AS2 (shrd%L2,%3,%2), xops); output_asm_insn (AS2 (shr%L3,%0,%3), xops); ! xops[1] = gen_rtx (CONST_INT, VOIDmode, 7); /* shift count & 1 */ ! output_asm_insn (AS2 (shr%B0,%1,%0), xops); ! output_asm_insn (AS2 (shrd%L2,%3,%2), xops); ! output_asm_insn (AS2 (shr%L3,%0,%3), xops); ! } ! else if (GET_CODE (xops[0]) == CONST_INT) ! { ! if (INTVAL (xops[0]) > 31) ! { ! output_asm_insn (AS2 (mov%L2,%3,%2), xops); /* Fast shift by 32 */ ! output_asm_insn (AS2 (xor%L3,%3,%3), xops); ! if (INTVAL (xops[0]) > 32) ! { ! xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xops[0]) - 32); ! output_asm_insn (AS2 (shr%2,%0,%2), xops); /* Remaining shift */ ! } ! } ! else ! { ! output_asm_insn (AS3 (shrd%L2,%0,%3,%2), xops); ! output_asm_insn (AS2 (shr%L3,%0,%3), xops); ! } ! } RET; }") --- 2579,2635 ---- xops[3] = high[0]; ! if (INTVAL (xops[0]) > 31) { ! output_asm_insn (AS2 (mov%L2,%3,%2), xops); /* Fast shift by 32 */ ! output_asm_insn (AS2 (xor%L3,%3,%3), xops); ! if (INTVAL (xops[0]) > 32) ! { ! xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xops[0]) - 32); ! ! output_asm_insn (AS2 (shr%2,%0,%2), xops); /* Remaining shift */ ! } ! } ! else ! { ! output_asm_insn (AS3 (shrd%L2,%0,%3,%2), xops); output_asm_insn (AS2 (shr%L3,%0,%3), xops); + } ! RET; ! }") ! (define_insn "lshrdi3_non_const_int" ! [(set (match_operand:DI 0 "register_operand" "=&r") ! (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") ! (match_operand:QI 2 "register_operand" "c"))) ! (clobber (match_dup 2))] ! "" ! "* ! { ! rtx xops[4], low[1], high[1]; ! CC_STATUS_INIT; ! split_di (operands, 1, low, high); ! xops[0] = operands[2]; ! xops[1] = const1_rtx; ! xops[2] = low[0]; ! xops[3] = high[0]; ! output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ ! ! output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); ! output_asm_insn (AS2 (shr%L3,%0,%3), xops); ! output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); ! output_asm_insn (AS2 (shr%L3,%0,%3), xops); ! ! xops[1] = gen_rtx (CONST_INT, VOIDmode, 7); /* shift count & 1 */ ! ! output_asm_insn (AS2 (shr%B0,%1,%0), xops); ! ! output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); ! output_asm_insn (AS2 (shr%L3,%0,%3), xops); ! RET; }") *************** *** 2358,2362 **** [(set (match_operand:SI 0 "general_operand" "=rm") (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") ! (match_operand:SI 2 "general_operand" "cI")))] "" "* --- 2638,2642 ---- [(set (match_operand:SI 0 "general_operand" "=rm") (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") ! (match_operand:SI 2 "nonmemory_operand" "cI")))] "" "* *************** *** 2371,2375 **** [(set (match_operand:HI 0 "general_operand" "=rm") (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") ! (match_operand:HI 2 "general_operand" "cI")))] "" "* --- 2651,2655 ---- [(set (match_operand:HI 0 "general_operand" "=rm") (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") ! (match_operand:HI 2 "nonmemory_operand" "cI")))] "" "* *************** *** 2384,2388 **** [(set (match_operand:QI 0 "general_operand" "=qm") (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") ! (match_operand:QI 2 "general_operand" "cI")))] "" "* --- 2664,2668 ---- [(set (match_operand:QI 0 "general_operand" "=qm") (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") ! (match_operand:QI 2 "nonmemory_operand" "cI")))] "" "* *************** *** 2399,2403 **** [(set (match_operand:SI 0 "general_operand" "=rm") (rotate:SI (match_operand:SI 1 "general_operand" "0") ! (match_operand:SI 2 "general_operand" "cI")))] "" "* --- 2679,2683 ---- [(set (match_operand:SI 0 "general_operand" "=rm") (rotate:SI (match_operand:SI 1 "general_operand" "0") ! (match_operand:SI 2 "nonmemory_operand" "cI")))] "" "* *************** *** 2412,2416 **** [(set (match_operand:HI 0 "general_operand" "=rm") (rotate:HI (match_operand:HI 1 "general_operand" "0") ! (match_operand:HI 2 "general_operand" "cI")))] "" "* --- 2692,2696 ---- [(set (match_operand:HI 0 "general_operand" "=rm") (rotate:HI (match_operand:HI 1 "general_operand" "0") ! (match_operand:HI 2 "nonmemory_operand" "cI")))] "" "* *************** *** 2425,2429 **** [(set (match_operand:QI 0 "general_operand" "=qm") (rotate:QI (match_operand:QI 1 "general_operand" "0") ! (match_operand:QI 2 "general_operand" "cI")))] "" "* --- 2705,2709 ---- [(set (match_operand:QI 0 "general_operand" "=qm") (rotate:QI (match_operand:QI 1 "general_operand" "0") ! (match_operand:QI 2 "nonmemory_operand" "cI")))] "" "* *************** *** 2438,2442 **** [(set (match_operand:SI 0 "general_operand" "=rm") (rotatert:SI (match_operand:SI 1 "general_operand" "0") ! (match_operand:SI 2 "general_operand" "cI")))] "" "* --- 2718,2722 ---- [(set (match_operand:SI 0 "general_operand" "=rm") (rotatert:SI (match_operand:SI 1 "general_operand" "0") ! (match_operand:SI 2 "nonmemory_operand" "cI")))] "" "* *************** *** 2451,2455 **** [(set (match_operand:HI 0 "general_operand" "=rm") (rotatert:HI (match_operand:HI 1 "general_operand" "0") ! (match_operand:HI 2 "general_operand" "cI")))] "" "* --- 2731,2735 ---- [(set (match_operand:HI 0 "general_operand" "=rm") (rotatert:HI (match_operand:HI 1 "general_operand" "0") ! (match_operand:HI 2 "nonmemory_operand" "cI")))] "" "* *************** *** 2464,2468 **** [(set (match_operand:QI 0 "general_operand" "=qm") (rotatert:QI (match_operand:QI 1 "general_operand" "0") ! (match_operand:QI 2 "general_operand" "cI")))] "" "* --- 2744,2748 ---- [(set (match_operand:QI 0 "general_operand" "=qm") (rotatert:QI (match_operand:QI 1 "general_operand" "0") ! (match_operand:QI 2 "nonmemory_operand" "cI")))] "" "* *************** *** 2566,2572 **** [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+rm") (const_int 1) ! (match_operand:SI 2 "nonimmediate_operand" "r")) ! (match_operand:SI 3 "immediate_operand" "i"))] ! "! TARGET_486" "* { --- 2846,2852 ---- [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+rm") (const_int 1) ! (match_operand:SI 2 "general_operand" "r")) ! (match_operand:SI 3 "const_int_operand" "n"))] ! "! TARGET_486 && GET_CODE (operands[2]) != CONST_INT" "* { *************** *** 2586,2590 **** (match_operand:SI 1 "general_operand" "r")) (match_dup 0)))] ! "! TARGET_486" "* { --- 2866,2870 ---- (match_operand:SI 1 "general_operand" "r")) (match_dup 0)))] ! "! TARGET_486 && GET_CODE (operands[1]) != CONST_INT" "* { *************** *** 2622,2741 **** (define_insn "" ! [(set (cc0) (zero_extract (match_operand:QI 0 "register_operand" "q") (const_int 1) ! (match_operand:SI 1 "general_operand" "ri")))] ! "" "* { ! if (GET_CODE (operands[1]) == CONST_INT) ! { ! operands[1] = gen_rtx (CONST_INT, VOIDmode, 1 << INTVAL (operands[1])); ! output_asm_insn (AS2 (test%B0,%1,%0), operands); ! } ! else ! { ! operands[0] = gen_rtx (REG, SImode, REGNO (operands[0])); ! cc_status.flags |= CC_Z_IN_NOT_C; ! output_asm_insn (AS2 (bt%L0,%1,%0), operands); ! } ! RET; }") ! ;; ??? The first argument of a zero_extract must not be reloaded, so ! ;; don't allow a MEM in the operand predicate without allowing it in the ! ;; constraint. ! (define_insn "" ! [(set (cc0) (zero_extract (match_operand:HI 0 "register_operand" "r") ! (const_int 1) ! (match_operand:SI 1 "general_operand" "ri")))] "" ! "* { ! if (GET_CODE (operands[1]) == CONST_INT) ! { ! if (QI_REG_P (operands[0]) && INTVAL (operands[1]) < 8) ! { ! cc_status.flags |= CC_NOT_NEGATIVE; ! operands[1] = gen_rtx (CONST_INT, VOIDmode, ! 1 << INTVAL (operands[1])); ! ! output_asm_insn (AS2 (test%B0,%1,%b0), operands); ! } ! else if (QI_REG_P (operands[0])) ! { ! operands[1] = gen_rtx (CONST_INT, VOIDmode, ! 1 << (INTVAL (operands[1]) - 8)); ! ! output_asm_insn (AS2 (test%B0,%1,%h0), operands); ! } ! else ! { ! /* ??? This will never set CC to negative, even if we test ! the sign bit of the HImode reg. But CC0 is only tested ! for EQ and NE after this insn. */ ! ! operands[1] = gen_rtx (CONST_INT, VOIDmode, ! 1 << INTVAL (operands[1])); ! ! output_asm_insn (AS2 (test%L0,%1,%k0), operands); ! } ! } else ! { ! cc_status.flags |= CC_Z_IN_NOT_C; ! output_asm_insn (AS2 (bt%W0,%1,%0), operands); ! } ! RET; }") - ;; ??? The first argument of a zero_extract must not be reloaded, so - ;; don't allow a MEM in the operand predicate without allowing it in the - ;; constraint. - (define_insn "" - [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r") - (const_int 1) - (match_operand:SI 1 "general_operand" "ri")))] - "" - "* - { - if (GET_CODE (operands[1]) == CONST_INT) - { - if (QI_REG_P (operands[0]) && INTVAL (operands[1]) < 8) - { - cc_status.flags |= CC_NOT_NEGATIVE; - operands[1] = gen_rtx (CONST_INT, VOIDmode, - 1 << INTVAL (operands[1])); - - output_asm_insn (AS2 (test%B0,%1,%b0), operands); - } - else if (QI_REG_P (operands[0]) && INTVAL (operands[1]) < 16) - { - cc_status.flags |= CC_NOT_NEGATIVE; - operands[1] = gen_rtx (CONST_INT, VOIDmode, - 1 << (INTVAL (operands[1]) - 8)); - - output_asm_insn (AS2 (test%B0,%1,%h0), operands); - } - else - { - operands[1] = gen_rtx (CONST_INT, VOIDmode, - 1 << INTVAL (operands[1])); - - output_asm_insn (AS2 (test%L0,%1,%0), operands); - } - } - else - { - cc_status.flags |= CC_Z_IN_NOT_C; - output_asm_insn (AS2 (bt%L0,%1,%0), operands); - } - RET; - }") - - ;; Store-flag instructions. - - (define_insn "seq" [(set (match_operand:QI 0 "general_operand" "=qm") (eq:QI (cc0) (const_int 0)))] --- 2902,2935 ---- (define_insn "" ! [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r") (const_int 1) ! (match_operand:SI 1 "general_operand" "r")))] ! "GET_CODE (operands[1]) != CONST_INT" "* { ! cc_status.flags |= CC_Z_IN_NOT_C; ! return AS2 (bt%L0,%1,%0); }") + + ;; Store-flag instructions. ! ;; For all sCOND expanders, also expand the compare or test insn that ! ;; generates cc0. Generate an equality comparison if `seq' or `sne'. ! (define_expand "seq" ! [(match_dup 1) ! (set (match_operand:QI 0 "general_operand" "") ! (eq:QI (cc0) (const_int 0)))] "" ! " { ! if (TARGET_IEEE_FP ! && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) ! operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); else ! operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); }") (define_insn "" [(set (match_operand:QI 0 "general_operand" "=qm") (eq:QI (cc0) (const_int 0)))] *************** *** 2747,2754 **** else return AS1 (sete,%0); ! } ! ") ! (define_insn "sne" [(set (match_operand:QI 0 "general_operand" "=qm") (ne:QI (cc0) (const_int 0)))] --- 2941,2961 ---- else return AS1 (sete,%0); ! }") ! ! (define_expand "sne" ! [(match_dup 1) ! (set (match_operand:QI 0 "general_operand" "") ! (ne:QI (cc0) (const_int 0)))] ! "" ! " ! { ! if (TARGET_IEEE_FP ! && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) ! operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); ! else ! operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); ! }") ! (define_insn "" [(set (match_operand:QI 0 "general_operand" "=qm") (ne:QI (cc0) (const_int 0)))] *************** *** 2763,2773 **** ") ! (define_insn "sgt" [(set (match_operand:QI 0 "general_operand" "=qm") (gt:QI (cc0) (const_int 0)))] "" ! "* OUTPUT_JUMP (\"setg %0\", \"seta %0\", 0); ") ! (define_insn "sgtu" [(set (match_operand:QI 0 "general_operand" "=qm") (gtu:QI (cc0) (const_int 0)))] --- 2970,3000 ---- ") ! (define_expand "sgt" ! [(match_dup 1) ! (set (match_operand:QI 0 "general_operand" "") ! (gt:QI (cc0) (const_int 0)))] ! "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") ! ! (define_insn "" [(set (match_operand:QI 0 "general_operand" "=qm") (gt:QI (cc0) (const_int 0)))] "" ! "* ! { ! if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) ! return AS1 (sete,%0); ! ! OUTPUT_JUMP (\"setg %0\", \"seta %0\", 0); ! }") ! ! (define_expand "sgtu" ! [(match_dup 1) ! (set (match_operand:QI 0 "general_operand" "") ! (gtu:QI (cc0) (const_int 0)))] ! "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") ! (define_insn "" [(set (match_operand:QI 0 "general_operand" "=qm") (gtu:QI (cc0) (const_int 0)))] *************** *** 2775,2785 **** "* return \"seta %0\"; ") ! (define_insn "slt" [(set (match_operand:QI 0 "general_operand" "=qm") (lt:QI (cc0) (const_int 0)))] "" ! "* OUTPUT_JUMP (\"setl %0\", \"setb %0\", \"sets %0\"); ") ! (define_insn "sltu" [(set (match_operand:QI 0 "general_operand" "=qm") (ltu:QI (cc0) (const_int 0)))] --- 3002,3032 ---- "* return \"seta %0\"; ") ! (define_expand "slt" ! [(match_dup 1) ! (set (match_operand:QI 0 "general_operand" "") ! (lt:QI (cc0) (const_int 0)))] ! "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") ! ! (define_insn "" [(set (match_operand:QI 0 "general_operand" "=qm") (lt:QI (cc0) (const_int 0)))] "" ! "* ! { ! if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) ! return AS1 (sete,%0); ! ! OUTPUT_JUMP (\"setl %0\", \"setb %0\", \"sets %0\"); ! }") ! ! (define_expand "sltu" ! [(match_dup 1) ! (set (match_operand:QI 0 "general_operand" "") ! (ltu:QI (cc0) (const_int 0)))] ! "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") ! (define_insn "" [(set (match_operand:QI 0 "general_operand" "=qm") (ltu:QI (cc0) (const_int 0)))] *************** *** 2787,2797 **** "* return \"setb %0\"; ") ! (define_insn "sge" [(set (match_operand:QI 0 "general_operand" "=qm") (ge:QI (cc0) (const_int 0)))] "" ! "* OUTPUT_JUMP (\"setge %0\", \"setae %0\", \"setns %0\"); ") ! (define_insn "sgeu" [(set (match_operand:QI 0 "general_operand" "=qm") (geu:QI (cc0) (const_int 0)))] --- 3034,3064 ---- "* return \"setb %0\"; ") ! (define_expand "sge" ! [(match_dup 1) ! (set (match_operand:QI 0 "general_operand" "") ! (ge:QI (cc0) (const_int 0)))] ! "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") ! ! (define_insn "" [(set (match_operand:QI 0 "general_operand" "=qm") (ge:QI (cc0) (const_int 0)))] "" ! "* ! { ! if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) ! return AS1 (sete,%0); ! ! OUTPUT_JUMP (\"setge %0\", \"setae %0\", \"setns %0\"); ! }") ! ! (define_expand "sgeu" ! [(match_dup 1) ! (set (match_operand:QI 0 "general_operand" "") ! (geu:QI (cc0) (const_int 0)))] ! "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") ! (define_insn "" [(set (match_operand:QI 0 "general_operand" "=qm") (geu:QI (cc0) (const_int 0)))] *************** *** 2799,2809 **** "* return \"setae %0\"; ") ! (define_insn "sle" [(set (match_operand:QI 0 "general_operand" "=qm") (le:QI (cc0) (const_int 0)))] "" ! "* OUTPUT_JUMP (\"setle %0\", \"setbe %0\", 0); ") ! (define_insn "sleu" [(set (match_operand:QI 0 "general_operand" "=qm") (leu:QI (cc0) (const_int 0)))] --- 3066,3096 ---- "* return \"setae %0\"; ") ! (define_expand "sle" ! [(match_dup 1) ! (set (match_operand:QI 0 "general_operand" "") ! (le:QI (cc0) (const_int 0)))] ! "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") ! ! (define_insn "" [(set (match_operand:QI 0 "general_operand" "=qm") (le:QI (cc0) (const_int 0)))] "" ! "* ! { ! if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) ! return AS1 (setb,%0); ! ! OUTPUT_JUMP (\"setle %0\", \"setbe %0\", 0); ! }") ! ! (define_expand "sleu" ! [(match_dup 1) ! (set (match_operand:QI 0 "general_operand" "") ! (leu:QI (cc0) (const_int 0)))] ! "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") ! (define_insn "" [(set (match_operand:QI 0 "general_operand" "=qm") (leu:QI (cc0) (const_int 0)))] *************** *** 2814,2818 **** ;; We ignore the overflow flag for signed branch instructions. ! (define_insn "beq" [(set (pc) (if_then_else (eq (cc0) --- 3101,3125 ---- ;; We ignore the overflow flag for signed branch instructions. ! ;; For all bCOND expanders, also expand the compare or test insn that ! ;; generates cc0. Generate an equality comparison if `beq' or `bne'. ! ! (define_expand "beq" ! [(match_dup 1) ! (set (pc) ! (if_then_else (eq (cc0) ! (const_int 0)) ! (label_ref (match_operand 0 "" "")) ! (pc)))] ! "" ! " ! { ! if (TARGET_IEEE_FP ! && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) ! operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); ! else ! operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); ! }") ! ! (define_insn "" [(set (pc) (if_then_else (eq (cc0) *************** *** 2829,2833 **** }") ! (define_insn "bne" [(set (pc) (if_then_else (ne (cc0) --- 3136,3157 ---- }") ! (define_expand "bne" ! [(match_dup 1) ! (set (pc) ! (if_then_else (ne (cc0) ! (const_int 0)) ! (label_ref (match_operand 0 "" "")) ! (pc)))] ! "" ! " ! { ! if (TARGET_IEEE_FP ! && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) ! operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); ! else ! operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); ! }") ! ! (define_insn "" [(set (pc) (if_then_else (ne (cc0) *************** *** 2844,2848 **** }") ! (define_insn "bgt" [(set (pc) (if_then_else (gt (cc0) --- 3168,3182 ---- }") ! (define_expand "bgt" ! [(match_dup 1) ! (set (pc) ! (if_then_else (gt (cc0) ! (const_int 0)) ! (label_ref (match_operand 0 "" "")) ! (pc)))] ! "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") ! ! (define_insn "" [(set (pc) (if_then_else (gt (cc0) *************** *** 2851,2857 **** (pc)))] "" ! "*OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", 0)") ! (define_insn "bgtu" [(set (pc) (if_then_else (gtu (cc0) --- 3185,3207 ---- (pc)))] "" ! "* ! { ! if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) ! return AS1 (je,%l0); ! ! OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", 0); ! }") ! ! (define_expand "bgtu" ! [(match_dup 1) ! (set (pc) ! (if_then_else (gtu (cc0) ! (const_int 0)) ! (label_ref (match_operand 0 "" "")) ! (pc)))] ! "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") ! (define_insn "" [(set (pc) (if_then_else (gtu (cc0) *************** *** 2862,2870 **** "ja %l0") - ;; There is no jump insn to check for `<' on IEEE floats. - ;; Page 17-80 in the 80387 manual says jb, but that's wrong; - ;; jb checks for `not >='. So swap the operands and do `>'. (define_expand "blt" ! [(set (pc) (if_then_else (lt (cc0) (const_int 0)) --- 3212,3218 ---- "ja %l0") (define_expand "blt" ! [(match_dup 1) ! (set (pc) (if_then_else (lt (cc0) (const_int 0)) *************** *** 2872,2894 **** (pc)))] "" ! " ! { ! rtx prev = get_last_insn_anywhere (); ! rtx body = PATTERN (prev); ! rtx comp; ! if (GET_CODE (body) == SET) ! comp = SET_SRC (body); ! else ! comp = SET_SRC (XVECEXP (body, 0, 0)); ! ! if (GET_CODE (comp) == COMPARE ! ? GET_MODE_CLASS (GET_MODE (XEXP (comp, 0))) == MODE_FLOAT ! : GET_MODE_CLASS (GET_MODE (comp)) == MODE_FLOAT) ! { ! reverse_comparison (prev); ! emit_insn (gen_bgt (operands[0])); ! DONE; ! } ! }") (define_insn "" --- 3220,3224 ---- (pc)))] "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" *************** *** 2899,2905 **** (pc)))] "" ! "*OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\")") ! (define_insn "bltu" [(set (pc) (if_then_else (ltu (cc0) --- 3229,3251 ---- (pc)))] "" ! "* ! { ! if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) ! return AS1 (je,%l0); ! ! OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\"); ! }") ! ! (define_expand "bltu" ! [(match_dup 1) ! (set (pc) ! (if_then_else (ltu (cc0) ! (const_int 0)) ! (label_ref (match_operand 0 "" "")) ! (pc)))] ! "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") ! (define_insn "" [(set (pc) (if_then_else (ltu (cc0) *************** *** 2910,2914 **** "jb %l0") ! (define_insn "bge" [(set (pc) (if_then_else (ge (cc0) --- 3256,3270 ---- "jb %l0") ! (define_expand "bge" ! [(match_dup 1) ! (set (pc) ! (if_then_else (ge (cc0) ! (const_int 0)) ! (label_ref (match_operand 0 "" "")) ! (pc)))] ! "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") ! ! (define_insn "" [(set (pc) (if_then_else (ge (cc0) *************** *** 2917,2923 **** (pc)))] "" ! "*OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\")") ! (define_insn "bgeu" [(set (pc) (if_then_else (geu (cc0) --- 3273,3295 ---- (pc)))] "" ! "* ! { ! if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) ! return AS1 (je,%l0); ! ! OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\"); ! }") ! ! (define_expand "bgeu" ! [(match_dup 1) ! (set (pc) ! (if_then_else (geu (cc0) ! (const_int 0)) ! (label_ref (match_operand 0 "" "")) ! (pc)))] ! "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") ! (define_insn "" [(set (pc) (if_then_else (geu (cc0) *************** *** 2928,2934 **** "jae %l0") - ;; See comment on `blt', above. (define_expand "ble" ! [(set (pc) (if_then_else (le (cc0) (const_int 0)) --- 3300,3306 ---- "jae %l0") (define_expand "ble" ! [(match_dup 1) ! (set (pc) (if_then_else (le (cc0) (const_int 0)) *************** *** 2936,2958 **** (pc)))] "" ! " ! { ! rtx prev = get_last_insn_anywhere (); ! rtx body = PATTERN (prev); ! rtx comp; ! if (GET_CODE (body) == SET) ! comp = SET_SRC (body); ! else ! comp = SET_SRC (XVECEXP (body, 0, 0)); ! ! if (GET_CODE (comp) == COMPARE ! ? GET_MODE_CLASS (GET_MODE (XEXP (comp, 0))) == MODE_FLOAT ! : GET_MODE_CLASS (GET_MODE (comp)) == MODE_FLOAT) ! { ! reverse_comparison (prev); ! emit_insn (gen_bge (operands[0])); ! DONE; ! } ! }") (define_insn "" --- 3308,3312 ---- (pc)))] "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" *************** *** 2963,2969 **** (pc)))] "" ! "*OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", 0) ") ! (define_insn "bleu" [(set (pc) (if_then_else (leu (cc0) --- 3317,3339 ---- (pc)))] "" ! "* ! { ! if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) ! return AS1 (jb,%l0); ! ! OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", 0); ! }") ! ! (define_expand "bleu" ! [(match_dup 1) ! (set (pc) ! (if_then_else (leu (cc0) ! (const_int 0)) ! (label_ref (match_operand 0 "" "")) ! (pc)))] ! "" ! "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") ! (define_insn "" [(set (pc) (if_then_else (leu (cc0) *************** *** 3013,3018 **** (label_ref (match_operand 0 "" ""))))] "" ! "*OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", 0) ") (define_insn "" [(set (pc) --- 3383,3394 ---- (label_ref (match_operand 0 "" ""))))] "" ! "* ! { ! if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) ! return AS1 (jne,%l0); + OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", 0); + }") + (define_insn "" [(set (pc) *************** *** 3031,3037 **** (label_ref (match_operand 0 "" ""))))] "" ! "*OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\") ! ") (define_insn "" [(set (pc) --- 3407,3418 ---- (label_ref (match_operand 0 "" ""))))] "" ! "* ! { ! if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) ! return AS1 (jne,%l0); + OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\"); + }") + (define_insn "" [(set (pc) *************** *** 3050,3055 **** (label_ref (match_operand 0 "" ""))))] "" ! "*OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\")") (define_insn "" [(set (pc) --- 3431,3442 ---- (label_ref (match_operand 0 "" ""))))] "" ! "* ! { ! if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) ! return AS1 (jne,%l0); + OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\"); + }") + (define_insn "" [(set (pc) *************** *** 3068,3073 **** (label_ref (match_operand 0 "" ""))))] "" ! "*OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", 0)") (define_insn "" [(set (pc) --- 3455,3466 ---- (label_ref (match_operand 0 "" ""))))] "" ! "* ! { ! if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) ! return AS1 (jae,%l0); + OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", 0); + }") + (define_insn "" [(set (pc) *************** *** 3107,3112 **** (match_operand:SI 1 "general_operand" ""))) (set (cc0) ! (compare (match_dup 5) ! (match_operand:SI 2 "general_operand" ""))) (set (pc) (if_then_else (gtu (cc0) --- 3500,3505 ---- (match_operand:SI 1 "general_operand" ""))) (set (cc0) ! (compare:CC (match_dup 5) ! (match_operand:SI 2 "general_operand" ""))) (set (pc) (if_then_else (gtu (cc0) *************** *** 3384,3399 **** (define_expand "movstrsi" ! [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" "")) ! (mem:BLK (match_operand:BLK 1 "general_operand" ""))) ! (use (match_operand:SI 2 "immediate_operand" "")) ! (use (match_operand:SI 3 "immediate_operand" "")) ! (set (match_operand:SI 4 "register_operand" "") ! (const_int 0)) ! (set (match_dup 0) ! (plus:SI (match_dup 0) ! (match_dup 2))) ! (set (match_dup 1) ! (plus:SI (match_dup 1) ! (match_dup 2)))])] "" " --- 3777,3787 ---- (define_expand "movstrsi" ! [(parallel [(set (mem:BLK (match_operand:BLK 0 "address_operand" "")) ! (mem:BLK (match_operand:BLK 1 "address_operand" ""))) ! (use (match_operand:SI 2 "const_int_operand" "")) ! (use (match_operand:SI 3 "const_int_operand" "")) ! (clobber (match_scratch:SI 4 "")) ! (clobber (match_dup 0)) ! (clobber (match_dup 1))])] "" " *************** *** 3403,3422 **** operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); - operands[4] = gen_reg_rtx (SImode); }") (define_insn "" ! [(set (mem:BLK (match_operand:SI 0 "register_operand" "D")) ! (mem:BLK (match_operand:SI 1 "register_operand" "S"))) ! (use (match_operand:SI 2 "immediate_operand" "n")) (use (match_operand:SI 3 "immediate_operand" "i")) ! (set (match_operand:SI 4 "register_operand" "c") ! (const_int 0)) ! (set (match_operand:SI 5 "register_operand" "=0") ! (plus:SI (match_dup 0) ! (match_dup 2))) ! (set (match_operand:SI 7 "register_operand" "=1") ! (plus:SI (match_dup 1) ! (match_dup 2)))] "" "* --- 3791,3808 ---- operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); }") + ;; It might seem that operands 0 & 1 could use predicate register_operand. + ;; But strength reduction might offset the MEM expression. So we let + ;; reload put the address into %edi & %esi. + (define_insn "" ! [(set (mem:BLK (match_operand:SI 0 "address_operand" "D")) ! (mem:BLK (match_operand:SI 1 "address_operand" "S"))) ! (use (match_operand:SI 2 "const_int_operand" "n")) (use (match_operand:SI 3 "immediate_operand" "i")) ! (clobber (match_scratch:SI 4 "=&c")) ! (clobber (match_dup 0)) ! (clobber (match_dup 1))] "" "* *************** *** 3429,3433 **** { xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2); ! xops[1] = gen_rtx (REG, SImode, 2); output_asm_insn (AS2 (mov%L1,%0,%1), xops); --- 3815,3819 ---- { xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2); ! xops[1] = operands[4]; output_asm_insn (AS2 (mov%L1,%0,%1), xops); *************** *** 3450,3456 **** (define_expand "cmpstrsi" [(parallel [(set (match_operand:QI 0 "general_operand" "") ! (compare ! (mem:BLK (match_operand:BLK 1 "general_operand" "")) ! (mem:BLK (match_operand:BLK 2 "general_operand" "")))) (use (match_operand:SI 3 "general_operand" "")) (use (match_operand:SI 4 "immediate_operand" "")) --- 3836,3842 ---- (define_expand "cmpstrsi" [(parallel [(set (match_operand:QI 0 "general_operand" "") ! (compare:CC ! (mem:BLK (match_operand:BLK 1 "address_operand" "")) ! (mem:BLK (match_operand:BLK 2 "address_operand" "")))) (use (match_operand:SI 3 "general_operand" "")) (use (match_operand:SI 4 "immediate_operand" "")) *************** *** 3466,3474 **** }") ! (define_insn "" ! [(set (match_operand:QI 0 "general_operand" "=q") ! (compare (mem:BLK (match_operand:SI 1 "general_operand" "S")) ! (mem:BLK (match_operand:SI 2 "general_operand" "D")))) ! (use (match_operand:SI 3 "general_operand" "c")) (use (match_operand:SI 4 "immediate_operand" "i")) (clobber (match_dup 1)) --- 3852,3871 ---- }") ! ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is ! ;; zero. Emit extra code to make sure that a zero-length compare is EQ. ! ! ;; It might seem that operands 0 & 1 could use predicate register_operand. ! ;; But strength reduction might offset the MEM expression. So we let ! ;; reload put the address into %edi & %esi. ! ! ;; ??? Most comparisons have a constant length, and it's therefore ! ;; possible to know that the length is non-zero, and to avoid the extra ! ;; code to handle zero-length compares. ! ! (define_insn "" ! [(set (match_operand:QI 0 "general_operand" "=&q") ! (compare:CC (mem:BLK (match_operand:SI 1 "address_operand" "S")) ! (mem:BLK (match_operand:SI 2 "address_operand" "D")))) ! (use (match_operand:SI 3 "register_operand" "c")) (use (match_operand:SI 4 "immediate_operand" "i")) (clobber (match_dup 1)) *************** *** 3478,3484 **** "* { ! rtx xops[3]; output_asm_insn (\"repz\;cmps%B2\", operands); xops[0] = operands[0]; --- 3875,3885 ---- "* { ! rtx xops[3], label; + label = gen_label_rtx (); + + output_asm_insn (AS2 (xor%B0,%0,%0), operands); output_asm_insn (\"repz\;cmps%B2\", operands); + output_asm_insn (\"je %l0\", &label); xops[0] = operands[0]; *************** *** 3490,3493 **** --- 3891,3895 ---- output_asm_insn (AS2 (mov%B0,%1,%b0), xops); output_asm_insn (AS2 (sub%B0,%2,%b0), xops); + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (label)); RET; }") *************** *** 3495,3501 **** (define_insn "" [(set (cc0) ! (compare (mem:BLK (match_operand:SI 0 "general_operand" "S")) ! (mem:BLK (match_operand:SI 1 "general_operand" "D")))) ! (use (match_operand:SI 2 "general_operand" "c")) (use (match_operand:SI 3 "immediate_operand" "i")) (clobber (match_dup 0)) --- 3897,3903 ---- (define_insn "" [(set (cc0) ! (compare:CC (mem:BLK (match_operand:SI 0 "address_operand" "S")) ! (mem:BLK (match_operand:SI 1 "address_operand" "D")))) ! (use (match_operand:SI 2 "register_operand" "c")) (use (match_operand:SI 3 "immediate_operand" "i")) (clobber (match_dup 0)) *************** *** 3503,3508 **** (clobber (match_dup 2))] "" ! "repz\;cmps%B2") (define_expand "ffssi2" [(set (match_dup 2) --- 3905,3919 ---- (clobber (match_dup 2))] "" ! "* ! { ! rtx xops[2]; + xops[0] = gen_rtx (REG, QImode, 0); + xops[1] = CONST0_RTX (QImode); + + output_asm_insn (AS2 (test%B0,%1,%0), xops); + return \"repz\;cmps%B2\"; + }") + (define_expand "ffssi2" [(set (match_dup 2) *************** *** 3625,3628 **** --- 4036,4079 ---- "TARGET_80387" "* return (char *) output_387_binary_op (insn, operands);") + + (define_expand "strlensi" + [(parallel [(set (match_dup 4) + (unspec:SI [(mem:BLK (match_operand:BLK 1 "general_operand" "")) + (match_operand:QI 2 "register_operand" "") + (match_operand:SI 3 "immediate_operand" "")] 0)) + (clobber (match_dup 1))]) + (set (match_dup 5) + (not:SI (match_dup 4))) + (set (match_operand:SI 0 "register_operand" "") + (minus:SI (match_dup 5) + (const_int 1)))] + "" + " + { + operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); + operands[4] = gen_reg_rtx (SImode); + operands[5] = gen_reg_rtx (SImode); + }") + + ;; It might seem that operands 0 & 1 could use predicate register_operand. + ;; But strength reduction might offset the MEM expression. So we let + ;; reload put the address into %edi & %esi. + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=&c") + (unspec:SI [(mem:BLK (match_operand:SI 1 "address_operand" "D")) + (match_operand:QI 2 "register_operand" "a") + (match_operand:SI 3 "immediate_operand" "i")] 0)) + (clobber (match_dup 1))] + "" + "* + { + rtx xops[2]; + + xops[0] = operands[0]; + xops[1] = constm1_rtx; + output_asm_insn (AS2 (mov%L0,%1,%0), xops); + return \"repnz\;scas%B2\"; + }") ;;- Local variables: diff -rc2N gcc-2.1/config/i386gas.h gcc-2.2.1/config/i386gas.h *** gcc-2.1/config/i386gas.h Sat Feb 15 23:59:26 1992 --- gcc-2.2.1/config/i386gas.h Mon May 25 16:10:20 1992 *************** *** 18,21 **** --- 18,23 ---- the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + /* Note that seq386gas.h is a GAS configuration that does not use this + file. */ #include "i386.h" *************** *** 122,130 **** if ((PTR)[0] == 'r' \ && (PTR)[1] == 'e' \ ! && (PTR)[2] == 'p' \ ! && (PTR)[3] == 'z') \ { \ ! fprintf (STREAM, "repe"); \ ! (PTR) += 4; \ } \ } --- 124,151 ---- if ((PTR)[0] == 'r' \ && (PTR)[1] == 'e' \ ! && (PTR)[2] == 'p') \ { \ ! if ((PTR)[3] == 'z') \ ! { \ ! fprintf (STREAM, "repe"); \ ! (PTR) += 4; \ ! } \ ! else if ((PTR)[3] == 'n' && (PTR)[4] == 'z') \ ! { \ ! fprintf (STREAM, "repne"); \ ! (PTR) += 5; \ ! } \ } \ } + + /* Define macro used to output shift-double opcodes when the shift + count is in %cl. Some assemblers require %cl as an argument; + some don't. + + GAS requires the %cl argument, so override unx386.h. */ + + #undef AS3_SHIFT_DOUBLE + #define AS3_SHIFT_DOUBLE(a,b,c,d) AS3 (a,b,c,d) + + /* Print opcodes the way that GAS expects them. */ + #define GAS_MNEMONICS 1 diff -rc2N gcc-2.1/config/i386rose.h gcc-2.2.1/config/i386rose.h *** gcc-2.1/config/i386rose.h Fri Mar 20 13:51:40 1992 --- gcc-2.2.1/config/i386rose.h Thu May 7 17:17:13 1992 *************** *** 19,22 **** --- 19,23 ---- the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + #include "halfpic.h" #include "i386gas.h" *************** *** 30,33 **** --- 31,44 ---- #endif + #define MASK_HALF_PIC 0x00000100 /* Mask for half-pic code */ + #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC) + + #ifdef SUBTARGET_SWITCHES + #undef SUBTARGET_SWITCHES + #endif + #define SUBTARGET_SWITCHES \ + { "half-pic", MASK_HALF_PIC}, \ + { "no-half-pic", -MASK_HALF_PIC}, + /* Prefix that appears before all global/static identifiers, except for temporary labels. */ *************** *** 60,68 **** #undef CC1_SPEC #endif ! #define CC1_SPEC "" ! ! #ifndef CC1PLUS_SPEC ! #define CC1PLUS_SPEC "%{!fgnu-binutils: -fno-gnu-binutils}" ! #endif #ifdef ASM_SPEC --- 71,79 ---- #undef CC1_SPEC #endif ! #define CC1_SPEC \ ! "%{pic-none: -mno-half-pic} \ ! %{pic-lib: -mhalf-pic} \ ! %{pic-extern: -mhalf-pic} \ ! %{pic-calls: -mhalf-pic}" #ifdef ASM_SPEC *************** *** 75,81 **** #endif #define LINK_SPEC "%{v*: -v} \ ! %{pic-none: -noshrlib} %{noshrlib} \ ! %{!pic-none: -warn_nopic} \ ! %{nostdlib} %{glue}" #ifdef LIB_SPEC --- 86,91 ---- #endif #define LINK_SPEC "%{v*: -v} \ ! %{!noshrlib: %{pic-none: -noshrlib} %{!pic-none: -warn_nopic}} \ ! %{nostdlib} %{noshrlib} %{glue}" #ifdef LIB_SPEC *************** *** 83,90 **** #endif ! /* For now, force static libraries instead of shared, but do so that ! does not use -noshrlib, since the old linker does not provide it. */ ! ! #define LIB_SPEC "%{!pic-none: %{!pic-lib: -L/usr/ccs/lib }} -lc" #ifdef LIBG_SPEC --- 93,97 ---- #endif ! #define LIB_SPEC "-lc" #ifdef LIBG_SPEC *************** *** 121,124 **** --- 128,248 ---- #define FUNCTION_PROFILER(FILE, LABELNO) fprintf (FILE, "\tcall _mcount\n") + /* Some machines may desire to change what optimizations are + performed for various optimization levels. This macro, if + defined, is executed once just after the optimization level is + determined and before the remainder of the command options have + been parsed. Values set in this macro are used as the default + values for the other command line options. + + LEVEL is the optimization level specified; 2 if -O2 is + specified, 1 if -O is specified, and 0 if neither is specified. */ + + #define OPTIMIZATION_OPTIONS(LEVEL) \ + { \ + flag_gnu_linker = FALSE; \ + \ + if (LEVEL) \ + { \ + flag_omit_frame_pointer = TRUE; \ + flag_thread_jumps = TRUE; \ + } \ + \ + if (LEVEL >= 2) \ + { \ + flag_strength_reduce = TRUE; \ + flag_cse_follow_jumps = TRUE; \ + flag_expensive_optimizations = TRUE; \ + flag_rerun_cse_after_loop = TRUE; \ + } \ + \ + if (LEVEL >= 3) \ + { \ + flag_inline_functions = TRUE; \ + } \ + } + + /* A C expression that is 1 if the RTX X is a constant which is a + valid address. On most machines, this can be defined as + `CONSTANT_P (X)', but a few machines are more restrictive in + which constant addresses are supported. + + `CONSTANT_P' accepts integer-values expressions whose values are + not explicitly known, such as `symbol_ref', `label_ref', and + `high' expressions and `const' arithmetic expressions, in + addition to `const_int' and `const_double' expressions. */ + + #ifdef CONSTANT_ADDRESS_P + #undef CONSTANT_ADDRESS_P + #endif + #define CONSTANT_ADDRESS_P(X) \ + (CONSTANT_P (X) && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X))) + + /* Define this macro if references to a symbol must be treated + differently depending on something about the variable or + function named by the symbol (such as what section it is in). + + The macro definition, if any, is executed immediately after the + rtl for DECL has been created and stored in `DECL_RTL (DECL)'. + The value of the rtl will be a `mem' whose address is a + `symbol_ref'. + + The usual thing for this macro to do is to a flag in the + `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified + name string in the `symbol_ref' (if one bit is not enough + information). + + The best way to modify the name string is by adding text to the + beginning, with suitable punctuation to prevent any ambiguity. + Allocate the new name in `saveable_obstack'. You will have to + modify `ASM_OUTPUT_LABELREF' to remove and decode the added text + and output the name accordingly. + + You can also check the information stored in the `symbol_ref' in + the definition of `GO_IF_LEGITIMATE_ADDRESS' or + `PRINT_OPERAND_ADDRESS'. */ + + #ifdef ENCODE_SECTION_INFO + #undef ENCODE_SECTION_INFO + #endif + #define ENCODE_SECTION_INFO(DECL) \ + do \ + { \ + if (HALF_PIC_P ()) \ + HALF_PIC_ENCODE (DECL); \ + } \ + while (0) + + + /* A C statement (sans semicolon) to output to the stdio stream + STREAM any text necessary for declaring the name NAME of an + initialized variable which is being defined. This macro must + output the label definition (perhaps using `ASM_OUTPUT_LABEL'). + The argument DECL is the `VAR_DECL' tree node representing the + variable. + + If this macro is not defined, then the variable name is defined + in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */ + + #ifdef ASM_DECLARE_OBJECT_NAME + #undef ASM_DECLARE_OBJECT_NAME + #endif + #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ + do \ + { \ + ASM_OUTPUT_LABEL(STREAM,NAME); \ + HALF_PIC_DECLARE (NAME); \ + } \ + while (0) + + /* This is how to declare a function name. */ + + #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ + do \ + { \ + ASM_OUTPUT_LABEL(STREAM,NAME); \ + HALF_PIC_DECLARE (NAME); \ + } \ + while (0) + /* Tell collect that the object format is OSF/rose. */ #define OBJECT_FORMAT_ROSE *************** *** 129,135 **** /* Define this macro meaning that gcc should find the library 'libgcc.a' ! by hand, rather than passing the argeument '-lgcc' to tell the linker to do the search */ #define LINK_LIBGCC_SPECIAL /* Defines to be able to build libgcc.a with GCC. */ --- 253,297 ---- /* Define this macro meaning that gcc should find the library 'libgcc.a' ! by hand, rather than passing the argument '-lgcc' to tell the linker to do the search */ #define LINK_LIBGCC_SPECIAL + + /* A C statement to output assembler commands which will identify the object + file as having been compile with GNU CC. We don't need or want this for + OSF1. GDB doesn't need it and kdb doesn't like it */ + #define ASM_IDENTIFY_GCC(FILE) + + /* This is how to output an assembler line defining a `double' constant. + Use "word" pseudos to avoid printing NaNs, infinity, etc. */ + + /* This is how to output an assembler line defining a `double' constant. */ + + #ifdef ASM_OUTPUT_DOUBLE + #undef ASM_OUTPUT_DOUBLE + #endif + #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \ + { \ + union { double d; long l[2]; } u2; \ + u2.d = VALUE; \ + fprintf (STREAM, "\t.long\t0x%08lx\t\t# %.20g\n\t.long\t0x%08lx\n", \ + u2.l[0], u2.d, u2.l[1]); \ + } + + /* This is how to output an assembler line defining a `float' constant. */ + + #ifdef ASM_OUTPUT_FLOAT + #undef ASM_OUTPUT_FLOAT + #endif + #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \ + { \ + union { float f; long l; } u2; \ + u2.f = VALUE; \ + fprintf (STREAM, "\t.long\t0x%08lx\t\t# %.12g\n", u2.l, u2.f); \ + } + + /* Generate calls to memcpy, etc., not bcopy, etc. */ + #define TARGET_MEM_FUNCTIONS + + /* Defines to be able to build libgcc.a with GCC. */ diff -rc2N gcc-2.1/config/i386sco.h gcc-2.2.1/config/i386sco.h *** gcc-2.1/config/i386sco.h Sun Mar 8 21:45:20 1992 --- gcc-2.2.1/config/i386sco.h Wed May 27 22:34:40 1992 *************** *** 31,34 **** --- 31,37 ---- #define HAVE_ATEXIT + /* Specify the size_t type. */ + #define SIZE_TYPE "unsigned int" + #if 0 /* Not yet certain whether this is needed. */ /* If no 387, use the general regs to return floating values, diff -rc2N gcc-2.1/config/i386sco4.h gcc-2.2.1/config/i386sco4.h *** gcc-2.1/config/i386sco4.h --- gcc-2.2.1/config/i386sco4.h Wed May 13 13:30:21 1992 *************** *** 0 **** --- 1,80 ---- + /* Definitions for Intel 386 running SCO Unix System V 3.2 Version 4. + Written by Chip Salzenberg. + Copyright (C) 1992 Free Software Foundation, Inc. + + This file is part of GNU CC. + + GNU CC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GNU CC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GNU CC; see the file COPYING. If not, write to + the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + + /* Mostly it's like earlier SCO UNIX. */ + + #include "i386sco.h" + + /* Use crt1.o as a startup file and crtn.o as a closing file. */ + + #undef STARTFILE_SPEC + #define STARTFILE_SPEC \ + "%{scoxpg3:%{p:mcrt1X.o%s}%{!p:crt1X.o%s}} \ + %{!scoxpg3:\ + %{posix:%{p:mcrt1P.o%s}%{!p:crt1P.o%s}} \ + %{!posix:\ + %{ansi:%{p:mcrt1A.o%s}%{!p:crt1A.o%s}} \ + %{!ansi:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}}}} \ + crtbegin.o%s" + + #undef ENDFILE_SPEC + #define ENDFILE_SPEC \ + "crtend.o%s \ + %{scoxpg3:crtnX.o%s} \ + %{!scoxpg3:\ + %{posix:crtnP.o%s} \ + %{!posix:\ + %{ansi:crtnA.o%s} \ + %{!ansi:crtn.o%s}}}" + + /* Library spec. */ + + #undef LIB_SPEC + #define LIB_SPEC \ + "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} \ + %{scoxpg3:-lcX -lcP -lcA} \ + %{!scoxpg3:\ + %{posix:-lcP -lcA} \ + %{!posix:\ + %{ansi:-lcA} \ + %{!ansi:%{scointl:-lintl} -lc}}}" + + /* Macros, macros everywhere: + Specify predefined symbols in preprocessor. */ + + #undef CPP_PREDEFINES + #define CPP_PREDEFINES "" + + #undef CPP_SPEC + #define CPP_SPEC \ + "-D__i386 -D_M_I386 -D_M_I86 -D_M_I86SM -D_M_SDATA -D_M_STEXT \ + -D__unix -D_M_UNIX -D_M_XENIX \ + -D_M_SYS5 -D_M_SYSV -D_M_SYSV -D_M_SYS3 -D_M_SYSIII \ + -D_M_COFF -D_M_BITFIELDS -D_M_WORDSWAP \ + %{scoxpg3:-D_XOPEN_SOURCE -D_STRICT_NAMES} \ + %{!scoxpg3:%{posix:-D_POSIX_SOURCE -D_STRICT_NAMES}} \ + %{!scoxpg3:%{!posix:\ + %{ansi:-D_STRICT_NAMES}%{!ansi:\ + -Di386 -DM_I386 -DM_I86 -DM_I86SM -DM_SDATA -DM_STEXT \ + -Dunix -DM_UNIX -DM_XENIX \ + -DM_SYS5 -DM_SYSV -D_M_SYSV -DM_SYS3 -DM_SYSIII \ + -DM_COFF -DM_BITFIELDS -DM_WORDSWAP \ + %{scointl:-D_M_INTERNAT -DM_INTERNAT} -D__STDC__=0}}}" diff -rc2N gcc-2.1/config/i386v.h gcc-2.2.1/config/i386v.h *** gcc-2.1/config/i386v.h Thu Mar 19 15:40:58 1992 --- gcc-2.2.1/config/i386v.h Sat Mar 28 23:50:08 1992 *************** *** 99,102 **** --- 99,117 ---- #define FRAME_POINTER_REQUIRED \ (current_function_calls_setjmp || current_function_calls_longjmp) + + /* Modify ASM_OUTPUT_LOCAL slightly to test -msvr3-shlib. */ + #undef ASM_OUTPUT_LOCAL + #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ + do { \ + int align = exact_log2 (ROUNDED); \ + if (align > 2) align = 2; \ + if (TARGET_SVR3_SHLIB) \ + data_section (); \ + else \ + bss_section (); \ + ASM_OUTPUT_ALIGN ((FILE), align == -1 ? 2 : align); \ + ASM_OUTPUT_LABEL ((FILE), (NAME)); \ + fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED)); \ + } while (0) /* Define a few machine-specific details of the implementation of diff -rc2N gcc-2.1/config/i386v4.h gcc-2.2.1/config/i386v4.h *** gcc-2.1/config/i386v4.h Sat Feb 1 00:59:17 1992 --- gcc-2.2.1/config/i386v4.h Thu May 28 14:41:14 1992 *************** *** 23,26 **** --- 23,27 ---- #include "att386.h" /* Use the i386 AT&T assembler syntax */ #include "svr4.h" /* Definitions common to all SVR4 targets */ + #include "real.h" #undef TARGET_VERSION *************** *** 58,61 **** --- 59,92 ---- "-Di386 -Dunix -D__svr4__ -Asystem(unix) -Acpu(i386) -Amachine(i386)" + /* If the host and target formats match, output the floats as hex. */ + #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT + #if defined (HOST_WORDS_BIG_ENDIAN) == WORDS_BIG_ENDIAN + /* This is how to output assembly code to define a `float' constant. + We always have to use a .long pseudo-op to do this because the native + SVR4 ELF assembler is buggy and it generates incorrect values when we + try to use the .float pseudo-op instead. */ + + #undef ASM_OUTPUT_FLOAT + #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ + do { long value; \ + REAL_VALUE_TO_TARGET_SINGLE ((VALUE), value); \ + fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value); \ + } while (0) + + /* This is how to output assembly code to define a `double' constant. + We always have to use a pair of .long pseudo-ops to do this because + the native SVR4 ELF assembler is buggy and it generates incorrect + values when we try to use the the .double pseudo-op instead. */ + + #undef ASM_OUTPUT_DOUBLE + #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ + do { long value[2]; \ + REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), value); \ + fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[0]); \ + fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[1]); \ + } while (0) + #endif /* word order matches */ + #endif /* HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT */ + /* Output at beginning of assembler file. */ /* The .file command should always begin the output. */ *************** *** 72,92 **** in its Dwarf output code: ! 0 for %eax (regno = 0) ! 1 for %ecx (regno = 2) ! 2 for %edx (regno = 1) ! 3 for %ebx (regno = 3) ! 4 for %esp (regno = 7) ! 5 for %ebp (regno = 6) ! 6 for %esi (regno = 4) ! 7 for %edi (regno = 5) ! ! 8 for FP_REGS[tos] (regno = 8) ! 9 for FP_REGS[tos-1] (regno = 9) ! 10 for FP_REGS[tos-2] (regno = 10) ! 11 for FP_REGS[tos-3] (regno = 11) ! 12 for FP_REGS[tos-4] (regno = 12) ! 13 for FP_REGS[tos-5] (regno = 13) ! 14 for FP_REGS[tos-6] (regno = 14) ! 15 for FP_REGS[tos-7] (regno = 15) */ --- 103,164 ---- in its Dwarf output code: ! 0 for %eax (gnu regno = 0) ! 1 for %ecx (gnu regno = 2) ! 2 for %edx (gnu regno = 1) ! 3 for %ebx (gnu regno = 3) ! 4 for %esp (gnu regno = 7) ! 5 for %ebp (gnu regno = 6) ! 6 for %esi (gnu regno = 4) ! 7 for %edi (gnu regno = 5) ! ! The following three DWARF register numbers are never generated by ! the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4 ! believes these numbers have these meanings. ! ! 8 for %eip (no gnu equivalent) ! 9 for %eflags (no gnu equivalent) ! 10 for %trapno (no gnu equivalent) ! ! It is not at all clear how we should number the FP stack registers ! for the x86 architecture. If the version of SDB on x86/svr4 were ! a bit less brain dead with respect to floating-point then we would ! have a precedent to follow with respect to DWARF register numbers ! for x86 FP registers, but the SDB on x86/svr4 is so completely ! broken with respect to FP registers that it is hardly worth thinking ! of it as something to strive for compatability with. ! ! The verison of x86/svr4 SDB I have at the moment does (partially) ! seem to believe that DWARF register number 11 is associated with ! the x86 register %st(0), but that's about all. Higher DWARF ! register numbers don't seem to be associated with anything in ! particular, and even for DWARF regno 11, SDB only seems to under- ! stand that it should say that a variable lives in %st(0) (when ! asked via an `=' command) if we said it was in DWARF regno 11, ! but SDB still prints garbage when asked for the value of the ! variable in question (via a `/' command). ! ! (Also note that the labels SDB prints for various FP stack regs ! when doing an `x' command are all wrong.) ! ! Note that these problems generally don't affect the native SVR4 ! C compiler because it doesn't allow the use of -O with -g and ! because when it is *not* optimizing, it allocates a memory ! location for each floating-point variable, and the memory ! location is what gets described in the DWARF AT_location ! attribute for the variable in question. ! ! Regardless of the severe mental illness of the x86/svr4 SDB, we ! do something sensible here and we use the following DWARF ! register numbers. Note that these are all stack-top-relative ! numbers. ! ! 11 for %st(0) (gnu regno = 8) ! 12 for %st(1) (gnu regno = 9) ! 13 for %st(2) (gnu regno = 10) ! 14 for %st(3) (gnu regno = 11) ! 15 for %st(4) (gnu regno = 12) ! 16 for %st(5) (gnu regno = 13) ! 17 for %st(6) (gnu regno = 14) ! 18 for %st(7) (gnu regno = 15) */ *************** *** 101,105 **** : (n) == 6 ? 5 \ : (n) == 7 ? 4 \ ! : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n) \ : (abort (), 0)) --- 173,177 ---- : (n) == 6 ? 5 \ : (n) == 7 ? 4 \ ! : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \ : (abort (), 0)) *************** *** 166,172 **** #define JUMP_TABLES_IN_TEXT_SECTION - #define WEAK_ASM_OP ".weak" - #define DEF_ASM_OP ".set" - /* Biggest alignment that any structure field can require on this machine, in bits. If packing is in effect, this can be smaller than --- 238,241 ---- *************** *** 214,227 **** c = getc (FILE); \ } while (1) - - /* This says how to output assembler code to declare an - uninitialized internal linkage data object. Under SVR4, - the linker seems to want the alignment of data objects - to depend on their types. We do exactly that here. */ - - #undef ASM_OUTPUT_ALIGNED_LOCAL - #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ - do { \ - fprintf (FILE, "\t.local\t%s\n", NAME); \ - ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN); \ - } while (0) --- 283,284 ---- diff -rc2N gcc-2.1/config/i860.c gcc-2.2.1/config/i860.c *** gcc-2.1/config/i860.c Sat Mar 14 00:15:46 1992 --- gcc-2.2.1/config/i860.c Sat Jun 6 17:38:47 1992 *************** *** 670,679 **** if (GET_CODE (operands[1]) == CONST_INT) { if((INTVAL (operands[1]) & 0xffff0000) == 0) return "or %L1,%?r0,%0"; if((INTVAL (operands[1]) & 0x0000ffff) == 0) return "orh %H1,%?r0,%0"; - if (operands[1] == const0_rtx) - return "mov %?r0,%0"; } return "mov %1,%0"; --- 670,681 ---- if (GET_CODE (operands[1]) == CONST_INT) { + if (operands[1] == const0_rtx) + return "mov %?r0,%0"; if((INTVAL (operands[1]) & 0xffff0000) == 0) return "or %L1,%?r0,%0"; + if((INTVAL (operands[1]) & 0xffff8000) == 0xffff8000) + return "adds %1,%?r0,%0"; if((INTVAL (operands[1]) & 0x0000ffff) == 0) return "orh %H1,%?r0,%0"; } return "mov %1,%0"; *************** *** 1197,1201 **** #if 1 cc_status.flags &= ~ CC_KNOW_HI_R31; ! output_asm_insn ("mov %1,%0", xoperands); #else if (GET_CODE (size) == REG) --- 1199,1203 ---- #if 1 cc_status.flags &= ~ CC_KNOW_HI_R31; ! output_asm_insn (singlemove_string (xoperands), xoperands); #else if (GET_CODE (size) == REG) *************** *** 1622,1626 **** #if TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT ! # error IEEE emulation needed #endif REAL_VALUE_FROM_CONST_DOUBLE (d, x); --- 1624,1628 ---- #if TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT ! error IEEE emulation needed #endif REAL_VALUE_FROM_CONST_DOUBLE (d, x); *************** *** 2038,2041 **** --- 2040,2064 ---- */ + /* This corresponds to a version 4 TDESC structure. Lower numbered + versions successively omit the last word of the structure. We + don't try to handle version 5 here. */ + + typedef struct TDESC_flags { + int version:4; + int reg_packing:1; + int callable_block:1; + int reserved:4; + int fregs:6; /* fp regs 2-7 */ + int iregs:16; /* regs 0-15 */ + } TDESC_flags; + + typedef struct TDESC { + TDESC_flags flags; + int integer_reg_offset; /* same as must_preserve_bytes */ + int floating_point_reg_offset; + unsigned int positive_frame_size; /* same as frame_upper_bytes */ + unsigned int negative_frame_size; /* same as frame_lower_bytes */ + } TDESC; + void function_epilogue (asm_file, local_bytes) *************** *** 2044,2051 **** --- 2067,2087 ---- { register unsigned frame_upper_bytes; + register unsigned frame_lower_bytes; register unsigned preserved_reg_bytes = 0; register unsigned i; register unsigned restored_so_far = 0; + register unsigned int_restored; + register unsigned mask; + unsigned intflags=0; + register TDESC_flags *flags = (TDESC_flags *) &intflags; + + flags->version = 4; + flags->reg_packing = 1; + flags->iregs = 8; /* old fp always gets saved */ + + /* Round-up the frame_lower_bytes so that it's a multiple of 16. */ + frame_lower_bytes = (local_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT; + /* Count the number of registers that were preserved in the prologue. Ignore r0. It is never preserved. */ *************** *** 2070,2084 **** /* Restore all of the "preserved" registers that need restoring. */ ! for (i = 1; i < 32; i++) ! if (regs_ever_live[i] && ! call_used_regs[i]) fprintf (asm_file, "\tld.l %d(%sfp),%s%s\n", must_preserve_bytes + (4 * restored_so_far++), i860_reg_prefix, i860_reg_prefix, reg_names[i]); ! for (i = 32; i < 64; i++) ! if (regs_ever_live[i] && ! call_used_regs[i]) fprintf (asm_file, "\tfld.l %d(%sfp),%s%s\n", must_preserve_bytes + (4 * restored_so_far++), i860_reg_prefix, i860_reg_prefix, reg_names[i]); /* Get the value we plan to use to restore the stack pointer into r31. */ --- 2106,2134 ---- /* Restore all of the "preserved" registers that need restoring. */ ! mask = 2; ! ! for (i = 1; i < 32; i++, mask<<=1) ! if (regs_ever_live[i] && ! call_used_regs[i]) { fprintf (asm_file, "\tld.l %d(%sfp),%s%s\n", must_preserve_bytes + (4 * restored_so_far++), i860_reg_prefix, i860_reg_prefix, reg_names[i]); + if (i > 3 && i < 16) + flags->iregs |= mask; + } ! int_restored = restored_so_far; ! mask = 1; ! ! for (i = 32; i < 64; i++) { ! if (regs_ever_live[i] && ! call_used_regs[i]) { fprintf (asm_file, "\tfld.l %d(%sfp),%s%s\n", must_preserve_bytes + (4 * restored_so_far++), i860_reg_prefix, i860_reg_prefix, reg_names[i]); + if (i > 33 & i < 40) + flags->fregs |= mask; + } + if (i > 33 && i < 40) + mask<<=1; + } /* Get the value we plan to use to restore the stack pointer into r31. */ *************** *** 2089,2095 **** /* Restore the return address and the old frame pointer. */ ! if (must_preserve_r1) fprintf (asm_file, "\tld.l 4(%sfp),%sr1\n", i860_reg_prefix, i860_reg_prefix); fprintf (asm_file, "\tld.l 0(%sfp),%sfp\n", --- 2139,2147 ---- /* Restore the return address and the old frame pointer. */ ! if (must_preserve_r1) { fprintf (asm_file, "\tld.l 4(%sfp),%sr1\n", i860_reg_prefix, i860_reg_prefix); + flags->iregs |= 2; + } fprintf (asm_file, "\tld.l 0(%sfp),%sfp\n", *************** *** 2100,2102 **** --- 2152,2187 ---- fprintf (asm_file, "\tbri %sr1\n\tmov %sr31,%ssp\n", i860_reg_prefix, i860_reg_prefix, i860_reg_prefix); + + #ifdef OUTPUT_TDESC /* Output an ABI-compliant TDESC entry */ + if (! frame_lower_bytes) { + flags->version--; + if (! frame_upper_bytes) { + flags->version--; + if (restored_so_far == int_restored) /* No FP saves */ + flags->version--; + } + } + assemble_name(asm_file,current_function_original_name); + fputs(".TDESC:\n", asm_file); + fprintf(asm_file, "%s 0x%0x\n", ASM_LONG, intflags); + fprintf(asm_file, "%s %d\n", ASM_LONG, + int_restored ? must_preserve_bytes : 0); + if (flags->version > 1) { + fprintf(asm_file, "%s %d\n", ASM_LONG, + (restored_so_far == int_restored) ? 0 : must_preserve_bytes + + (4 * int_restored)); + if (flags->version > 2) { + fprintf(asm_file, "%s %d\n", ASM_LONG, frame_upper_bytes); + if (flags->version > 3) + fprintf(asm_file, "%s %d\n", ASM_LONG, frame_lower_bytes); + } + } + tdesc_section(); + fprintf(asm_file, "%s ", ASM_LONG); + assemble_name(asm_file, current_function_original_name); + fprintf(asm_file, "\n%s ", ASM_LONG); + assemble_name(asm_file, current_function_original_name); + fputs(".TDESC\n", asm_file); + text_section(); + #endif } diff -rc2N gcc-2.1/config/i860.h gcc-2.2.1/config/i860.h *** gcc-2.1/config/i860.h Sat Mar 14 00:15:48 1992 --- gcc-2.2.1/config/i860.h Fri May 15 16:22:29 1992 *************** *** 351,355 **** non-zero floating-point constant into some register, use an integer register if the constant is SFmode and GENERAL_REGS is one of our options. ! Otherwise, put the constant intoo memory. */ #define PREFERRED_RELOAD_CLASS(X,CLASS) \ --- 351,355 ---- non-zero floating-point constant into some register, use an integer register if the constant is SFmode and GENERAL_REGS is one of our options. ! Otherwise, put the constant into memory. */ #define PREFERRED_RELOAD_CLASS(X,CLASS) \ *************** *** 897,901 **** return it with a return statement. Otherwise, break from the switch. */ ! #define CONST_COSTS(RTX,CODE) \ case CONST_INT: \ if (INTVAL (RTX) == 0) \ --- 897,901 ---- return it with a return statement. Otherwise, break from the switch. */ ! #define CONST_COSTS(RTX,CODE, OUTER_CODE) \ case CONST_INT: \ if (INTVAL (RTX) == 0) \ *************** *** 905,911 **** case LABEL_REF: \ case SYMBOL_REF: \ ! return 2; \ case CONST_DOUBLE: \ ! return 4; /* Specify the cost of a branch insn; roughly the number of extra insns that --- 905,911 ---- case LABEL_REF: \ case SYMBOL_REF: \ ! return 4; \ case CONST_DOUBLE: \ ! return 6; /* Specify the cost of a branch insn; roughly the number of extra insns that diff -rc2N gcc-2.1/config/i860.md gcc-2.2.1/config/i860.md *** gcc-2.1/config/i860.md Thu Jan 23 14:10:22 1992 --- gcc-2.2.1/config/i860.md Sun Apr 5 13:46:51 1992 *************** *** 1647,1652 **** (set (match_dup 4) (xor:SI (match_operand:SI 1 "register_operand" "") (const_int -2147483648))) (set (subreg:SI (match_dup 5) 0) (match_dup 4)) - (set (subreg:SI (match_dup 5) 1) (subreg:SI (match_dup 2) 1)) (set (match_operand:DF 0 "register_operand" "") (minus:DF (match_dup 5) (match_dup 2)))] --- 1647,1652 ---- (set (match_dup 4) (xor:SI (match_operand:SI 1 "register_operand" "") (const_int -2147483648))) + (set (match_dup 5) (match_dup 3)) (set (subreg:SI (match_dup 5) 0) (match_dup 4)) (set (match_operand:DF 0 "register_operand" "") (minus:DF (match_dup 5) (match_dup 2)))] diff -rc2N gcc-2.1/config/i860b.h gcc-2.2.1/config/i860b.h *** gcc-2.1/config/i860b.h Wed Jan 15 18:27:36 1992 --- gcc-2.2.1/config/i860b.h Fri Apr 24 21:17:01 1992 *************** *** 18,22 **** inside = FALSE; \ } \ ! fprintf((f), "%s ", ASCII_DATA_ASM_OP); \ } \ if ((p)[i] < 32 || (p)[i] == '\\' || (p)[i] == '"' || (p)[i] >= 127) { \ --- 18,22 ---- inside = FALSE; \ } \ ! fprintf((f), "\t%s ", ASCII_DATA_ASM_OP); \ } \ if ((p)[i] < 32 || (p)[i] == '\\' || (p)[i] == '"' || (p)[i] >= 127) { \ diff -rc2N gcc-2.1/config/i860v3.h gcc-2.2.1/config/i860v3.h *** gcc-2.1/config/i860v3.h Mon Mar 16 04:42:18 1992 --- gcc-2.2.1/config/i860v3.h Fri Apr 24 21:30:42 1992 *************** *** 104,108 **** bytes_in_chunk = 0; \ } \ ! fprintf ((FILE), "%s\t%d\n", ASM_BYTE_OP, ch); \ } \ else \ --- 104,108 ---- bytes_in_chunk = 0; \ } \ ! fprintf ((FILE), "\t%s\t%d\n", ASM_BYTE_OP, ch); \ } \ else \ *************** *** 126,132 **** #undef CTORS_SECTION_ASM_OP ! #define CTORS_SECTION_ASM_OP ".section\t.ctors,\"x\"\n" #undef DTORS_SECTION_ASM_OP ! #define DTORS_SECTION_ASM_OP ".section\t.dtors,\"x\"\n" /* Add definitions to support the .tdesc section as specified in the svr4 --- 126,132 ---- #undef CTORS_SECTION_ASM_OP ! #define CTORS_SECTION_ASM_OP ".section\t.ctors,\"x\"" #undef DTORS_SECTION_ASM_OP ! #define DTORS_SECTION_ASM_OP ".section\t.dtors,\"x\"" /* Add definitions to support the .tdesc section as specified in the svr4 diff -rc2N gcc-2.1/config/i860v4.h gcc-2.2.1/config/i860v4.h *** gcc-2.1/config/i860v4.h Mon Mar 16 04:43:05 1992 --- gcc-2.2.1/config/i860v4.h Sat Jun 6 17:38:49 1992 *************** *** 61,64 **** --- 61,113 ---- } while (0) + /* If the host and target formats match, output the floats as hex. */ + #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT + #if defined (HOST_WORDS_BIG_ENDIAN) == WORDS_BIG_ENDIAN + + /* This is how to output an assembler line defining a `double' constant. + Note that the native i860/svr4 ELF assembler can't properly handle + infinity. It generates an incorrect (non-infinity) value when given + `.double 99e9999' and it doesn't grok `inf' at all. It also mishandles + NaNs and -0.0. */ + + #undef ASM_OUTPUT_DOUBLE + #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ + { \ + if (REAL_VALUE_ISINF (VALUE) \ + || REAL_VALUE_ISNAN (VALUE) \ + || REAL_VALUE_MINUS_ZERO (VALUE)) \ + { \ + long t[2]; \ + REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ + fprintf (FILE, "\t.word 0x%lx\n\t.word 0x%lx\n", t[0], t[1]); \ + } \ + else \ + fprintf (FILE, "\t.double %.20g\n", VALUE); \ + } + + /* This is how to output an assembler line defining a `float' constant. + Note that the native i860/svr4 ELF assembler can't properly handle + infinity. It actually generates an assembly time error when given + `.float 99e9999' and it doesn't grok `inf' at all. It also mishandles + NaNs and -0.0. */ + + #undef ASM_OUTPUT_FLOAT + #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ + { \ + if (REAL_VALUE_ISINF (VALUE) \ + || REAL_VALUE_ISNAN (VALUE) \ + || REAL_VALUE_MINUS_ZERO (VALUE)) \ + { \ + long t; \ + REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ + fprintf (FILE, "\t.word 0x%lx\n", t); \ + } \ + else \ + fprintf (FILE, "\t.float %.12g\n", VALUE); \ + } + + #endif /* word order matches */ + #endif /* HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT */ + #undef ASM_FILE_START #define ASM_FILE_START(FILE) \ *************** *** 130,131 **** --- 179,196 ---- } \ } + + #ifdef OUTPUT_TDESC + #undef ASM_FILE_END + #define ASM_FILE_END(FILE) \ + do { \ + if (current_function_original_name != NULL) { \ + tdesc_section(); \ + fprintf ((FILE), "%s __ETEXT\n", ASM_LONG); \ + fprintf ((FILE), "%s 0\n", ASM_LONG); \ + text_section(); \ + fputs("__ETEXT:\n", (FILE)); \ + } \ + fprintf ((FILE), "\t.ident\t\"GCC: (GNU) %s\"\n", \ + version_string); \ + } while (0) + #endif diff -rc2N gcc-2.1/config/i960.c gcc-2.2.1/config/i960.c *** gcc-2.1/config/i960.c --- gcc-2.2.1/config/i960.c Wed Jun 3 16:31:46 1992 *************** *** 0 **** --- 1,2326 ---- + /* Subroutines used for code generation on intel 80960. + Copyright (C) 1992 Free Software Foundation, Inc. + Contributed by Steven McGeady, Intel Corp. + Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson + Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support. + + This file is part of GNU CC. + + GNU CC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GNU CC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GNU CC; see the file COPYING. If not, write to + the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + #include + + #include "config.h" + #include "rtl.h" + #include "regs.h" + #include "hard-reg-set.h" + #include "real.h" + #include "insn-config.h" + #include "conditions.h" + #include "insn-flags.h" + #include "output.h" + #include "insn-attr.h" + #include "flags.h" + #include "tree.h" + #include "insn-codes.h" + #include "assert.h" + #include "expr.h" + #include "function.h" + #include "recog.h" + #include + + /* Save the operands last given to a compare for use when we + generate a scc or bcc insn. */ + + rtx i960_compare_op0, i960_compare_op1; + + /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS + macro in i960.h. */ + + static int i960_maxbitalignment; + static int i960_last_maxbitalignment; + + /* Used to implement switching between MEM and ALU insn types, for better + C series performance. */ + + enum insn_types i960_last_insn_type; + + /* Where to save/restore register 14 to/from before/after a procedure call + when it holds an argument block pointer. */ + + static rtx g14_save_reg; + + /* The leaf-procedure return register. Set only if this is a leaf routine. */ + + static int i960_leaf_ret_reg; + + /* True if replacing tail calls with jumps is OK. */ + + static int tail_call_ok; + + /* A string containing a list of insns to emit in the epilogue so as to + restore all registers saved by the prologue. Created by the prologue + code as it saves registers away. */ + + char epilogue_string[1000]; + + /* A unique number (per function) for return labels. */ + + static int ret_label = 0; + + #if 0 + /* Handle pragmas for compatibility with Intel's compilers. */ + + /* ??? This is incomplete, since it does not handle all pragmas that the + intel compilers understand. Also, it needs to be rewritten to accept + a stream instead of a string for GCC 2. */ + + void + process_pragma(str) + char *str; + { + int align; + int i; + + if ((i = sscanf (str, " align %d", &align)) == 1) + switch (align) + { + case 0: /* Return to last alignment. */ + align = i960_last_maxbitalignment / 8; + + case 16: /* Byte alignments. */ + case 8: + case 4: + case 2: + case 1: + i960_last_maxbitalignment = i960_maxbitalignment; + i960_maxbitalignment = align * 8; + break; + + default: /* Unknown, silently ignore. */ + break; + } + + /* NOTE: ic960 R3.0 pragma align definition: + + #pragma align [(size)] | (identifier=size[,...]) + #pragma noalign [(identifier)[,...]] + + (all parens are optional) + + - size is [1,2,4,8,16] + - noalign means size==1 + - applies only to component elements of a struct (and union?) + - identifier applies to structure tag (only) + - missing identifier means next struct + + - alignment rules for bitfields need more investigation */ + + /* Should be pragma 'far' or equivalent for callx/balx here. */ + } + #endif + + /* Initialize variables before compiling any files. */ + + void + i960_initialize () + { + if (TARGET_IC_COMPAT2_0) + { + i960_maxbitalignment = 8; + i960_last_maxbitalignment = 128; + } + else + { + i960_maxbitalignment = 128; + i960_last_maxbitalignment = 8; + } + } + + /* Return true if OP can be used as the source of an fp move insn. */ + + int + fpmove_src_operand (op, mode) + rtx op; + enum machine_mode mode; + { + return (GET_CODE (op) == CONST_DOUBLE || general_operand (op, mode)); + } + + #if 0 + /* Return true if OP is a register or zero. */ + + int + reg_or_zero_operand (op, mode) + rtx op; + enum machine_mode mode; + { + return register_operand (op, mode) || op == const0_rtx; + } + #endif + + /* Return truth value of whether OP can be used as an operands in a three + address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */ + + int + arith_operand (op, mode) + rtx op; + enum machine_mode mode; + { + return (register_operand (op, mode) || literal (op, mode)); + } + + /* Return true if OP is a register or a valid floating point literal. */ + + int + fp_arith_operand (op, mode) + rtx op; + enum machine_mode mode; + { + return (register_operand (op, mode) || fp_literal (op, mode)); + } + + /* Return true is OP is a register or a valid signed integer literal. */ + + int + signed_arith_operand (op, mode) + rtx op; + enum machine_mode mode; + { + return (register_operand (op, mode) || signed_literal (op, mode)); + } + + /* Return truth value of whether OP is a integer which fits the + range constraining immediate operands in three-address insns. */ + + int + literal (op, mode) + rtx op; + enum machine_mode mode; + { + return ((GET_CODE (op) == CONST_INT) && INTVAL(op) >= 0 && INTVAL(op) < 32); + } + + /* Return true if OP is a float constant of 1. */ + + int + fp_literal_one (op, mode) + rtx op; + enum machine_mode mode; + { + return (TARGET_NUMERICS && (mode == VOIDmode || mode == GET_MODE (op)) + && (op == CONST1_RTX (mode))); + } + + /* Return true if OP is a float constant of 0. */ + + int + fp_literal_zero (op, mode) + rtx op; + enum machine_mode mode; + { + return (TARGET_NUMERICS && (mode == VOIDmode || mode == GET_MODE (op)) + && (op == CONST0_RTX (mode))); + } + + /* Return true if OP is a valid floating point literal. */ + + int + fp_literal(op, mode) + rtx op; + enum machine_mode mode; + { + return fp_literal_zero (op, mode) || fp_literal_one (op, mode); + } + + /* Return true if OP is a valid signed immediate constant. */ + + int + signed_literal(op, mode) + rtx op; + enum machine_mode mode; + { + return ((GET_CODE (op) == CONST_INT) && INTVAL(op) > -32 && INTVAL(op) < 32); + } + + /* Return truth value of statement that OP is a symbolic memory + operand of mode MODE. */ + + int + symbolic_memory_operand (op, mode) + rtx op; + enum machine_mode mode; + { + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + if (GET_CODE (op) != MEM) + return 0; + op = XEXP (op, 0); + return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST + || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); + } + + /* Return truth value of whether OP is EQ or NE. */ + + int + eq_or_neq (op, mode) + rtx op; + enum machine_mode mode; + { + return (GET_CODE (op) == EQ || GET_CODE (op) == NE); + } + + /* OP is an integer register or a constant. */ + + int + arith32_operand (op, mode) + rtx op; + enum machine_mode mode; + { + if (register_operand (op, mode)) + return 1; + return (CONSTANT_P (op)); + } + + /* Return true if OP is an integer constant which is a power of 2. */ + + int + power2_operand (op,mode) + rtx op; + enum machine_mode mode; + { + if (GET_CODE(op) != CONST_INT) + return 0; + + return exact_log2 (INTVAL (op)) >= 0; + } + + /* If VAL has only one bit set, return the index of that bit. Otherwise + return -1. */ + + int + bitpos (val) + unsigned int val; + { + register int i; + + for (i = 0; val != 0; i++, val >>= 1) + { + if (val & 1) + { + if (val != 1) + return -1; + return i; + } + } + return -1; + } + + /* Return non-zero if OP is a mask, i.e. all one bits are consecutive. + The return value indicates how many consecutive non-zero bits exist + if this is a mask. This is the same as the next function, except that + it does not indicate what the start and stop bit positions are. */ + + int + is_mask (val) + unsigned int val; + { + register int start, end, i; + + start = -1; + for (i = 0; val != 0; val >>= 1, i++) + { + if (val & 1) + { + if (start < 0) + start = i; + + end = i; + continue; + } + /* Still looking for the first bit. */ + if (start < 0) + continue; + + /* We've seen the start of a bit sequence, and now a zero. There + must be more one bits, otherwise we would have exited the loop. + Therefore, it is not a mask. */ + if (val) + return 0; + } + + /* The bit string has ones from START to END bit positions only. */ + return end - start + 1; + } + + /* If VAL is a mask, then return nonzero, with S set to the starting bit + position and E set to the ending bit position of the mask. The return + value indicates how many consecutive bits exist in the mask. This is + the same as the previous function, except that it also indicates the + start and end bit positions of the mask. */ + + int + bitstr (val, s, e) + unsigned int val; + int *s, *e; + { + register int start, end, i; + + start = -1; + end = -1; + for (i = 0; val != 0; val >>= 1, i++) + { + if (val & 1) + { + if (start < 0) + start = i; + + end = i; + continue; + } + + /* Still looking for the first bit. */ + if (start < 0) + continue; + + /* We've seen the start of a bit sequence, and now a zero. There + must be more one bits, otherwise we would have exited the loop. + Therefor, it is not a mask. */ + if (val) + { + start = -1; + end = -1; + break; + } + } + + /* The bit string has ones from START to END bit positions only. */ + *s = start; + *e = end; + return ((start < 0) ? 0 : end - start + 1); + } + + /* Return the machine mode to use for a comparison. */ + + enum machine_mode + select_cc_mode (op, x) + RTX_CODE op; + rtx x; + { + if (op == GTU || op == LTU || op == GEU || op == LEU) + return CC_UNSmode; + return CCmode; + } + + /* X and Y are two things to compare using CODE. Emit the compare insn and + return the rtx for register 36 in the proper mode. */ + + rtx + gen_compare_reg (code, x, y) + enum rtx_code code; + rtx x, y; + { + rtx cc_reg; + enum machine_mode ccmode = SELECT_CC_MODE (code, x); + enum machine_mode mode + = GET_MODE (x) == VOIDmode ? GET_MODE (y) : GET_MODE (x); + + if (mode == SImode) + { + if (! arith_operand (x, mode)) + x = force_reg (SImode, x); + if (! arith_operand (y, mode)) + y = force_reg (SImode, y); + } + + cc_reg = gen_rtx (REG, ccmode, 36); + emit_insn (gen_rtx (SET, VOIDmode, cc_reg, + gen_rtx (COMPARE, ccmode, x, y))); + + return cc_reg; + } + + /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2, + REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar + are 4. Indexed addresses are cost 6. */ + + /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */ + + int + i960_address_cost (x) + rtx x; + { + #if 0 + /* Handled before calling here. */ + if (GET_CODE (x) == REG) + return 1; + #endif + if (GET_CODE (x) == PLUS) + { + rtx base = XEXP (x, 0); + rtx offset = XEXP (x, 1); + + if (GET_CODE (base) == SUBREG) + base = SUBREG_REG (base); + if (GET_CODE (offset) == SUBREG) + offset = SUBREG_REG (offset); + + if (GET_CODE (base) == REG) + { + if (GET_CODE (offset) == REG) + return 2; + if (GET_CODE (offset) == CONST_INT) + { + if ((unsigned)INTVAL (offset) < 2047) + return 2; + return 4; + } + if (CONSTANT_P (offset)) + return 4; + } + if (GET_CODE (base) == PLUS || GET_CODE (base) == MULT) + return 6; + + abort (); + } + if (GET_CODE (x) == MULT) + return 6; + + /* Symbol_refs and other unrecognized addresses are cost 4. */ + return 4; + } + + /* Emit insns to move operands[1] into operands[0]. + + Return 1 if we have written out everything that needs to be done to + do the move. Otherwise, return 0 and the caller will emit the move + normally. */ + + int + emit_move_sequence (operands, mode) + rtx *operands; + enum machine_mode mode; + { + register rtx operand0 = operands[0]; + register rtx operand1 = operands[1]; + + /* We can only store registers to memory. */ + + if (GET_CODE (operand0) == MEM && GET_CODE (operand1) != REG) + operands[1] = force_reg (mode, operand1); + + return 0; + } + + /* Emit insns to load a constant. Uses several strategies to try to use + as few insns as possible. */ + + char * + i960_output_ldconst (dst, src) + register rtx dst, src; + { + register int rsrc1; + register unsigned rsrc2; + enum machine_mode mode = GET_MODE (dst); + rtx operands[4]; + union { long l[2]; double d; } x; + + operands[0] = operands[2] = dst; + operands[1] = operands[3] = src; + + /* Anything that isn't a compile time constant, such as a SYMBOL_REF, + must be a ldconst insn. */ + + if (GET_CODE (src) != CONST_INT && GET_CODE (src) != CONST_DOUBLE) + { + output_asm_insn ("ldconst %1,%0", operands); + return ""; + } + else if (mode == DFmode) + { + rtx first, second; + + if (fp_literal_zero (src, VOIDmode)) + { + if (FP_REG_P (dst)) + return "movrl %1,%0"; + else + return "movl 0,%0"; + } + + #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT + split_double (src, &first, &second); + + output_asm_insn ("# ldconst %1,%0",operands); + + operands[0] = gen_rtx (REG, SImode, REGNO (dst)); + operands[1] = first; + output_asm_insn (i960_output_ldconst (operands[0], operands[1]), + operands); + operands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1); + operands[1] = second; + output_asm_insn (i960_output_ldconst (operands[0], operands[1]), + operands); + return ""; + #else + if (fp_literal_one (src, VOIDmode)) + return "movrl 0f1.0,%0"; + fatal ("inline double constants not supported on this host"); + #endif + } + else if (mode == TImode) + { + /* ??? This is currently not handled at all. */ + abort (); + + /* Note: lowest order word goes in lowest numbered reg. */ + rsrc1 = INTVAL (src); + if (rsrc1 >= 0 && rsrc1 < 32) + return "movq %1,%0"; + else + output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands); + /* Go pick up the low-order word. */ + } + else if (mode == DImode) + { + rtx upperhalf, lowerhalf; + char *string; + + if (GET_CODE (src) == CONST_DOUBLE) + { + upperhalf = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_HIGH (src)); + lowerhalf = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (src)); + } + else if (GET_CODE (src) == CONST_INT) + { + lowerhalf = src; + upperhalf = INTVAL (src) < 0 ? constm1_rtx : const0_rtx; + } + else + abort (); + + /* Note: lowest order word goes in lowest numbered reg. */ + /* Numbers from 0 to 31 can be handled with a single insn. */ + rsrc1 = INTVAL (lowerhalf); + if (upperhalf == const0_rtx && rsrc1 >= 0 && rsrc1 < 32) + return "movl %1,%0"; + + /* Output the upper half with a recursive call. */ + string = i960_output_ldconst (gen_rtx (REG, SImode, REGNO (dst) + 1), + upperhalf); + output_asm_insn (string); + /* The lower word is emitted as normally. */ + } + else if (mode == SFmode) + { + #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT + union { long l; float f; } flt; + + flt.f = (float) *((double *) &CONST_DOUBLE_LOW (src)); + + output_asm_insn ("# ldconst %1,%0",operands); + operands[0] = gen_rtx (REG, SImode, REGNO (dst)); + operands[1] = gen_rtx (CONST_INT, VOIDmode, flt.l); + output_asm_insn (i960_output_ldconst (operands[0], operands[1]), + operands); + #else + if (fp_literal_zero (src, VOIDmode)) + return "movr 0f0.0,%0"; + if (fp_literal_one (src, VOIDmode)) + return "movr 0f1.0,%0"; + fatal ("inline float constants not supported on this host"); + #endif + return ""; + } + else + { + rsrc1 = INTVAL (src); + if (mode == QImode) + { + if (rsrc1 > 0xff) + rsrc1 &= 0xff; + } + else if (mode == HImode) + { + if (rsrc1 > 0xffff) + rsrc1 &= 0xffff; + } + } + + if (rsrc1 >= 0) + { + /* ldconst 0..31,X -> mov 0..31,X */ + if (rsrc1 < 32) + { + if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) + return "lda %1,%0"; + return "mov %1,%0"; + } + + /* ldconst 32..63,X -> add 31,nn,X */ + if (rsrc1 < 63) + { + if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) + return "lda %1,%0"; + operands[1] = gen_rtx (CONST_INT, VOIDmode, rsrc1 - 31); + output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands); + return ""; + } + } + else if (rsrc1 < 0) + { + /* ldconst -1..-31 -> sub 0,0..31,X */ + if (rsrc1 >= -31) + { + /* return 'sub -(%1),0,%0' */ + operands[1] = gen_rtx (CONST_INT, VOIDmode, - rsrc1); + output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands); + return ""; + } + + /* ldconst -32 -> not 31,X */ + if (rsrc1 == -32) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, ~rsrc1); + output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands); + return ""; + } + } + + /* If const is a single bit. */ + if (bitpos (rsrc1) >= 0) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, bitpos (rsrc1)); + output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands); + return ""; + } + + /* If const is a bit string of less than 6 bits (1..31 shifted). */ + if (is_mask (rsrc1)) + { + int s, e; + + if (bitstr (rsrc1, &s, &e) < 6) + { + rsrc2 = ((unsigned int) rsrc1) >> s; + operands[1] = gen_rtx (CONST_INT, VOIDmode, rsrc2); + operands[2] = gen_rtx (CONST_INT, VOIDmode, s); + output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands); + return ""; + } + } + + /* Unimplemented cases: + const is in range 0..31 but rotated around end of word: + ror 31,3,g0 -> ldconst 0xe0000003,g0 + + and any 2 instruction cases that might be worthwhile */ + + output_asm_insn ("ldconst %1,%0", operands); + return ""; + } + + /* Determine if there is an opportunity for a bypass optimization. + Bypass suceeds on the 960K* if the destination of the previous + instruction is the second operand of the current instruction. + Bypass always succeeds on the C*. + + Return 1 if the pattern should interchange the operands. + + CMPBR_FLAG is true if this is for a compare-and-branch insn. + OP1 and OP2 are the two source operands of a 3 operand insn. */ + + int + i960_bypass (insn, op1, op2, cmpbr_flag) + register rtx insn, op1, op2; + int cmpbr_flag; + { + register rtx prev_insn, prev_dest; + + if (TARGET_C_SERIES) + return 0; + + /* Can't do this if op1 isn't a register. */ + if (! REG_P (op1)) + return 0; + + /* Can't do this for a compare-and-branch if both ops aren't regs. */ + if (cmpbr_flag && ! REG_P (op2)) + return 0; + + prev_insn = prev_real_insn (insn); + + if (prev_insn && GET_CODE (prev_insn) == INSN + && GET_CODE (PATTERN (prev_insn)) == SET) + { + prev_dest = SET_DEST (PATTERN (prev_insn)); + if ((GET_CODE (prev_dest) == REG && REGNO (prev_dest) == REGNO (op1)) + || (GET_CODE (prev_dest) == SUBREG + && GET_CODE (SUBREG_REG (prev_dest)) == REG + && REGNO (SUBREG_REG (prev_dest)) == REGNO (op1))) + return 1; + } + return 0; + } + + /* Output the code which declares the function name. This also handles + leaf routines, which have special requirements, and initializes some + global variables. */ + + void + i960_function_name_declare (file, name, fndecl) + FILE *file; + char *name; + tree fndecl; + { + register int i, j; + int leaf_proc_ok; + rtx insn; + + /* Increment global return label. */ + + ret_label++; + + /* Compute whether tail calls and leaf routine optimizations can be performed + for this function. */ + + if (TARGET_TAILCALL) + tail_call_ok = 1; + else + tail_call_ok = 0; + + if (TARGET_LEAFPROC) + leaf_proc_ok = 1; + else + leaf_proc_ok = 0; + + /* Even if nobody uses extra parms, can't have leafroc or tail calls if + argblock, because argblock uses g14 implicitly. */ + + if (current_function_args_size != 0) + { + tail_call_ok = 0; + leaf_proc_ok = 0; + } + + /* See if caller passes in an address to return value. */ + + if (aggregate_value_p (DECL_RESULT (fndecl))) + { + tail_call_ok = 0; + leaf_proc_ok = 0; + } + + /* Can not use tail calls or make this a leaf routine if there is a non + zero frame size. */ + + if (get_frame_size () != 0) + leaf_proc_ok = 0; + + /* I don't understand this condition, and do not think that it is correct. + Apparently this is just checking whether the frame pointer is used, and + we can't trust regs_ever_live[fp] since it is (almost?) always set. */ + + if (tail_call_ok) + for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == INSN + && reg_mentioned_p (frame_pointer_rtx, insn)) + { + tail_call_ok = 0; + break; + } + + /* Check for CALL insns. Can not be a leaf routine if there are any. */ + + if (leaf_proc_ok) + for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == CALL_INSN) + { + leaf_proc_ok = 0; + break; + } + + /* Can not be a leaf routine if any non-call clobbered registers are + used in this function. */ + + if (leaf_proc_ok) + for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (regs_ever_live[i] + && ((! call_used_regs[i]) || (i > 7 && i < 12))) + { + /* Global registers. */ + if (i < 16 && i > 7 && i != 13) + leaf_proc_ok = 0; + /* Local registers. */ + else if (i < 32) + leaf_proc_ok = 0; + } + + /* Now choose a leaf return register, if we can find one, and if it is + OK for this to be a leaf routine. */ + + i960_leaf_ret_reg = -1; + + if (optimize && leaf_proc_ok) + { + for (i960_leaf_ret_reg = -1, i = 0; i < 8; i++) + if (regs_ever_live[i] == 0) + { + i960_leaf_ret_reg = i; + regs_ever_live[i] = 1; + break; + } + } + + /* Do this after choosing the leaf return register, so it will be listed + if one was chosen. */ + + fprintf (file, "\t# Function '%s'\n", name); + fprintf (file, "\t# Registers used: "); + + for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + if (regs_ever_live[i]) + { + fprintf (file, "%s%s ", reg_names[i], call_used_regs[i] ? "" : "*"); + + if (i > 15 && j == 0) + { + fprintf (file,"\n\t#\t\t "); + j++; + } + } + } + + fprintf (file, "\n"); + + if (i960_leaf_ret_reg >= 0) + { + /* Make it a leaf procedure. */ + + if (TREE_PUBLIC (fndecl)) + fprintf (file,"\t.globl %s.lf\n", name); + + fprintf (file, "\t.leafproc\t_%s,%s.lf\n", name, name); + fprintf (file, "_%s:\n", name); + fprintf (file, "\tlda LR%d,g14\n", ret_label); + fprintf (file, "%s.lf:\n", name); + fprintf (file, "\tmov g14,g%d\n", i960_leaf_ret_reg); + + if (TARGET_C_SERIES) + { + fprintf (file, "\tlda 0,g14\n"); + i960_last_insn_type = I_TYPE_MEM; + } + else + { + fprintf (file, "\tmov 0,g14\n"); + i960_last_insn_type = I_TYPE_REG; + } + } + else + { + ASM_OUTPUT_LABEL (file, name); + i960_last_insn_type = I_TYPE_CTRL; + } + } + + /* Compute and return the frame size. */ + + int + compute_frame_size (size) + int size; + { + int actual_fsize; + int outgoing_args_size + = current_function_outgoing_args_size + current_function_pretend_args_size; + + /* The STARTING_FRAME_OFFSET is totally hidden to us as far + as size is concerned. */ + actual_fsize = (size + 15) & -16; + actual_fsize += (outgoing_args_size + 15) & -16; + + return actual_fsize; + } + + /* Output code for the function prologue. */ + + void + i960_function_prologue (file, size) + FILE *file; + unsigned int size; + { + register int i, j, nr; + int n_iregs = 0; + int rsize = 0; + int actual_fsize, offset; + char tmpstr[1000]; + /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved + somewhere. */ + int regs[FIRST_PSEUDO_REGISTER]; + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (regs_ever_live[i] + && ((! call_used_regs[i]) || (i > 7 && i < 12))) + { + regs[i] = -1; + /* Count global registers that need saving. */ + if (i < 16) + n_iregs++; + } + else + regs[i] = 0; + + epilogue_string[0] = '\0'; + + /* First look for local registers to save globals in. */ + for (i = 0; i < 16; i++) + { + if (regs[i] == 0) + continue; + + /* Start at r4, not r3. */ + for (j = 20; j < 32; j++) + { + if (regs[j] != 0) + continue; + + regs[i] = 1; + regs[j] = -1; + regs_ever_live[j] = 1; + nr = 1; + if (i <= 14 && i % 2 == 0 && j <= 30 && j % 2 == 0 + && regs[i+1] != 0 && regs[j+1] == 0) + { + nr = 2; + regs[i+1] = 1; + regs[j+1] = -1; + regs_ever_live[j+1] = 1; + } + if (nr == 2 && i <= 12 && i % 4 == 0 && j <= 28 && j % 4 == 0 + && regs[i+2] != 0 && regs[j+2] == 0) + { + nr = 3; + regs[i+2] = 1; + regs[j+2] = -1; + regs_ever_live[j+2] = 1; + } + if (nr == 3 && regs[i+3] != 0 && regs[j+3] == 0) + { + nr = 4; + regs[i+3] = 1; + regs[j+3] = -1; + regs_ever_live[j+3] = 1; + } + + fprintf (file, "\tmov%s %s,%s\n", + ((nr == 4) ? "q" : + (nr == 3) ? "t" : + (nr == 2) ? "l" : ""), + reg_names[i], reg_names[j]); + sprintf (tmpstr, "\tmov%s %s,%s\n", + ((nr == 4) ? "q" : + (nr == 3) ? "t" : + (nr == 2) ? "l" : ""), + reg_names[j], reg_names[i]); + strcat (epilogue_string, tmpstr); + + n_iregs -= nr; + i += nr-1; + break; + } + } + + /* N_iregs is now the number of global registers that haven't been saved + yet. */ + + rsize = (n_iregs * 4); + actual_fsize = compute_frame_size (size) + rsize; + #if 0 + /* ??? The 1.2.1 compiler does this also. This is meant to round the frame + size up to the nearest multiple of 16. I don't know whether this is + necessary, or even desirable. + + The frame pointer must be aligned, but the call instruction takes care of + that. If we leave the stack pointer unaligned, we may save a little on + dynamic stack allocation. And we don't lose, at least according to the + i960CA manual. */ + actual_fsize = (actual_fsize + 15) & ~0xF; + #endif + + /* Allocate space for register save and locals. */ + if (actual_fsize > 0) + { + if (actual_fsize < 32) + fprintf (file, "\taddo %d,sp,sp\n", actual_fsize); + else + fprintf (file, "\tlda\t%d(sp),sp\n", actual_fsize); + } + + /* Take hardware register save area created by the call instruction + into account. */ + offset = compute_frame_size (size) + 64; + /* Save registers on stack if needed. */ + for (i = 0, j = n_iregs; j > 0 && i < 16; i++) + { + if (regs[i] != -1) + continue; + + nr = 1; + + if (i <= 14 && i % 2 == 0 && regs[i+1] == -1 && offset % 2 == 0) + nr = 2; + + if (nr == 2 && i <= 12 && i % 4 == 0 && regs[i+2] == -1 + && offset % 4 == 0) + nr = 3; + + if (nr == 3 && regs[i+3] == -1) + nr = 4; + + fprintf (file,"\tst%s %s,%d(fp)\n", + ((nr == 4) ? "q" : + (nr == 3) ? "t" : + (nr == 2) ? "l" : ""), + reg_names[i], offset); + sprintf (tmpstr,"\tld%s %d(fp),%s\n", + ((nr == 4) ? "q" : + (nr == 3) ? "t" : + (nr == 2) ? "l" : ""), + offset, reg_names[i]); + strcat (epilogue_string, tmpstr); + i += nr-1; + j -= nr; + offset += nr * 4; + } + + if (actual_fsize == 0 && size == 0 && rsize == 0) + return; + + fprintf (file, "\t#Prologue stats:\n"); + fprintf (file, "\t# Total Frame Size: %d bytes\n", actual_fsize); + + if (size) + fprintf (file, "\t# Local Variable Size: %d bytes\n", size); + if (rsize) + fprintf (file, "\t# Register Save Size: %d regs, %d bytes\n", + n_iregs, rsize); + fprintf (file, "\t#End Prologue#\n"); + } + + /* Output code for the function epilogue. */ + + void + i960_function_epilogue (file, size) + FILE *file; + unsigned int size; + { + if (i960_leaf_ret_reg >= 0) + { + fprintf (file, "LR%d: ret\n", ret_label); + return; + } + + if (*epilogue_string == 0) + { + register rtx tmp; + + /* Emit a return insn, but only if control can fall through to here. */ + + tmp = get_last_insn (); + while (tmp) + { + if (GET_CODE (tmp) == BARRIER) + return; + if (GET_CODE (tmp) == CODE_LABEL) + break; + if (GET_CODE (tmp) == JUMP_INSN) + { + if (GET_CODE (PATTERN (tmp)) == RETURN) + return; + break; + } + if (GET_CODE (tmp) == NOTE) + { + tmp = PREV_INSN (tmp); + continue; + } + break; + } + fprintf (file, "LR%d: ret\n", ret_label); + return; + } + + fprintf (file, "LR%d:\n", ret_label); + + fprintf (file, "\t#EPILOGUE#\n"); + + /* Output the string created by the prologue which will restore all + registers saved by the prologue. */ + + if (epilogue_string[0] != '\0') + fprintf (file, "%s", epilogue_string); + + /* Must clear g14 on return. */ + + if (current_function_args_size != 0) + fprintf (file, "\tmov 0,g14\n"); + + fprintf (file, "\tret\n"); + fprintf (file, "\t#End Epilogue#\n"); + } + + /* Output code for a call insn. */ + + char * + i960_output_call_insn (target, argsize_rtx, insn) + register rtx target, argsize_rtx, insn; + { + int non_indirect; + int argsize = INTVAL (argsize_rtx); + rtx nexti = next_real_insn (insn); + rtx operands[1]; + + operands[0] = target; + + non_indirect = ((GET_CODE (target) == MEM) + && (GET_CODE (XEXP (target, 0)) == SYMBOL_REF)); + + /* Nexti could be zero if the called routine is volatile. */ + if (optimize && (*epilogue_string == 0) && argsize == 0 && tail_call_ok + && (nexti == 0 || GET_CODE (PATTERN (nexti)) == RETURN)) + { + /* Delete following return insn. */ + if (nexti && no_labels_between_p (insn, nexti)) + delete_insn (nexti); + output_asm_insn (non_indirect ? "b %0" : "bx %0", + operands); + return "# notreached"; + } + + output_asm_insn (non_indirect ? "callj %0" : "callx %0", operands); + return ""; + } + + /* Output code for a return insn. */ + + char * + i960_output_ret_insn (insn) + register rtx insn; + { + static char lbuf[20]; + + if (*epilogue_string != 0) + { + if (! TARGET_CODE_ALIGN && next_real_insn (insn) == 0) + return ""; + + sprintf (lbuf, "b LR%d", ret_label); + return lbuf; + } + + if (current_function_args_size != 0) + output_asm_insn ("mov 0,g14", 0); + + if (i960_leaf_ret_reg >= 0) + { + sprintf (lbuf, "bx (%s)", reg_names[i960_leaf_ret_reg]); + return lbuf; + } + return "ret"; + } + + #if 0 + /* Return a character string representing the branch prediction + opcode to be tacked on an instruction. This must at least + return a null string. */ + + char * + i960_br_predict_opcode (lab_ref, insn) + rtx lab_ref, insn; + { + if (TARGET_BRANCH_PREDICT) + { + unsigned long label_uid; + + if (GET_CODE (lab_ref) == CODE_LABEL) + label_uid = INSN_UID (lab_ref); + else if (GET_CODE (lab_ref) == LABEL_REF) + label_uid = INSN_UID (XEXP (lab_ref, 0)); + else + return ".f"; + + /* If not optimizing, then the insn_addresses array will not be + valid. In this case, always return ".t" since most branches + are taken. If optimizing, return .t for backward branches + and .f for forward branches. */ + if (! optimize + || insn_addresses[label_uid] < insn_addresses[INSN_UID (insn)]) + return ".t"; + return ".f"; + } + + return ""; + } + #endif + + /* Print the operand represented by rtx X formatted by code CODE. */ + + void + i960_print_operand (file, x, code) + FILE *file; + rtx x; + char code; + { + enum rtx_code rtxcode = GET_CODE (x); + + if (rtxcode == REG) + { + switch (code) + { + case 'D': + /* Second reg of a double. */ + fprintf (file, "%s", reg_names[REGNO (x)+1]); + break; + + case 0: + fprintf (file, "%s", reg_names[REGNO (x)]); + break; + + default: + abort (); + } + return; + } + else if (rtxcode == MEM) + { + output_address (XEXP (x, 0)); + return; + } + else if (rtxcode == CONST_INT) + { + if (INTVAL (x) > 9999 || INTVAL (x) < -999) + fprintf (file, "0x%x", INTVAL (x)); + else + fprintf (file, "%d", INTVAL (x)); + return; + } + else if (rtxcode == CONST_DOUBLE) + { + double d; + + if (x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode)) + { + fprintf (file, "0f0.0"); + return; + } + else if (x == CONST1_RTX (DFmode) || x == CONST1_RTX (SFmode)) + { + fprintf (file, "0f1.0"); + return; + } + + /* This better be a comment. */ + REAL_VALUE_FROM_CONST_DOUBLE (d, x); + fprintf (file, "%#g", d); + return; + } + + switch(code) + { + case 'B': + /* Branch or jump, depending on assembler. */ + if (TARGET_ASM_COMPAT) + fputs ("j", file); + else + fputs ("b", file); + break; + + case 'S': + /* Sign of condition. */ + if ((rtxcode == EQ) || (rtxcode == NE) || (rtxcode == GTU) + || (rtxcode == LTU) || (rtxcode == GEU) || (rtxcode == LEU)) + fputs ("o", file); + else if ((rtxcode == GT) || (rtxcode == LT) + || (rtxcode == GE) || (rtxcode == LE)) + fputs ("i", file); + else + abort(); + break; + + case 'I': + /* Inverted condition. */ + rtxcode = reverse_condition (rtxcode); + goto normal; + + case 'X': + /* Inverted condition w/ reversed operands. */ + rtxcode = reverse_condition (rtxcode); + /* Fallthrough. */ + + case 'R': + /* Reversed operand condition. */ + rtxcode = swap_condition (rtxcode); + /* Fallthrough. */ + + case 'C': + /* Normal condition. */ + normal: + if (rtxcode == EQ) { fputs ("e", file); return; } + else if (rtxcode == NE) { fputs ("ne", file); return; } + else if (rtxcode == GT) { fputs ("g", file); return; } + else if (rtxcode == GTU) { fputs ("g", file); return; } + else if (rtxcode == LT) { fputs ("l", file); return; } + else if (rtxcode == LTU) { fputs ("l", file); return; } + else if (rtxcode == GE) { fputs ("ge", file); return; } + else if (rtxcode == GEU) { fputs ("ge", file); return; } + else if (rtxcode == LE) { fputs ("le", file); return; } + else if (rtxcode == LEU) { fputs ("le", file); return; } + else abort (); + break; + + case 0: + output_addr_const (file, x); + break; + + default: + abort (); + } + + return; + } + + /* Print a memory address as an operand to reference that memory location. + + This is exactly the same as legitimate_address_p, except that it the prints + addresses instead of recognizing them. */ + + void + i960_print_operand_addr (file, addr) + FILE *file; + register rtx addr; + { + rtx breg, ireg; + rtx scale, offset; + + ireg = 0; + breg = 0; + offset = 0; + scale = const1_rtx; + + if (GET_CODE (addr) == REG) + breg = addr; + else if (CONSTANT_P (addr)) + offset = addr; + else if (GET_CODE (addr) == PLUS) + { + rtx op0, op1; + + op0 = XEXP (addr, 0); + op1 = XEXP (addr, 1); + + if (GET_CODE (op0) == REG) + { + breg = op0; + if (GET_CODE (op1) == REG) + ireg = op1; + else if (CONSTANT_P (op1)) + offset = op1; + else + abort (); + } + else if (GET_CODE (op0) == PLUS) + { + if (GET_CODE (XEXP (op0, 0)) == MULT) + { + ireg = XEXP (XEXP (op0, 0), 0); + scale = XEXP (XEXP (op0, 0), 1); + if (GET_CODE (XEXP (op0, 1)) == REG) + { + breg = XEXP (op0, 1); + offset = op1; + } + else + abort (); + } + else if (GET_CODE (XEXP (op0, 0)) == REG) + { + breg = XEXP (op0, 0); + if (GET_CODE (XEXP (op0, 1)) == REG) + { + ireg = XEXP (op0, 1); + offset = op1; + } + else + abort (); + } + else + abort (); + } + else if (GET_CODE (op0) == MULT) + { + ireg = XEXP (op0, 0); + scale = XEXP (op0, 1); + if (GET_CODE (op1) == REG) + breg = op1; + else if (CONSTANT_P (op1)) + offset = op1; + else + abort (); + } + else + abort (); + } + else if (GET_CODE (addr) == MULT) + { + breg = XEXP (addr, 0); + scale = XEXP (addr, 1); + } + else + abort (); + + if (offset) + output_addr_const (file, offset); + if (breg) + fprintf (file, "(%s)", reg_names[REGNO (breg)]); + if (ireg) + fprintf (file, "[%s*%d]", reg_names[REGNO (ireg)], INTVAL (scale)); + } + + /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression + that is a valid memory address for an instruction. + The MODE argument is the machine mode for the MEM expression + that wants to use this address. + + On 80960, legitimate addresses are: + base ld (g0),r0 + disp (12 or 32 bit) ld foo,r0 + base + index ld (g0)[g1*1],r0 + base + displ ld 0xf00(g0),r0 + base + index*scale + displ ld 0xf00(g0)[g1*4],r0 + index*scale + base ld (g0)[g1*4],r0 + index*scale + displ ld 0xf00[g1*4],r0 + index*scale ld [g1*4],r0 + index + base + displ ld 0xf00(g0)[g1*1],r0 + + In each case, scale can be 1, 2, 4, 8, or 16. */ + + /* This is exactly the same as i960_print_operand_addr, except that + it recognizes addresses instead of printing them. + + It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should + convert common non-canonical forms to canonical form so that they will + be recognized. */ + + int + legitimate_address_p (mode, addr, strict) + enum machine_mode mode; + register rtx addr; + int strict; + { + if (GET_CODE (addr) == REG) + return (strict ? REG_OK_FOR_BASE_P_STRICT (addr) + : REG_OK_FOR_BASE_P (addr)); + else if (CONSTANT_P (addr)) + return 1; + else if (GET_CODE (addr) == PLUS) + { + rtx op0, op1; + + if (! TARGET_COMPLEX_ADDR && ! reload_completed) + return 0; + + op0 = XEXP (addr, 0); + op1 = XEXP (addr, 1); + + if (GET_CODE (op0) == REG) + { + if (! (strict ? REG_OK_FOR_BASE_P_STRICT (op0) + : REG_OK_FOR_BASE_P (op0))) + return 0; + + if (GET_CODE (op1) == REG) + return (strict ? REG_OK_FOR_INDEX_P_STRICT (op1) + : REG_OK_FOR_INDEX_P (op1)); + else if (CONSTANT_P (op1)) + return 1; + else + return 0; + } + else if (GET_CODE (op0) == PLUS) + { + if (GET_CODE (XEXP (op0, 0)) == MULT) + { + if (! (GET_CODE (XEXP (XEXP (op0, 0), 0)) == REG + && (strict ? REG_OK_FOR_INDEX_P_STRICT (XEXP (XEXP (op0, 0), 0)) + : REG_OK_FOR_INDEX_P (XEXP (XEXP (op0, 0), 0))) + && SCALE_TERM_P (XEXP (XEXP (op0, 0), 1)))) + return 0; + + if (GET_CODE (XEXP (op0, 1)) == REG) + return ((strict ? REG_OK_FOR_BASE_P_STRICT (XEXP (op0, 1)) + : REG_OK_FOR_BASE_P (XEXP (op0, 1))) + && CONSTANT_P (op1)); + else + return 0; + } + else if (GET_CODE (XEXP (op0, 0)) == REG) + { + if (! (strict ? REG_OK_FOR_BASE_P_STRICT (XEXP (op0, 0)) + : REG_OK_FOR_BASE_P (XEXP (op0, 0)))) + return 0; + + if (GET_CODE (XEXP (op0, 1)) == REG) + return ((strict ? REG_OK_FOR_INDEX_P_STRICT (XEXP (op0, 1)) + : REG_OK_FOR_INDEX_P (XEXP (op0, 1))) + && CONSTANT_P (op1)); + else + return 0; + } + else + return 0; + } + else if (GET_CODE (op0) == MULT) + { + if (! (GET_CODE (XEXP (op0, 0)) == REG + && (strict ? REG_OK_FOR_INDEX_P_STRICT (XEXP (op0, 0)) + : REG_OK_FOR_INDEX_P (XEXP (op0, 0))) + && SCALE_TERM_P (XEXP (op0, 1)))) + return 0; + + if (GET_CODE (op1) == REG) + return (strict ? REG_OK_FOR_BASE_P_STRICT (op1) + : REG_OK_FOR_BASE_P (op1)); + else if (CONSTANT_P (op1)) + return 1; + else + return 0; + } + else + return 0; + } + else if (GET_CODE (addr) == MULT) + { + if (! TARGET_COMPLEX_ADDR && ! reload_completed) + return 0; + + return (GET_CODE (XEXP (addr, 0)) == REG + && (strict ? REG_OK_FOR_INDEX_P_STRICT (XEXP (addr, 0)) + : REG_OK_FOR_INDEX_P (XEXP (addr, 0))) + && SCALE_TERM_P (XEXP (addr, 1))); + } + else + return 0; + } + + /* Try machine-dependent ways of modifying an illegitimate address + to be legitimate. If we find one, return the new, valid address. + This macro is used in only one place: `memory_address' in explow.c. + + This converts some non-canonical addresses to canonical form so they + can be recognized. */ + + rtx + legitimize_address (x, oldx, mode) + register rtx x; + register rtx oldx; + enum machine_mode mode; + { + if (GET_CODE (x) == SYMBOL_REF) + { + abort (); + x = copy_to_reg (x); + } + + if (! TARGET_COMPLEX_ADDR && ! reload_completed) + return x; + + /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const))) + into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be + created by virtual register instantiation, register elimination, and + similar optimizations. */ + if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT + && GET_CODE (XEXP (x, 1)) == PLUS) + x = gen_rtx (PLUS, Pmode, + gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)), + XEXP (XEXP (x, 1), 1)); + + /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const) + into (plus (plus (mult (reg) (const)) (reg)) (const)). */ + else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT + && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS + && CONSTANT_P (XEXP (x, 1))) + { + rtx constant, other; + + if (GET_CODE (XEXP (x, 1)) == CONST_INT) + { + constant = XEXP (x, 1); + other = XEXP (XEXP (XEXP (x, 0), 1), 1); + } + else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT) + { + constant = XEXP (XEXP (XEXP (x, 0), 1), 1); + other = XEXP (x, 1); + } + else + constant = 0; + + if (constant) + x = gen_rtx (PLUS, Pmode, + gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0), + XEXP (XEXP (XEXP (x, 0), 1), 0)), + plus_constant (other, INTVAL (constant))); + } + + return x; + } + + #if 0 + /* Return the most stringent alignment that we are willing to consider + objects of size SIZE and known alignment ALIGN as having. */ + + int + i960_alignment (size, align) + int size; + int align; + { + int i; + + if (! TARGET_STRICT_ALIGN) + if (TARGET_IC_COMPAT2_0 || align >= 4) + { + i = i960_object_bytes_bitalign (size) / BITS_PER_UNIT; + if (i > align) + align = i; + } + + return align; + } + #endif + + /* Modes for condition codes. */ + #define C_MODES \ + ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode)) + + /* Modes for single-word (and smaller) quantities. */ + #define S_MODES \ + (~C_MODES \ + & ~ ((1 << (int) DImode) | (1 << (int) TImode) \ + | (1 << (int) DFmode) | (1 << (int) TFmode))) + + /* Modes for double-word (and smaller) quantities. */ + #define D_MODES \ + (~C_MODES \ + & ~ ((1 << (int) TImode) | (1 << (int) TFmode))) + + /* Modes for quad-word quantities. */ + #define T_MODES (~C_MODES) + + /* Modes for single-float quantities. */ + #define SF_MODES ((1 << (int) SFmode)) + + /* Modes for double-float quantities. */ + #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode)) + + /* Modes for quad-float quantities. */ + #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode)) + + unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] = { + T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, + T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, + T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, + T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, + + TF_MODES, TF_MODES, TF_MODES, TF_MODES, C_MODES}; + + + /* Return the minimum alignment of an expression rtx X in bytes. This takes + advantage of machine specific facts, such as knowing that the frame pointer + is always 16 byte aligned. */ + + int + i960_expr_alignment (x, size) + rtx x; + int size; + { + int align = 1; + + if (x == 0) + return 1; + + switch (GET_CODE(x)) + { + case CONST_INT: + align = INTVAL(x); + + if ((align & 0xf) == 0) + align = 16; + else if ((align & 0x7) == 0) + align = 8; + else if ((align & 0x3) == 0) + align = 4; + else if ((align & 0x1) == 0) + align = 2; + else + align = 1; + break; + + case PLUS: + align = MIN (i960_expr_alignment (XEXP (x, 0), size), + i960_expr_alignment (XEXP (x, 1), size)); + break; + + case SYMBOL_REF: + /* If this is a valid program, objects are guaranteed to be + correctly aligned for whatever size the reference actually is. */ + align = i960_object_bytes_bitalign (size) / BITS_PER_UNIT; + break; + + case REG: + if (REGNO (x) == FRAME_POINTER_REGNUM) + align = 16; + break; + + case ASHIFT: + case LSHIFT: + align = i960_expr_alignment (XEXP (x, 0)); + + if (GET_CODE (XEXP (x, 1)) == CONST_INT) + { + align = align << INTVAL (XEXP (x, 1)); + align = MIN (align, 16); + } + break; + + case MULT: + align = (i960_expr_alignment (XEXP (x, 0), size) * + i960_expr_alignment (XEXP (x, 1), size)); + + align = MIN (align, 16); + break; + } + + return align; + } + + /* Return true if it is possible to reference both BASE and OFFSET, which + have alignment at least as great as 4 byte, as if they had alignment valid + for an object of size SIZE. */ + + int + i960_improve_align (base, offset, size) + rtx base; + rtx offset; + int size; + { + int i, j; + + /* We have at least a word reference to the object, so we know it has to + be aligned at least to 4 bytes. */ + + i = MIN (i960_expr_alignment (base, 4), + i960_expr_alignment (offset, 4)); + + i = MAX (i, 4); + + /* We know the size of the request. If strict align is not enabled, we + can guess that the alignment is OK for the requested size. */ + + if (! TARGET_STRICT_ALIGN) + if ((j = (i960_object_bytes_bitalign (size) / BITS_PER_UNIT)) > i) + i = j; + + return (i >= size); + } + + /* Return true if it is possible to access BASE and OFFSET, which have 4 byte + (SImode) alignment as if they had 16 byte (TImode) alignment. */ + + int + i960_si_ti (base, offset) + rtx base; + rtx offset; + { + return i960_improve_align (base, offset, 16); + } + + /* Return true if it is possible to access BASE and OFFSET, which have 4 byte + (SImode) alignment as if they had 8 byte (DImode) alignment. */ + + int + i960_si_di (base, offset) + rtx base; + rtx offset; + { + return i960_improve_align (base, offset, 8); + } + + /* Return raw values of size and alignment (in words) for the data + type being accessed. These values will be rounded by the caller. */ + + static void + i960_arg_size_and_align (mode, type, size_out, align_out) + enum machine_mode mode; + tree type; + int *size_out; + int *align_out; + { + int size, align; + + /* Use formal alignment requirements of type being passed, except make + it at least a word. If we don't have a type, this is a library call, + and the parm has to be of scalar type. In this case, consider its + formal alignment requirement to be its size in words. */ + + if (mode == BLKmode) + size = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; + else if (mode == VOIDmode) + { + /* End of parm list. */ + assert (type != 0 && TYPE_MODE (type) == VOIDmode); + size = 1; + } + else + size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; + + if (type == 0) + align = size; + else if (TYPE_ALIGN (type) >= BITS_PER_WORD) + align = TYPE_ALIGN (type) / BITS_PER_WORD; + else + align = 1; + + *size_out = size; + *align_out = align; + } + + /* On the 80960 the first 12 args are in registers and the rest are pushed. + Any arg that is bigger than 4 words is placed on the stack and all + subsequent arguments are placed on the stack. + + Additionally, parameters with an alignment requirement stronger than + a word must be be aligned appropriately. */ + + /* Update CUM to advance past an argument described by MODE and TYPE. */ + + void + i960_function_arg_advance (cum, mode, type, named) + CUMULATIVE_ARGS *cum; + enum machine_mode mode; + tree type; + int named; + { + int size, align; + + i960_arg_size_and_align (mode, type, &size, &align); + + if (named == 0 || size > 4 || cum->ca_nstackparms != 0 + || (size + ROUND (cum->ca_nregparms, align)) > NPARM_REGS + || MUST_PASS_IN_STACK (mode, type)) + cum->ca_nstackparms = ROUND (cum->ca_nstackparms, align) + size; + else + cum->ca_nregparms = ROUND (cum->ca_nregparms, align) + size; + } + + /* Return the register that the argument described by MODE and TYPE is + passed in, or else return 0 if it is passed on the stack. */ + + rtx + i960_function_arg (cum, mode, type, named) + CUMULATIVE_ARGS *cum; + enum machine_mode mode; + tree type; + int named; + { + rtx ret; + int size, align; + + i960_arg_size_and_align (mode, type, &size, &align); + + if (named == 0 || size > 4 || cum->ca_nstackparms != 0 + || (size + ROUND (cum->ca_nregparms, align)) > NPARM_REGS + || MUST_PASS_IN_STACK (mode, type)) + { + cum->ca_nstackparms = ROUND (cum->ca_nstackparms, align); + ret = 0; + } + else + { + cum->ca_nregparms = ROUND (cum->ca_nregparms, align); + ret = gen_rtx (REG, mode, cum->ca_nregparms); + } + + return ret; + } + + /* Return the rtx for the register representing the return value, or 0 + if the return value must be passed through the stack. */ + + rtx + i960_function_value (type) + tree type; + { + int mode = TYPE_MODE (type); + + if (mode == BLKmode) + { + unsigned int size = int_size_in_bytes (type); + + if (size <= 16) + mode = mode_for_size (i960_object_bytes_bitalign (size), MODE_INT, 0); + } + + if (mode == BLKmode || mode == VOIDmode) + /* Tell stmt.c and expr.c to pass in address */ + return 0; + else + return gen_rtx (REG, mode, 0); + } + + /* Floating-point support. */ + + void + i960_output_double (file, value) + FILE *file; + double value; + { + if (REAL_VALUE_ISINF (value)) + { + fprintf (file, "\t.word 0\n"); + fprintf (file, "\t.word 0x7ff00000 # Infinity\n"); + } + else + fprintf (file, "\t.double 0d%.17e\n", (value)); + } + + void + i960_output_float (file, value) + FILE *file; + double value; + { + if (REAL_VALUE_ISINF (value)) + fprintf (file, "\t.word 0x7f800000 # Infinity\n"); + else + fprintf (file, "\t.float 0f%.12e\n", (value)); + } + + /* Return the number of bits that an object of size N bytes is aligned to. */ + + int + i960_object_bytes_bitalign (n) + int n; + { + if (n > 8) n = 128; + else if (n > 4) n = 64; + else if (n > 2) n = 32; + else if (n > 1) n = 16; + else n = 8; + + return n; + } + + /* Compute the size of an aggregate type TSIZE. */ + + tree + i960_round_size (tsize) + tree tsize; + { + int size, align; + + if (TREE_CODE (tsize) != INTEGER_CST) + return tsize; + + size = TREE_INT_CST_LOW (tsize); + align = i960_object_bytes_bitalign (size / BITS_PER_UNIT); + + /* Handle #pragma align. */ + if (align > i960_maxbitalignment) + align = i960_maxbitalignment; + + if (size % align) + size = ((size / align) + 1) * align; + + return size_int (size); + } + + /* Compute the alignment for an aggregate type TSIZE. */ + + int + i960_round_align (align, tsize) + int align; + tree tsize; + { + if (TREE_CODE (tsize) != INTEGER_CST) + return align; + + align = i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize) + / BITS_PER_UNIT); + return align; + } + + /* Do any needed setup for a varargs function. For the i960, we must + create a register paramter block if one doesn't exist, and then copy + all register parameters to memory. */ + + void + i960_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) + CUMULATIVE_ARGS *cum; + enum machine_mode mode; + tree type; + int *pretend_size; + int no_rtl; + { + if (cum->ca_nregparms < NPARM_REGS) + { + int first_reg_offset = cum->ca_nregparms; + + if (first_reg_offset > NPARM_REGS) + first_reg_offset = NPARM_REGS; + + if (! (no_rtl) && first_reg_offset != NPARM_REGS) + { + rtx label = gen_label_rtx (); + emit_insn (gen_cmpsi (arg_pointer_rtx, const0_rtx)); + emit_jump_insn (gen_bne (label)); + emit_insn (gen_rtx (SET, VOIDmode, arg_pointer_rtx, + stack_pointer_rtx)); + emit_insn (gen_rtx (SET, VOIDmode, stack_pointer_rtx, + memory_address (SImode, + plus_constant (stack_pointer_rtx, + 48)))); + emit_label (label); + move_block_from_reg + (first_reg_offset, + gen_rtx (MEM, BLKmode, virtual_incoming_args_rtx), + NPARM_REGS - first_reg_offset); + } + *pretend_size = (NPARM_REGS - first_reg_offset) * UNITS_PER_WORD; + } + } + + /* Calculate the final size of the reg parm stack space for the current + function, based on how many bytes would be allocated on the stack. */ + + int + i960_final_reg_parm_stack_space (const_size, var_size) + int const_size; + tree var_size; + { + if (var_size || const_size > 48) + return 48; + else + return 0; + } + + /* Calculate the size of the reg parm stack space. This is a bit complicated + on the i960. */ + + int + i960_reg_parm_stack_space (fndecl) + tree fndecl; + { + /* In this case, we are called from emit_library_call, and we don't need + to pretend we have more space for parameters than what's apparent. */ + if (fndecl == 0) + return 0; + + /* In this case, we are called from locate_and_pad_parms when we're + not IN_REGS, so we have an arg block. */ + if (fndecl != current_function_decl) + return 48; + + /* Otherwise, we have an arg block if the current function has more than + 48 bytes of parameters. */ + if (current_function_args_size != 0) + return 48; + else + return 0; + } + + /* Return the register class of a scratch register needed to copy IN into + or out of a register in CLASS in MODE. If it can be done directly, + NO_REGS is returned. */ + + enum reg_class + secondary_reload_class (class, mode, in) + enum reg_class class; + enum machine_mode mode; + rtx in; + { + int regno = -1; + + if (GET_CODE (in) == REG || GET_CODE (in) == SUBREG) + regno = true_regnum (in); + + /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put + LOCAL_OR_GLOBAL_REGS into anything. */ + if (class == LOCAL_OR_GLOBAL_REGS || class == LOCAL_REGS + || class == GLOBAL_REGS || (regno >= 0 && regno < 32)) + return NO_REGS; + + /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */ + if (class == FP_REGS + && ((regno >= 0 && regno <= FIRST_PSEUDO_REGISTER) + || in == CONST0_RTX (mode) || in == CONST1_RTX (mode))) + return NO_REGS; + + return LOCAL_OR_GLOBAL_REGS; + } + + /* Emit the code necessary for a procedure call. Return value is needed + after the call if target is non-zero. */ + + void + i960_expand_call (first_operand, second_operand, target) + rtx first_operand, second_operand, target; + { + /* Used to ensure that g14_save_reg is initialized once and only once + for each function if it is needed. */ + static char *this_function_name = 0; + int frob_g14 = 0; + + if (this_function_name != current_function_name) + { + rtx seq, first; + struct sequence_stack *seq_stack; + + this_function_name = current_function_name; + + /* If the current function has an argument block, then save g14 into + a pseudo at the top of the function and restore it after this + function call. If the current function has no argument block, + then g14 is zero before and after the call. */ + + if (current_function_args_size != 0) + { + start_sequence (); + seq_stack = sequence_stack; + while (seq_stack->next) + seq_stack = seq_stack->next; + first = seq_stack->first; + g14_save_reg = copy_to_reg (arg_pointer_rtx); + seq = gen_sequence (); + end_sequence (); + emit_insn_after (seq, first); + } + } + + if (current_function_args_size != 0) + frob_g14 = 1; + + if (GET_CODE (second_operand) != CONST_INT || INTVAL (second_operand) > 48) + { + /* Calling a function needing an argument block. */ + emit_insn (gen_rtx (SET, VOIDmode, arg_pointer_rtx, + virtual_outgoing_args_rtx)); + } + else + { + /* Calling a normal function -- only set to zero if we know our g14 + is nonzero. */ + if (frob_g14) + emit_insn (gen_rtx (SET, VOIDmode, arg_pointer_rtx, const0_rtx)); + } + + if (target) + emit_call_insn (gen_rtx (SET, VOIDmode, target, + gen_rtx (CALL, VOIDmode, first_operand, + second_operand))); + else + emit_call_insn (gen_rtx (CALL, VOIDmode, first_operand, second_operand)); + + if (frob_g14) + emit_insn (gen_rtx (SET, VOIDmode, arg_pointer_rtx, g14_save_reg)); + else if (GET_CODE (second_operand) != CONST_INT + || INTVAL (second_operand) > 48) + { + /* Calling a function needing an argument block. It will have set + reg14 back to zero before returning, so we must emit a clobber here + to tell cse that g14 has changed. */ + emit_insn (gen_rtx (CLOBBER, VOIDmode, arg_pointer_rtx)); + } + } + + /* Look at the opcode P, and set i96_last_insn_type to indicate which + function unit it executed on. */ + + /* ??? This would make more sense as an attribute. */ + + void + i960_scan_opcode (p) + char *p; + { + switch (*p) + { + case 'a': + case 'd': + case 'e': + case 'm': + case 'n': + case 'o': + case 'r': + /* Ret is not actually of type REG, but it won't matter, because no + insn will ever follow it. */ + case 'u': + case 'x': + i960_last_insn_type = I_TYPE_REG; + break; + + case 'b': + if (p[1] == 'x' || p[3] == 'x') + i960_last_insn_type = I_TYPE_MEM; + i960_last_insn_type = I_TYPE_CTRL; + break; + + case 'f': + case 't': + i960_last_insn_type = I_TYPE_CTRL; + break; + + case 'c': + if (p[1] == 'a') + { + if (p[4] == 'x') + i960_last_insn_type = I_TYPE_MEM; + else + i960_last_insn_type = I_TYPE_CTRL; + } + else if (p[1] == 'm') + { + if (p[3] == 'd') + i960_last_insn_type = I_TYPE_REG; + else if (p[4] == 'b' || p[4] == 'j') + i960_last_insn_type = I_TYPE_CTRL; + else + i960_last_insn_type = I_TYPE_REG; + } + else + i960_last_insn_type = I_TYPE_REG; + break; + + case 'l': + i960_last_insn_type = I_TYPE_MEM; + break; + + case 's': + if (p[1] == 't') + i960_last_insn_type = I_TYPE_MEM; + else + i960_last_insn_type = I_TYPE_REG; + break; + } + } diff -rc2N gcc-2.1/config/i960.h gcc-2.2.1/config/i960.h *** gcc-2.1/config/i960.h --- gcc-2.2.1/config/i960.h Wed May 27 17:57:09 1992 *************** *** 0 **** --- 1,1481 ---- + /* Definitions of target machine for GNU compiler, for Intel 80960 + Copyright (C) 1992 Free Software Foundation, Inc. + Contributed by Steven McGeady, Intel Corp. + Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson + Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support. + + This file is part of GNU CC. + + GNU CC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GNU CC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GNU CC; see the file COPYING. If not, write to + the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + /* Note that some other tm.h files may include this one and then override + many of the definitions that relate to assembler syntax. */ + + /* Names to predefine in the preprocessor for this target machine. */ + #define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960" + + /* Name to predefine in the preprocessor for processor variations. */ + #define CPP_SPEC "%{mic*:-D__i960\ + %{mka:-D__i960KA}%{mkb:-D__i960KB}%{mkc:-D__i960KC}\ + %{msa:-D__i960SA}%{msb:-D__i960SB}%{msc:-D__i960SC}\ + %{mmc:-D__i960MC}\ + %{mca:-D__i960CA}%{mcb:-D__i960CB}%{mcc:-D__i960CC}\ + %{mcf:-D__i960CF}}\ + %{mka:-D__i960KA__ -D__i960_KA__}\ + %{mkb:-D__i960KB__ -D__i960_KB__}\ + %{mkc:-D__i960KC__ -D__i960_KC__}\ + %{msa:-D__i960SA__ -D__i960_SA__}\ + %{msb:-D__i960SB__ -D__i960_SB__}\ + %{msc:-D__i960SC__ -D__i960_SC__}\ + %{mmc:-D__i960MC__ -D__i960_MC__}\ + %{mca:-D__i960CA__ -D__i960_CA__}\ + %{mcb:-D__i960CB__ -D__i960_CB__}\ + %{mcc:-D__i960CC__ -D__i960_CC__}\ + %{mcf:-D__i960CF__ -D__i960_CF__}\ + %{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\ + %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}}}}" + + /* -mic* options make characters signed by default. */ + #define SIGNED_CHAR_SPEC \ + (DEFAULT_SIGNED_CHAR ? "%{funsigned-char:-D__CHAR_UNSIGNED__}" \ + : "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}") + + /* Specs for the compiler, to handle processor variations. */ + #define CC1_SPEC \ + "%{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\ + %{!mcc:%{!mcf:-mkb}}}}}}}}}}}\ + %{mbout:%{g*:-gstabs}}\ + %{mcoff:%{g*:-gcoff}}\ + %{!mbout:%{!mcoff:%{g*:-gstabs}}}" + + /* Specs for the assembler, to handle processor variations. + For compatibility with Intel's gnu960 tool chain, pass -A options to + the assembler. */ + #define ASM_SPEC \ + "%{mka:-AKA}%{mkb:-AKB}%{mkc:-AKC}%{msa:-ASA}%{msb:-ASB}\ + %{msc:-ASC}%{mmc:-AMC}%{mca:-ACA}%{mcb:-ACB}%{mcc:-ACC}%{mcf:-ACF}\ + %{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\ + %{!mcc:%{!mcf:-AKB}}}}}}}}}}}" + + /* Specs for the linker, to handle processor variations. + For compatibility with Intel's gnu960 tool chain, pass -F and -A options + to the linker. */ + #define LINK_SPEC \ + "%{mka:-AKA}%{mkb:-AKB}%{mkc:-AKC}%{msa:-ASA}%{msb:-ASB}\ + %{msc:-ASC}%{mmc:-AMC}%{mca:-ACA}%{mcb:-ACB}%{mcc:-ACC}%{mcf:-ACF}\ + %{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\ + %{!mcc:%{!mcf:-AKB}}}}}}}}}}}\ + %{mbout:-Fbout}%{mcoff:-Fcoff}" + + /* Specs for the libraries to link with, to handle processor variations. + Compatible with Intel's gnu960 tool chain. */ + #define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\ + %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}" + + /* These compiler options take an argument. */ + #define WORD_SWITCH_TAKES_ARG(STR) \ + (!strcmp (STR, "Tdata") || !strcmp (STR, "include") \ + || !strcmp (STR, "imacros") || !strcmp (STR, "Ttext")) + + /* Omit frame pointer at -O2. Inline functions at -O3. */ + #define OPTIMIZATION_OPTIONS(LEVEL) \ + { \ + if ((LEVEL) >= 2) \ + { \ + flag_omit_frame_pointer = 1; \ + target_flags |= TARGET_FLAG_LEAFPROC; \ + target_flags |= TARGET_FLAG_TAILCALL; \ + } \ + if ((LEVEL) >= 3) \ + flag_inline_functions = 1; \ + } + + /* Print subsidiary information on the compiler version in use. */ + #define TARGET_VERSION fprintf (stderr," (intel 80960)"); + + /* Generate DBX debugging information. */ + #define DBX_DEBUGGING_INFO + + /* Generate SDB style debugging information. */ + #define SDB_DEBUGGING_INFO + + /* Generate DBX_DEBUGGING_INFO by default. */ + #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + + /* Redefine this to print in hex like iC960. */ + #define PUT_SDB_TYPE(A) fprintf (asm_out_file, "\t.type\t0x%x;", A) + + /* Run-time compilation parameters selecting different hardware subsets. */ + + /* 960 architecture with floating-point. */ + #define TARGET_FLAG_NUMERICS 0x01 + #define TARGET_NUMERICS (target_flags & TARGET_FLAG_NUMERICS) + + /* 960 architecture with memory management. */ + /* ??? Not used currently. */ + #define TARGET_FLAG_PROTECTED 0x02 + #define TARGET_PROTECTED (target_flags & TARGET_FLAG_PROTECTED) + + /* The following three are mainly used to provide a little sanity checking + against the -mARCH flags given. */ + + /* Nonzero if we should generate code for the KA and similar processors. + No FPU, no microcode instructions. */ + #define TARGET_FLAG_K_SERIES 0x04 + #define TARGET_K_SERIES (target_flags & TARGET_FLAG_K_SERIES) + + /* Nonzero if we should generate code for the MC processor. + Not really different from KB for our purposes. */ + #define TARGET_FLAG_MC 0x08 + #define TARGET_MC (target_flags & TARGET_FLAG_MC) + + /* Nonzero if we should generate code for the CA processor. + Enables different optimization strategies. */ + #define TARGET_FLAG_C_SERIES 0x10 + #define TARGET_C_SERIES (target_flags & TARGET_FLAG_C_SERIES) + + /* Nonzero if we should generate leaf-procedures when we find them. + You may not want to do this because leaf-proc entries are + slower when not entered via BAL - this would be true when + a linker not supporting the optimization is used. */ + #define TARGET_FLAG_LEAFPROC 0x20 + #define TARGET_LEAFPROC (target_flags & TARGET_FLAG_LEAFPROC) + + /* Nonzero if we should perform tail-call optimizations when we find them. + You may not want to do this because the detection of cases where + this is not valid is not totally complete. */ + #define TARGET_FLAG_TAILCALL 0x40 + #define TARGET_TAILCALL (target_flags & TARGET_FLAG_TAILCALL) + + /* Nonzero if use of a complex addressing mode is a win on this implementation. + Complex addressing modes are probably not worthwhile on the K-series, + but they definitely are on the C-series. */ + #define TARGET_FLAG_COMPLEX_ADDR 0x80 + #define TARGET_COMPLEX_ADDR (target_flags & TARGET_FLAG_COMPLEX_ADDR) + + /* Align code to 8 byte boundaries for faster fetching. */ + #define TARGET_FLAG_CODE_ALIGN 0x100 + #define TARGET_CODE_ALIGN (target_flags & TARGET_FLAG_CODE_ALIGN) + + /* Append branch prediction suffixes to branch opcodes. */ + /* ??? Not used currently. */ + #define TARGET_FLAG_BRANCH_PREDICT 0x200 + #define TARGET_BRANCH_PREDICT (target_flags & TARGET_FLAG_BRANCH_PREDICT) + + /* Forces prototype and return promotions. */ + /* ??? This does not work. */ + #define TARGET_FLAG_CLEAN_LINKAGE 0x400 + #define TARGET_CLEAN_LINKAGE (target_flags & TARGET_FLAG_CLEAN_LINKAGE) + + /* For compatibility with iC960 v3.0. */ + #define TARGET_FLAG_IC_COMPAT3_0 0x800 + #define TARGET_IC_COMPAT3_0 (target_flags & TARGET_FLAG_IC_COMPAT3_0) + + /* For compatibility with iC960 v2.0. */ + #define TARGET_FLAG_IC_COMPAT2_0 0x1000 + #define TARGET_IC_COMPAT2_0 (target_flags & TARGET_FLAG_IC_COMPAT2_0) + + /* If no unaligned accesses are to be permitted. */ + #define TARGET_FLAG_STRICT_ALIGN 0x2000 + #define TARGET_STRICT_ALIGN (target_flags & TARGET_FLAG_STRICT_ALIGN) + + /* For compatibility with iC960 assembler. */ + #define TARGET_FLAG_ASM_COMPAT 0x4000 + #define TARGET_ASM_COMPAT (target_flags & TARGET_FLAG_ASM_COMPAT) + + /* For compatibility with the gcc960 v1.2 compiler. Use the old structure + alignement rules. Also, turns on STRICT_ALIGNMENT. */ + #define TARGET_FLAG_OLD_ALIGN 0x8000 + #define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN) + + extern int target_flags; + + /* Macro to define tables used to set the flags. + This is a list in braces of pairs in braces, + each pair being { "NAME", VALUE } + where VALUE is the bits to set or minus the bits to clear. + An empty string NAME is used to identify the default VALUE. */ + + /* ??? Not all ten of these architecture variations actually exist, but I + am not sure which are real and which aren't. */ + + #define TARGET_SWITCHES \ + { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\ + {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \ + TARGET_FLAG_COMPLEX_ADDR)},\ + {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ + TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\ + {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\ + {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \ + TARGET_FLAG_COMPLEX_ADDR)},\ + {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ + TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\ + {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ + TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\ + {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\ + TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\ + {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES|\ + TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN)},\ + {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ + TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\ + TARGET_FLAG_CODE_ALIGN)}, \ + {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\ + TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\ + {"numerics", (TARGET_FLAG_NUMERICS)}, \ + {"soft-float", -(TARGET_FLAG_NUMERICS)}, \ + {"leaf-procedures", TARGET_FLAG_LEAFPROC}, \ + {"no-leaf-procedures",-(TARGET_FLAG_LEAFPROC)}, \ + {"tail-call",TARGET_FLAG_TAILCALL}, \ + {"no-tail-call",-(TARGET_FLAG_TAILCALL)}, \ + {"complex-addr",TARGET_FLAG_COMPLEX_ADDR}, \ + {"no-complex-addr",-(TARGET_FLAG_COMPLEX_ADDR)}, \ + {"code-align",TARGET_FLAG_CODE_ALIGN}, \ + {"no-code-align",-(TARGET_FLAG_CODE_ALIGN)}, \ + {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE)}, \ + {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE)}, \ + {"ic-compat", TARGET_FLAG_IC_COMPAT2_0}, \ + {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0}, \ + {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0}, \ + {"asm-compat",TARGET_FLAG_ASM_COMPAT}, \ + {"intel-asm",TARGET_FLAG_ASM_COMPAT}, \ + {"strict-align", TARGET_FLAG_STRICT_ALIGN}, \ + {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN)}, \ + {"old-align", TARGET_FLAG_OLD_ALIGN}, \ + {"no-old-align", -(TARGET_FLAG_OLD_ALIGN)}, \ + { "", TARGET_DEFAULT}} + + /* Override conflicting target switch options. + Doesn't actually detect if more than one -mARCH option is given, but + does handle the case of two blatantly conflicting -mARCH options. */ + #define OVERRIDE_OPTIONS \ + { \ + if (TARGET_K_SERIES && TARGET_C_SERIES) \ + { \ + warning ("conflicting architectures defined - using C series", 0); \ + target_flags &= ~TARGET_FLAG_K_SERIES; \ + } \ + if (TARGET_K_SERIES && TARGET_MC) \ + { \ + warning ("conflicting architectures defined - using K series", 0); \ + target_flags &= ~TARGET_FLAG_MC; \ + } \ + if (TARGET_C_SERIES && TARGET_MC) \ + { \ + warning ("conflicting architectures defined - using C series", 0);\ + target_flags &= ~TARGET_FLAG_MC; \ + } \ + if (TARGET_IC_COMPAT3_0) \ + { \ + flag_short_enums = 1; \ + flag_signed_char = 1; \ + target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \ + if (TARGET_IC_COMPAT2_0) \ + { \ + warning ("iC2.0 and iC3.0 are incompatible - using iC3.0", 0); \ + target_flags &= ~TARGET_FLAG_IC_COMPAT2_0; \ + } \ + } \ + if (TARGET_IC_COMPAT2_0) \ + { \ + flag_signed_char = 1; \ + target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \ + } \ + /* ??? Function inlining is not supported, because the i960 \ + calling convention requires the caller to manage the arg \ + pointer in a wierd fashion. This is ordinarily done by \ + expand_call, but this is never called when inlining \ + functions, and no replacement for it exists. */ \ + flag_no_inline = 1; \ + i960_initialize (); \ + } + + /* Don't enable anything by default. The user is expected to supply a -mARCH + option. If none is given, then -mkb is added by CC1_SPEC. */ + #define TARGET_DEFAULT 0 + + /* Target machine storage layout. */ + + /* Define this if most significant bit is lowest numbered + in instructions that operate on numbered bit-fields. */ + #define BITS_BIG_ENDIAN 0 + + /* Define this if most significant byte of a word is the lowest numbered. + The i960 case be either big endian or little endian. We only support + little endian, which is the most common. */ + #define BYTES_BIG_ENDIAN 0 + + /* Define this if most significant word of a multiword number is lowest + numbered. */ + #define WORDS_BIG_ENDIAN 0 + + /* Number of bits in an addressible storage unit. */ + #define BITS_PER_UNIT 8 + + /* Bitfields cannot cross word boundaries. */ + #define BITFIELD_NBYTES_LIMITED 1 + + /* Width in bits of a "word", which is the contents of a machine register. + Note that this is not necessarily the width of data type `int'; + if using 16-bit ints on a 68000, this would still be 32. + But on a machine with 16-bit registers, this would be 16. */ + #define BITS_PER_WORD 32 + + /* Width of a word, in units (bytes). */ + #define UNITS_PER_WORD 4 + + /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ + #define POINTER_SIZE 32 + + /* Width in bits of a long double. Identical to double for now. */ + #define LONG_DOUBLE_TYPE_SIZE 64 + + /* Allocation boundary (in *bits*) for storing pointers in memory. */ + #define POINTER_BOUNDARY 32 + + /* Allocation boundary (in *bits*) for storing arguments in argument list. */ + #define PARM_BOUNDARY 32 + + /* Boundary (in *bits*) on which stack pointer should be aligned. */ + #define STACK_BOUNDARY 128 + + /* Allocation boundary (in *bits*) for the code of a function. */ + #define FUNCTION_BOUNDARY 128 + + /* Alignment of field after `int : 0' in a structure. */ + #define EMPTY_FIELD_BOUNDARY 32 + + /* This makes zero-length anonymous fields lay the next field + at a word boundary. It also makes the whole struct have + at least word alignment if there are any bitfields at all. */ + #define PCC_BITFIELD_TYPE_MATTERS 1 + + /* Every structure's size must be a multiple of this. */ + #define STRUCTURE_SIZE_BOUNDARY 8 + + /* No data type wants to be aligned rounder than this. + Extended precision floats gets 4-word alignment. */ + #define BIGGEST_ALIGNMENT 128 + + /* Define this if move instructions will actually fail to work + when given unaligned data. + 80960 will work even with unaligned data, but it is slow. */ + #define STRICT_ALIGNMENT TARGET_OLD_ALIGN + + /* Specify alignment for string literals (which might be higher than the + base type's minimnal alignment requirement. This allows strings to be + aligned on word boundaries, and optimizes calls to the str* and mem* + library functions. */ + #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ + (i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \ + ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \ + : (ALIGN)) + + /* Macros to determine size of aggregates (structures and unions + in C). Normally, these may be defined to simply return the maximum + alignment and simple rounded-up size, but on some machines (like + the i960), the total size of a structure is based on a non-trivial + rounding method. */ + + #define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \ + ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \ + ? i960_round_align ((SPECIFIED), TYPE_SIZE (TYPE)) \ + : MAX ((COMPUTED), (SPECIFIED))) + + #define ROUND_TYPE_SIZE(TYPE, SIZE, ALIGN) \ + ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \ + ? (tree) i960_round_size (SIZE) \ + : round_up ((SIZE), (ALIGN))) + + /* Standard register usage. */ + + /* Number of actual hardware registers. + The hardware registers are assigned numbers for the compiler + from 0 to just below FIRST_PSEUDO_REGISTER. + All registers that the compiler knows about must be given numbers, + even those that are not normally considered general registers. + + Registers 0-15 are the global registers (g0-g15). + Registers 16-31 are the local registers (r0-r15). + Register 32-35 are the fp registers (fp0-fp3). + Register 36 is the condition code register. + Register 37 is unused. */ + + #define FIRST_PSEUDO_REGISTER 38 + + /* 1 for registers that have pervasive standard uses and are not available + for the register allocator. On 80960, this includes the frame pointer + (g15), the previous FP (r0), the stack pointer (r1), the return + instruction pointer (r2), and the argument pointer (g14). */ + #define FIXED_REGISTERS \ + {0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 1, 1, \ + 1, 1, 1, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 1, 1} + + /* 1 for registers not available across function calls. + These must include the FIXED_REGISTERS and also any + registers that can be used without being saved. + The latter must include the registers where values are returned + and the register where structure-value addresses are passed. + Aside from that, you can include as many other registers as you like. */ + + /* On the 80960, note that: + g0..g3 are used for return values, + g0..g7 may always be used for parameters, + g8..g11 may be used for parameters, but are preserved if they aren't, + g12 is always preserved, but otherwise unused, + g13 is the struct return ptr if used, or temp, but may be trashed, + g14 is the leaf return ptr or the arg block ptr otherwise zero, + must be reset to zero before returning if it was used, + g15 is the frame pointer, + r0 is the previous FP, + r1 is the stack pointer, + r2 is the return instruction pointer, + r3-r15 are always available, + fp0..fp3 are never available. */ + #define CALL_USED_REGISTERS \ + {1, 1, 1, 1, 1, 1, 1, 1, \ + 0, 0, 0, 0, 0, 1, 1, 1, \ + 1, 1, 1, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 1, 1, 1, 1, 1} + + /* If no fp unit, make all of the fp registers fixed so that they can't + be used. */ + #define CONDITIONAL_REGISTER_USAGE \ + if (! TARGET_NUMERICS) { \ + fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\ + } \ + + /* Return number of consecutive hard regs needed starting at reg REGNO + to hold something of mode MODE. + This is ordinarily the length in words of a value of mode MODE + but can be less for certain modes in special long registers. + + On 80960, ordinary registers hold 32 bits worth, but can be ganged + together to hold double or extended precision floating point numbers, + and the floating point registers hold any size floating point number */ + #define HARD_REGNO_NREGS(REGNO, MODE) \ + ((REGNO) < 32 \ + ? (((MODE) == VOIDmode) \ + ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \ + : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0) + + /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. + On 80960, the cpu registers can hold any mode but the float registers + can only hold SFmode, DFmode, or TFmode. */ + extern unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER]; + #define HARD_REGNO_MODE_OK(REGNO, MODE) \ + ((hard_regno_mode_ok[REGNO] & (1 << (int) (MODE))) != 0) + + /* Value is 1 if it is a good idea to tie two pseudo registers + when one has mode MODE1 and one has mode MODE2. + If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, + for any hard reg, then this must be 0 for correct output. */ + + #define MODES_TIEABLE_P(MODE1, MODE2) \ + ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) + + /* Specify the registers used for certain standard purposes. + The values of these macros are register numbers. */ + + /* 80960 pc isn't overloaded on a register that the compiler knows about. */ + /* #define PC_REGNUM */ + + /* Register to use for pushing function arguments. */ + #define STACK_POINTER_REGNUM 17 + + /* Actual top-of-stack address is same as + the contents of the stack pointer register. */ + #define STACK_POINTER_OFFSET (-current_function_outgoing_args_size) + + /* Base register for access to local variables of the function. */ + #define FRAME_POINTER_REGNUM 15 + + /* Value should be nonzero if functions must have frame pointers. + Zero means the frame pointer need not be set up (and parms + may be accessed via the stack pointer) in functions that seem suitable. + This is computed in `reload', in reload1.c. */ + #define FRAME_POINTER_REQUIRED (! leaf_function_p ()) + + /* C statement to store the difference between the frame pointer + and the stack pointer values immediately after the function prologue. */ + + #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ + do { (VAR) = compute_frame_size (get_frame_size ()); } while (0) + + /* Base register for access to arguments of the function. */ + #define ARG_POINTER_REGNUM 14 + + /* Register in which static-chain is passed to a function. + On i960, we use r3. */ + #define STATIC_CHAIN_REGNUM 19 + + /* Functions which return large structures get the address + to place the wanted value at in g13. */ + + #define STRUCT_VALUE_REGNUM 13 + + /* The order in which to allocate registers. */ + + #define REG_ALLOC_ORDER \ + { 4, 5, 6, 7, 0, 1, 2, 3, 13, /* g4, g5, g6, g7, g0, g1, g2, g3, g13 */ \ + 20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11 */ \ + 28, 29, 30, 31, 19, 8, 9, 10, /* r12, r13, r14, r15, r3, g8, g9, g10 */ \ + 11, 12, /* g11, g12 */ \ + 32, 33, 34, 35, /* fp0, fp1, fp2, fp3 */ \ + /* We can't actually allocate these. */ \ + 16, 17, 18, 14, 15, 36, 37} /* r0, r1, r2, g14, g15, cc */ + + /* Define the classes of registers for register constraints in the + machine description. Also define ranges of constants. + + One of the classes must always be named ALL_REGS and include all hard regs. + If there is more than one class, another class must be named NO_REGS + and contain no registers. + + The name GENERAL_REGS must be the name of a class (or an alias for + another name such as ALL_REGS). This is the class of registers + that is allowed by "g" or "r" in a register constraint. + Also, registers outside this class are allocated only when + instructions express preferences for them. + + The classes must be numbered in nondecreasing order; that is, + a larger-numbered class must never be contained completely + in a smaller-numbered class. + + For any two classes, it is very desirable that there be another + class that represents their union. */ + + /* The 80960 has four kinds of registers, global, local, floating point, + and condition code. The cc register is never allocated, so no class + needs to be defined for it. */ + + enum reg_class { NO_REGS, GLOBAL_REGS, LOCAL_REGS, LOCAL_OR_GLOBAL_REGS, + FP_REGS, ALL_REGS, LIM_REG_CLASSES }; + + /* 'r' includes floating point registers if TARGET_NUMERICS. 'd' never + does. */ + #define GENERAL_REGS ((TARGET_NUMERICS) ? ALL_REGS : LOCAL_OR_GLOBAL_REGS) + + #define N_REG_CLASSES (int) LIM_REG_CLASSES + + /* Give names of register classes as strings for dump file. */ + + #define REG_CLASS_NAMES \ + { "NO_REGS", "GLOBAL_REGS", "LOCAL_REGS", "LOCAL_OR_GLOBAL_REGS", \ + "FP_REGS", "ALL_REGS" } + + /* Define which registers fit in which classes. + This is an initializer for a vector of HARD_REG_SET + of length N_REG_CLASSES. */ + + #define REG_CLASS_CONTENTS \ + { {0, 0}, {0x0ffff, 0}, {0xffff0000, 0}, {-1,0}, {0, -1}, {-1,-1}} + + /* The same information, inverted: + Return the class number of the smallest class containing + reg number REGNO. This could be a conditional expression + or could index an array. */ + + #define REGNO_REG_CLASS(REGNO) \ + ((REGNO) < 16 ? GLOBAL_REGS \ + : (REGNO) < 32 ? LOCAL_REGS \ + : (REGNO) < 36 ? FP_REGS \ + : NO_REGS) + + /* The class value for index registers, and the one for base regs. + There is currently no difference between base and index registers on the + i960, but this distinction may one day be useful. */ + #define INDEX_REG_CLASS LOCAL_OR_GLOBAL_REGS + #define BASE_REG_CLASS LOCAL_OR_GLOBAL_REGS + + /* Get reg_class from a letter such as appears in the machine description. + 'f' is a floating point register (fp0..fp3) + 'l' is a local register (r0-r15) + 'b' is a global register (g0-g15) + 'd' is any local or global register + 'r' or 'g' are pre-defined to the class GENERAL_REGS. */ + /* 'l' and 'b' are probably never used. Note that 'd' and 'r' are *not* + the same thing, since 'r' may include the fp registers. */ + #define REG_CLASS_FROM_LETTER(C) \ + (((C) == 'f') && (TARGET_NUMERICS) ? FP_REGS : ((C) == 'l' ? LOCAL_REGS : \ + (C) == 'b' ? GLOBAL_REGS : ((C) == 'd' ? LOCAL_OR_GLOBAL_REGS : NO_REGS))) + + /* The letters I, J, K, L and M in a register constraint string + can be used to stand for particular ranges of immediate operands. + This macro defines what the ranges are. + C is the letter, and VALUE is a constant value. + Return 1 if VALUE is in the range specified by C. + + For 80960: + 'I' is used for literal values 0..31 + 'J' means literal 0 + 'K' means 0..-31. */ + + #define CONST_OK_FOR_LETTER_P(VALUE, C) \ + ((C) == 'I' ? (((unsigned) (VALUE)) <= 31) \ + : (C) == 'J' ? ((VALUE) == 0) \ + : (C) == 'K' ? ((VALUE) > -32 && (VALUE) <= 0) \ + : 0) + + /* Similar, but for floating constants, and defining letters G and H. + Here VALUE is the CONST_DOUBLE rtx itself. + For the 80960, G is 0.0 and H is 1.0. */ + + #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ + ((TARGET_NUMERICS) && \ + (((C) == 'G' && ((VALUE) == CONST0_RTX (DFmode) \ + || (VALUE) == CONST0_RTX (SFmode))) \ + || ((C) == 'H' && ((VALUE) == CONST1_RTX (DFmode) \ + || (VALUE) == CONST1_RTX (SFmode))))) + + /* Given an rtx X being reloaded into a reg required to be + in class CLASS, return the class of reg to actually use. + In general this is just CLASS; but on some machines + in some cases it is preferable to use a more restrictive class. */ + + /* On 960, can't load constant into floating-point reg except + 0.0 or 1.0. + + Any hard reg is ok as a src operand of a reload insn. */ + + #define PREFERRED_RELOAD_CLASS(X,CLASS) \ + (GET_CODE (X) == REG && REGNO (X) < FIRST_PSEUDO_REGISTER \ + ? (CLASS) \ + : ((CLASS) == FP_REGS && CONSTANT_P (X) \ + && (X) != CONST0_RTX (DFmode) && (X) != CONST1_RTX (DFmode)\ + && (X) != CONST0_RTX (SFmode) && (X) != CONST1_RTX (SFmode)\ + ? NO_REGS \ + : (CLASS) == ALL_REGS ? LOCAL_OR_GLOBAL_REGS : (CLASS))) + + #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ + secondary_reload_class (CLASS, MODE, IN) + + /* Return the maximum number of consecutive registers + needed to represent mode MODE in a register of class CLASS. */ + /* On 80960, this is the size of MODE in words, + except in the FP regs, where a single reg is always enough. */ + #define CLASS_MAX_NREGS(CLASS, MODE) \ + ((CLASS) == FP_REGS ? 1 : HARD_REGNO_NREGS (0, (MODE))) + + /* Stack layout; function entry, exit and calling. */ + + /* Define this if pushing a word on the stack + makes the stack pointer a smaller address. */ + /* #define STACK_GROWS_DOWNWARD */ + + /* Define this if the nominal address of the stack frame + is at the high-address end of the local variables; + that is, each additional local variable allocated + goes at a more negative offset in the frame. */ + /* #define FRAME_GROWS_DOWNWARD */ + + /* Offset within stack frame to start allocating local variables at. + If FRAME_GROWS_DOWNWARD, this is the offset to the END of the + first local allocated. Otherwise, it is the offset to the BEGINNING + of the first local allocated. + + The i960 has a 64 byte register save area, plus possibly some extra + bytes allocated for varargs functions. */ + #define STARTING_FRAME_OFFSET 64 + + /* If we generate an insn to push BYTES bytes, + this says how many the stack pointer really advances by. + On 80960, don't define this because there are no push insns. */ + /* #define PUSH_ROUNDING(BYTES) BYTES */ + + /* Offset of first parameter from the argument pointer register value. */ + #define FIRST_PARM_OFFSET(FNDECL) 0 + + /* When a parameter is passed in a register, no stack space is + allocated for it. However, when args are passed in the + stack, space is allocated for every register parameter. */ + #define MAYBE_REG_PARM_STACK_SPACE 48 + #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) \ + i960_final_reg_parm_stack_space (CONST_SIZE, VAR_SIZE); + #define REG_PARM_STACK_SPACE(DECL) i960_reg_parm_stack_space (DECL) + #define OUTGOING_REG_PARM_STACK_SPACE + + /* Keep the stack pointer constant throughout the function. */ + #define ACCUMULATE_OUTGOING_ARGS + + /* Value is 1 if returning from a function call automatically + pops the arguments described by the number-of-args field in the call. + FUNTYPE is the data type of the function (as a tree), + or for a library call it is an identifier node for the subroutine name. */ + + #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0 + + /* Define how to find the value returned by a library function + assuming the value has mode MODE. */ + + #define LIBCALL_VALUE(MODE) gen_rtx ((REG), (MODE), 0) + + /* 1 if N is a possible register number for a function value + as seen by the caller. + On 80960, returns are in g0..g3 */ + + #define FUNCTION_VALUE_REGNO_P(N) ((N) < 4) + + /* 1 if N is a possible register number for function argument passing. + On 80960, parameters are passed in g0..g11 */ + + #define FUNCTION_ARG_REGNO_P(N) ((N) < 12) + + /* Perform any needed actions needed for a function that is receiving a + variable number of arguments. + + CUM is as above. + + MODE and TYPE are the mode and type of the current parameter. + + PRETEND_SIZE is a variable that should be set to the amount of stack + that must be pushed by the prolog to pretend that our caller pushed + it. + + Normally, this macro will push all remaining incoming registers on the + stack and set PRETEND_SIZE to the length of the registers pushed. */ + + #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ + i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL) + + /* Define a data type for recording info about an argument list + during the scan of that argument list. This data type should + hold all necessary information about the function itself + and about the args processed so far, enough to enable macros + such as FUNCTION_ARG to determine where the next arg should go. + + On 80960, this is two integers, which count the number of register + parameters and the number of stack parameters seen so far. */ + + struct cum_args { int ca_nregparms; int ca_nstackparms; }; + + #define CUMULATIVE_ARGS struct cum_args + + /* Define the number of registers that can hold parameters. + This macro is used only in macro definitions below and/or i960.c. */ + #define NPARM_REGS 12 + + /* Define how to round to the next parameter boundary. + This macro is used only in macro definitions below and/or i960.c. */ + #define ROUND(X, MULTIPLE_OF) \ + ((((X) + (MULTIPLE_OF) - 1) / (MULTIPLE_OF)) * MULTIPLE_OF) + + /* Initialize a variable CUM of type CUMULATIVE_ARGS + for a call to a function whose data type is FNTYPE. + For a library call, FNTYPE is 0. + + On 80960, the offset always starts at 0; the first parm reg is g0. */ + + #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ + ((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0) + + /* Update the data in CUM to advance over an argument + of mode MODE and data type TYPE. + CUM should be advanced to align with the data type accessed and + also the size of that data type in # of regs. + (TYPE is null for libcalls where that information may not be available.) */ + + #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ + i960_function_arg_advance(&CUM, MODE, TYPE, NAMED) + + /* Indicate the alignment boundary for an argument of the specified mode and + type. */ + #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ + (((TYPE) != 0) \ + ? ((TYPE_ALIGN (TYPE) <= PARM_BOUNDARY) \ + ? PARM_BOUNDARY \ + : TYPE_ALIGN (TYPE)) \ + : ((GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY) \ + ? PARM_BOUNDARY \ + : GET_MODE_ALIGNMENT (MODE))) + + /* Determine where to put an argument to a function. + Value is zero to push the argument on the stack, + or a hard register in which to store the argument. + + MODE is the argument's machine mode. + TYPE is the data type of the argument (as a tree). + This is null for libcalls where that information may + not be available. + CUM is a variable of type CUMULATIVE_ARGS which gives info about + the preceding args and about the function being called. + NAMED is nonzero if this argument is a named parameter + (otherwise it is an extra parameter matching an ellipsis). */ + + extern struct rtx_def *i960_function_arg (); + #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ + i960_function_arg(&CUM, MODE, TYPE, NAMED) + + /* Define how to find the value returned by a function. + VALTYPE is the data type of the value (as a tree). + If the precise function being called is known, FUNC is its FUNCTION_DECL; + otherwise, FUNC is 0. */ + + extern struct rtx_def *i960_function_value (); + #define FUNCTION_VALUE(TYPE, FUNC) i960_function_value (TYPE) + + /* Force objects larger than 16 bytes to be returned in memory, since we + only have 4 registers available for return values. */ + + #define RETURN_IN_MEMORY(TYPE) (int_size_in_bytes (TYPE) > 16) + + /* For an arg passed partly in registers and partly in memory, + this is the number of registers used. + This never happens on 80960. */ + + #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 + + /* Output the label for a function definition. + This handles leaf functions and a few other things for the i960. */ + + #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ + i960_function_name_declare (FILE, NAME, DECL) + + /* This macro generates the assembly code for function entry. + FILE is a stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to allocate. + Refer to the array `regs_ever_live' to determine which registers + to save; `regs_ever_live[I]' is nonzero if register number I + is ever used in the function. This macro is responsible for + knowing which registers should not be saved even if used. */ + + #define FUNCTION_PROLOGUE(FILE, SIZE) i960_function_prologue ((FILE), (SIZE)) + + /* Output assembler code to FILE to increment profiler label # LABELNO + for profiling a function entry. */ + + #define FUNCTION_PROFILER(FILE, LABELNO) \ + fprintf (FILE, "\tlda LP%d,g0\n\tbal mcount\n", (LABELNO)) + + /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, + the stack pointer does not matter. The value is tested only in + functions that have frame pointers. + No definition is equivalent to always zero. */ + + #define EXIT_IGNORE_STACK 1 + + /* This macro generates the assembly code for function exit, + on machines that need it. If FUNCTION_EPILOGUE is not defined + then individual return instructions are generated for each + return statement. Args are same as for FUNCTION_PROLOGUE. + + The function epilogue should not depend on the current stack pointer! + It should use the frame pointer only. This is mandatory because + of alloca; we also take advantage of it to omit stack adjustments + before returning. */ + + #define FUNCTION_EPILOGUE(FILE, SIZE) i960_function_epilogue (FILE, SIZE) + + /* Addressing modes, and classification of registers for them. */ + + /* #define HAVE_POST_INCREMENT */ + /* #define HAVE_POST_DECREMENT */ + + /* #define HAVE_PRE_DECREMENT */ + /* #define HAVE_PRE_INCREMENT */ + + /* Macros to check register numbers against specific register classes. */ + + /* These assume that REGNO is a hard or pseudo reg number. + They give nonzero only if REGNO is a hard reg of the suitable class + or a pseudo reg currently allocated to a suitable hard reg. + Since they use reg_renumber, they are safe only once reg_renumber + has been allocated, which happens in local-alloc.c. */ + + #define REGNO_OK_FOR_INDEX_P(REGNO) \ + ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) + #define REGNO_OK_FOR_BASE_P(REGNO) \ + ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) + #define REGNO_OK_FOR_FP_P(REGNO) \ + ((REGNO) < 36 || (unsigned) reg_renumber[REGNO] < 36) + + /* Now macros that check whether X is a register and also, + strictly, whether it is in a specified class. + + These macros are specific to the 960, and may be used only + in code for printing assembler insns and in conditions for + define_optimization. */ + + /* 1 if X is an fp register. */ + + #define FP_REG_P(X) (REGNO (X) >= 32 && REGNO (X) < 36) + + /* Maximum number of registers that can appear in a valid memory address. */ + #define MAX_REGS_PER_ADDRESS 2 + + #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X) + + /* LEGITIMATE_CONSTANT_P is nonzero if the constant value X + is a legitimate general operand. + It is given that X satisfies CONSTANT_P. + + Anything but a CONST_DOUBLE can be made to work, excepting 0.0 and 1.0. */ + + #define LEGITIMATE_CONSTANT_P(X) \ + ((GET_CODE (X) != CONST_DOUBLE) || fp_literal ((X), VOIDmode)) + + /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx + and check its validity for a certain class. + We have two alternate definitions for each of them. + The usual definition accepts all pseudo regs; the other rejects + them unless they have been allocated suitable hard regs. + The symbol REG_OK_STRICT causes the latter definition to be used. + + Most source files want to accept pseudo regs in the hope that + they will get allocated to the class that the insn wants them to be in. + Source files for reload pass need to be strict. + After reload, it makes no difference, since pseudo regs have + been eliminated by then. */ + + #ifndef REG_OK_STRICT + + /* Nonzero if X is a hard reg that can be used as an index + or if it is a pseudo reg. */ + #define REG_OK_FOR_INDEX_P(X) \ + (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER) + /* Nonzero if X is a hard reg that can be used as a base reg + or if it is a pseudo reg. */ + #define REG_OK_FOR_BASE_P(X) \ + (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER) + + #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) + #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X)) + + #else + + /* Nonzero if X is a hard reg that can be used as an index. */ + #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) + /* Nonzero if X is a hard reg that can be used as a base reg. */ + #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) + + #endif + + /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression + that is a valid memory address for an instruction. + The MODE argument is the machine mode for the MEM expression + that wants to use this address. + + On 80960, legitimate addresses are: + base ld (g0),r0 + disp (12 or 32 bit) ld foo,r0 + base + index ld (g0)[g1*1],r0 + base + displ ld 0xf00(g0),r0 + base + index*scale + displ ld 0xf00(g0)[g1*4],r0 + index*scale + base ld (g0)[g1*4],r0 + index*scale + displ ld 0xf00[g1*4],r0 + index*scale ld [g1*4],r0 + index + base + displ ld 0xf00(g0)[g1*1],r0 + + In each case, scale can be 1, 2, 4, 8, or 16. */ + + /* Returns 1 if the scale factor of an index term is valid. */ + #define SCALE_TERM_P(X) \ + (GET_CODE (X) == CONST_INT \ + && (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \ + || INTVAL(X) == 8 || INTVAL (X) == 16)) + + + #ifdef REG_OK_STRICT + #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ + { if (legitimate_address_p (MODE, X, 1)) goto ADDR; } + #else + #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ + { if (legitimate_address_p (MODE, X, 0)) goto ADDR; } + #endif + + /* Try machine-dependent ways of modifying an illegitimate address + to be legitimate. If we find one, return the new, valid address. + This macro is used in only one place: `memory_address' in explow.c. + + OLDX is the address as it was before break_out_memory_refs was called. + In some cases it is useful to look at this to decide what needs to be done. + + MODE and WIN are passed so that this macro can use + GO_IF_LEGITIMATE_ADDRESS. + + It is always safe for this macro to do nothing. It exists to recognize + opportunities to optimize the output. */ + + /* On 80960, convert non-cannonical addresses to canonical form. */ + + extern struct rtx_def *legitimize_address (); + #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ + { rtx orig_x = (X); \ + (X) = legitimize_address (X, OLDX, MODE); \ + if ((X) != orig_x && memory_address_p (MODE, X)) \ + goto WIN; } + + /* Go to LABEL if ADDR (a legitimate address expression) + has an effect that depends on the machine mode it is used for. + On the 960 this is never true. */ + + #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) + + /* Specify the machine mode that this machine uses + for the index in the tablejump instruction. */ + #define CASE_VECTOR_MODE SImode + + /* Define this if the tablejump instruction expects the table + to contain offsets from the address of the table. + Do not define this if the table should contain absolute addresses. */ + /* #define CASE_VECTOR_PC_RELATIVE */ + + /* Specify the tree operation to be used to convert reals to integers. */ + #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR + + /* This is the kind of divide that is easiest to do in the general case. */ + #define EASY_DIV_EXPR TRUNC_DIV_EXPR + + /* Define this as 1 if `char' should by default be signed; else as 0. */ + #define DEFAULT_SIGNED_CHAR 0 + + /* Allow and ignore #sccs directives. */ + #define SCCS_DIRECTIVE + + /* Max number of bytes we can move from memory to memory + in one reasonably fast instruction. */ + #define MOVE_MAX 16 + + /* Define if normal loads of shorter-than-word items from memory clears + the rest of the bigs in the register. */ + #define BYTE_LOADS_ZERO_EXTEND + + /* Nonzero if access to memory by bytes is no faster than for words. + Defining this results in worse code on the i960. */ + + #define SLOW_BYTE_ACCESS 0 + + /* We assume that the store-condition-codes instructions store 0 for false + and some other value for true. This is the value stored for true. */ + + #define STORE_FLAG_VALUE 1 + + /* Define if shifts truncate the shift count + which implies one can omit a sign-extension or zero-extension + of a shift count. */ + #define SHIFT_COUNT_TRUNCATED + + /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits + is done just by pretending it is already truncated. */ + #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 + + /* Specify the machine mode that pointers have. + After generation of rtl, the compiler makes no further distinction + between pointers and any other objects of this machine mode. */ + #define Pmode SImode + + /* Specify the widest mode that BLKmode objects can be promoted to */ + #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) + + /* These global variables are used to pass information between + cc setter and cc user at insn emit time. */ + + extern struct rtx_def *i960_compare_op0, *i960_compare_op1; + + /* Define the function that build the compare insn for scc and bcc. */ + + extern struct rtx_def *gen_compare_reg (); + + /* Add any extra modes needed to represent the condition code. + + Also, signed and unsigned comparisons are distinguished, as + are operations which are compatible with chkbit insns. */ + #define EXTRA_CC_MODES CC_UNSmode, CC_CHKmode + + /* Define the names for the modes specified above. */ + #define EXTRA_CC_NAMES "CC_UNS", "CC_CHK" + + /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, + return the mode to be used for the comparison. For floating-point, CCFPmode + should be used. CC_NOOVmode should be used when the first operand is a + PLUS, MINUS, or NEG. CCmode should be used when no special processing is + needed. */ + #define SELECT_CC_MODE(OP,X) select_cc_mode (OP, X) + + /* A function address in a call instruction is a byte address + (for indexing purposes) so give the MEM rtx a byte's mode. */ + #define FUNCTION_MODE SImode + + /* Define this if addresses of constant functions + shouldn't be put through pseudo regs where they can be cse'd. + Desirable on machines where ordinary constants are expensive + but a CALL with constant address is cheap. */ + #define NO_FUNCTION_CSE + + /* Use memcpy, etc. instead of bcopy. */ + + #ifndef WIND_RIVER + #define TARGET_MEM_FUNCTIONS 1 + #endif + + /* Compute the cost of computing a constant rtl expression RTX + whose rtx-code is CODE. The body of this macro is a portion + of a switch statement. If the code is computed here, + return it with a return statement. Otherwise, break from the switch. */ + + /* Constants that can be (non-ldconst) insn operands are cost 0. Constants + that can be non-ldconst operands in rare cases are cost 1. Other constants + have higher costs. */ + + #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ + case CONST_INT: \ + if ((INTVAL (RTX) >= 0 && INTVAL (RTX) < 32) \ + || power2_operand (RTX, VOIDmode)) \ + return 0; \ + else if (INTVAL (RTX) >= -31 && INTVAL (RTX) < 0) \ + return 1; \ + case CONST: \ + case LABEL_REF: \ + case SYMBOL_REF: \ + return (TARGET_FLAG_C_SERIES ? 6 : 8); \ + case CONST_DOUBLE: \ + if ((RTX) == CONST0_RTX (DFmode) || (RTX) == CONST0_RTX (SFmode) \ + || (RTX) == CONST1_RTX (DFmode) || (RTX) == CONST1_RTX (SFmode))\ + return 1; \ + return 12; + + /* The i960 offers addressing modes which are "as cheap as a register". + See i960.c (or gcc.texinfo) for details. */ + + #define ADDRESS_COST(RTX) \ + (GET_CODE (RTX) == REG ? 1 : i960_address_cost (RTX)) + + /* Control the assembler format that we output. */ + + /* Output at beginning of assembler file. */ + + #define ASM_FILE_START(file) + + /* Output to assembler file text saying following lines + may contain character constants, extra white space, comments, etc. */ + + #define ASM_APP_ON "" + + /* Output to assembler file text saying following lines + no longer contain unusual constructs. */ + + #define ASM_APP_OFF "" + + /* Output before read-only data. */ + + #define TEXT_SECTION_ASM_OP ".text" + + /* Output before writable data. */ + + #define DATA_SECTION_ASM_OP ".data" + + /* How to refer to registers in assembler output. + This sequence is indexed by compiler's hard-register-number (see above). */ + + #define REGISTER_NAMES { \ + "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \ + "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \ + "pfp","sp", "rip", "r3", "r4", "r5", "r6", "r7", \ + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ + "fp0","fp1","fp2", "fp3", "cc", "fake" } + + /* How to renumber registers for dbx and gdb. + In the 960 encoding, g0..g15 are registers 16..31. */ + + #define DBX_REGISTER_NUMBER(REGNO) \ + (((REGNO) < 16) ? (REGNO) + 16 \ + : (((REGNO) > 31) ? (REGNO) : (REGNO) - 16)) + + /* Don't emit dbx records longer than this. This is an arbitrary value. */ + #define DBX_CONTIN_LENGTH 1500 + + /* This is how to output a note to DBX telling it the line number + to which the following sequence of instructions corresponds. */ + + #define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \ + { if (write_symbols == SDB_DEBUG) { \ + fprintf ((FILE), "\t.ln %d\n", \ + (sdb_begin_function_line \ + ? (LINE) - sdb_begin_function_line : 1)); \ + } else if (write_symbols == DBX_DEBUG) { \ + fprintf((FILE),"\t.stabd 68,0,%d\n",(LINE)); \ + } } + + /* This is how to output the definition of a user-level label named NAME, + such as the label on a static function or variable NAME. */ + + #define ASM_OUTPUT_LABEL(FILE,NAME) \ + do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) + + /* This is how to output a command to make the user-level label named NAME + defined for reference from other files. */ + + #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ + { fputs ("\t.globl ", FILE); \ + assemble_name (FILE, NAME); \ + fputs ("\n", FILE); } + + /* This is how to output a reference to a user-level label named NAME. + `assemble_name' uses this. */ + + #define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "_%s", NAME) + + /* This is how to output an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + + #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, "%s%d:\n", PREFIX, NUM) + + /* This is how to store into the string LABEL + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + + #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ + sprintf (LABEL, "*%s%d", PREFIX, NUM) + + /* This is how to output an assembler line defining a `double' constant. */ + + #define ASM_OUTPUT_DOUBLE(FILE,VALUE) i960_output_double(FILE, VALUE) + + /* This is how to output an assembler line defining a `float' constant. */ + + #define ASM_OUTPUT_FLOAT(FILE,VALUE) i960_output_float(FILE, VALUE) + + /* This is how to output an assembler line defining an `int' constant. */ + + #define ASM_OUTPUT_INT(FILE,VALUE) \ + ( fprintf (FILE, "\t.word "), \ + output_addr_const (FILE, (VALUE)), \ + fprintf (FILE, "\n")) + + /* Likewise for `char' and `short' constants. */ + + #define ASM_OUTPUT_SHORT(FILE,VALUE) \ + ( fprintf (FILE, "\t.short "), \ + output_addr_const (FILE, (VALUE)), \ + fprintf (FILE, "\n")) + + #define ASM_OUTPUT_CHAR(FILE,VALUE) \ + ( fprintf (FILE, "\t.byte "), \ + output_addr_const (FILE, (VALUE)), \ + fprintf (FILE, "\n")) + + /* This is how to output an assembler line for a numeric constant byte. */ + + #define ASM_OUTPUT_BYTE(FILE,VALUE) \ + fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) + + #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ + fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO]) + + /* This is how to output an insn to pop a register from the stack. + It need not be very fast code. */ + + #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ + fprintf (FILE, "\tsubo\t4,sp,sp\n\tld\t(sp),%s\n", reg_names[REGNO]) + + /* This is how to output an element of a case-vector that is absolute. */ + + #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ + fprintf (FILE, "\t.word L%d\n", VALUE) + + /* This is how to output an element of a case-vector that is relative. */ + + #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ + fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL) + + /* This is how to output an assembler line that says to advance the + location counter to a multiple of 2**LOG bytes. */ + + #define ASM_OUTPUT_ALIGN(FILE,LOG) \ + fprintf (FILE, "\t.align %d\n", (LOG)) + + #define ASM_OUTPUT_SKIP(FILE,SIZE) \ + fprintf (FILE, "\t.space %d\n", (SIZE)) + + /* This says how to output an assembler line + to define a global common symbol. */ + + /* For common objects, output unpadded size... gld960 & lnk960 both + have code to align each common object at link time. Also, if size + is 0, treat this as a declaration, not a definition - i.e., + do nothing at all. */ + + #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ + { if ((SIZE) != 0) \ + { \ + fputs (".globl ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fputs ("\n.comm ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%d\n", (ROUNDED)); \ + } \ + } + + /* This says how to output an assembler line to define a local common symbol. + Output unpadded size, with request to linker to align as requested. + 0 size should not be possible here. */ + + #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ + ( fputs (".bss\t", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%d,%d\n", (SIZE), \ + ((ALIGN) <= 8 ? 0 \ + : ((ALIGN) <= 16 ? 1 \ + : ((ALIGN) <= 32 ? 2 \ + : ((ALIGN <= 64 ? 3 : 4))))))) + + /* Output text for an #ident directive. */ + #define ASM_OUTPUT_IDENT(FILE, STR) fprintf(FILE, "\t# %s\n", STR); + + /* Align code to 8 byte boundary if TARGET_CODE_ALIGN is true. */ + + #define ASM_OUTPUT_ALIGN_CODE(FILE) \ + { if (TARGET_CODE_ALIGN) fputs("\t.align 3\n",FILE); } + + /* Store in OUTPUT a string (made with alloca) containing + an assembler-name for a local static variable named NAME. + LABELNO is an integer which is different for each call. */ + + #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ + ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ + sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) + + /* Define the parentheses used to group arithmetic operations + in assembler code. */ + + #define ASM_OPEN_PAREN "(" + #define ASM_CLOSE_PAREN ")" + + /* Define results of standard character escape sequences. */ + #define TARGET_BELL 007 + #define TARGET_BS 010 + #define TARGET_TAB 011 + #define TARGET_NEWLINE 012 + #define TARGET_VT 013 + #define TARGET_FF 014 + #define TARGET_CR 015 + + /* Output assembler code to FILE to initialize this source file's + basic block profiling info, if that has not already been done. */ + + #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ + { fprintf (FILE, "\tld LPBX0,g12\n"); \ + fprintf (FILE, "\tcmpobne 0,g12,LPY%d\n",LABELNO);\ + fprintf (FILE, "\tlda LPBX0,g12\n"); \ + fprintf (FILE, "\tcall ___bb_init_func\n"); \ + fprintf (FILE, "LPY%d:\n",LABELNO); } + + /* Output assembler code to FILE to increment the entry-count for + the BLOCKNO'th basic block in this source file. */ + + #define BLOCK_PROFILER(FILE, BLOCKNO) \ + { int blockn = (BLOCKNO); \ + fprintf (FILE, "\tld LPBX2+%d,g12\n", 4 * blockn); \ + fprintf (FILE, "\taddo g12,1,g12\n"); \ + fprintf (FILE, "\tst g12,LPBX2+%d\n", 4 * blockn); } + + /* Print operand X (an rtx) in assembler syntax to file FILE. + CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. + For `%' followed by punctuation, CODE is the punctuation and X is null. */ + + #define PRINT_OPERAND(FILE, X, CODE) \ + i960_print_operand (FILE, X, CODE); + + /* Print a memory address as an operand to reference that memory location. */ + + #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ + i960_print_operand_addr (FILE, ADDR) + + /* Output assembler code for a block containing the constant parts + of a trampoline, leaving space for the variable parts. */ + + /* On the i960, the trampoline contains three instructions: + ldconst _function, r4 + ldconst static addr, r3 + jump (r4) */ + + #define TRAMPOLINE_TEMPLATE(FILE) \ + { \ + ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C203000)); \ + ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ + ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C183000)); \ + ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ + ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x84212000)); \ + } + + /* Length in units of the trampoline for entering a nested function. */ + + #define TRAMPOLINE_SIZE 20 + + /* Emit RTL insns to initialize the variable parts of a trampoline. + FNADDR is an RTX for the address of the function's pure code. + CXT is an RTX for the static chain value for the function. */ + + #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ + { \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), \ + FNADDR); \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), \ + CXT); \ + } + + #if 0 + /* Promote char and short arguments to ints, when want compitibility with + the iC960 compilers. */ + + /* ??? In order for this to work, all users would need to be changed + to test the value of the macro at run time. */ + #define PROMOTE_PROTOTYPES TARGET_CLEAN_LINKAGE + /* ??? This does not exist. */ + #define PROMOTE_RETURN TARGET_CLEAN_LINKAGE + #endif + + /* Instruction type definitions. Used to alternate instructions types for + better performance on the C series chips. */ + + enum insn_types { I_TYPE_REG, I_TYPE_MEM, I_TYPE_CTRL }; + + /* Holds the insn type of the last insn output to the assembly file. */ + + extern enum insn_types i960_last_insn_type; + + /* Parse opcodes, and set the insn last insn type based on them. */ + + #define ASM_OUTPUT_OPCODE(FILE, INSN) i960_scan_opcode (INSN) + + /* Table listing what rtl codes each predicate in i960.c will accept. */ + + #define PREDICATE_CODES \ + {"fpmove_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ + LABEL_REF, SUBREG, REG, MEM}}, \ + {"arith_operand", {SUBREG, REG, CONST_INT}}, \ + {"fp_arith_operand", {SUBREG, REG, CONST_DOUBLE}}, \ + {"signed_arith_operand", {SUBREG, REG, CONST_INT}}, \ + {"literal", {CONST_INT}}, \ + {"fp_literal_one", {CONST_DOUBLE}}, \ + {"fp_literal_double", {CONST_DOUBLE}}, \ + {"fp_literal", {CONST_DOUBLE}}, \ + {"signed_literal", {CONST_INT}}, \ + {"symbolic_memory_operand", {SUBREG, MEM}}, \ + {"eq_or_neq", {EQ, NE}}, \ + {"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT, \ + CONST_DOUBLE, CONST}}, \ + {"power2_operand", {CONST_INT}}, + + /* Define functions in i960.c and used in insn-output.c. */ + + extern char *i960_output_ldconst (); + extern char *i960_output_call_insn (); + extern char *i960_output_ret_insn (); diff -rc2N gcc-2.1/config/i960.md gcc-2.2.1/config/i960.md *** gcc-2.1/config/i960.md --- gcc-2.2.1/config/i960.md Wed May 27 17:55:12 1992 *************** *** 0 **** --- 1,2512 ---- + ;;- Machine description for Intel 80960 chip for GNU C compiler + ;; Copyright (C) 1992 Free Software Foundation, Inc. + ;; Contributed by Steven McGeady, Intel Corp. + ;; Additional work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson + ;; Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support. + + ;; This file is part of GNU CC. + + ;; GNU CC is free software; you can redistribute it and/or modify + ;; it under the terms of the GNU General Public License as published by + ;; the Free Software Foundation; either version 2, or (at your option) + ;; any later version. + + ;; GNU CC is distributed in the hope that it will be useful, + ;; but WITHOUT ANY WARRANTY; without even the implied warranty of + ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + ;; GNU General Public License for more details. + + ;; You should have received a copy of the GNU General Public License + ;; along with GNU CC; see the file COPYING. If not, write to + ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + + ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. + + ;; Insn attributes which describe the i960. + + ;; Modscan is not used, since the compiler never emits any of these insns. + (define_attr "type" + "move,arith,alu2,mult,div,modscan,load,store,branch,call,address,compare,fpload,fpstore,fpmove,fpcvt,fpcc,fpadd,fpmul,fpdiv,multi,misc" + (const_string "arith")) + + ;; Length (in # of insns). + (define_attr "length" "" + (cond [(eq_attr "type" "load,fpload") + (if_then_else (match_operand 1 "symbolic_memory_operand" "") + (const_int 2) + (const_int 1)) + (eq_attr "type" "store,fpstore") + (if_then_else (match_operand 0 "symbolic_memory_operand" "") + (const_int 2) + (const_int 1)) + (eq_attr "type" "address") + (const_int 2)] + (const_int 1))) + + (define_asm_attributes + [(set_attr "length" "1") + (set_attr "type" "multi")]) + + ;; (define_function_unit {name} {num-units} {n-users} {test} + ;; {ready-delay} {busy-delay} [{conflict-list}]) + + ;; The integer ALU + (define_function_unit "alu" 2 0 (eq_attr "type" "arith,compare,move,address") 1 0) + (define_function_unit "alu" 2 0 (eq_attr "type" "alu2") 2 0) + (define_function_unit "alu" 2 0 (eq_attr "type" "mult") 5 0) + (define_function_unit "alu" 2 0 (eq_attr "type" "div") 35 0) + (define_function_unit "alu" 2 0 (eq_attr "type" "modscan") 3 0) + + ;; Memory with load-delay of 1 (i.e., 2 cycle load). + (define_function_unit "memory" 1 0 (eq_attr "type" "load,fpload") 2 0) + + ;; Floating point operations. + (define_function_unit "fp" 1 2 (eq_attr "type" "fpmove") 5 0) + (define_function_unit "fp" 1 2 (eq_attr "type" "fpcvt") 35 0) + (define_function_unit "fp" 1 2 (eq_attr "type" "fpcc") 10 0) + (define_function_unit "fp" 1 2 (eq_attr "type" "fpadd") 10 0) + (define_function_unit "fp" 1 2 (eq_attr "type" "fpmul") 20 0) + (define_function_unit "fp" 1 2 (eq_attr "type" "fpdiv") 35 0) + + ;; Compare instructions. + ;; This controls RTL generation and register allocation. + + ;; We generate RTL for comparisons and branches by having the cmpxx + ;; patterns store away the operands. Then, the scc and bcc patterns + ;; emit RTL for both the compare and the branch. + ;; + ;; We start with the DEFINE_EXPANDs, then then DEFINE_INSNs to match + ;; the patterns. Finally, we have the DEFINE_SPLITs for some of the scc + ;; insns that actually require more than one machine instruction. + + ;; Put cmpsi first because it is expected to be the most common. + + (define_expand "cmpsi" + [(set (reg:CC 36) + (compare:CC (match_operand:SI 0 "nonimmediate_operand" "") + (match_operand:SI 1 "general_operand" "")))] + "" + " + { + i960_compare_op0 = operands[0]; + i960_compare_op1 = operands[1]; + DONE; + }") + + (define_expand "cmpdf" + [(set (reg:CC 36) + (compare:CC (match_operand:DF 0 "register_operand" "r") + (match_operand:DF 1 "nonmemory_operand" "rGH")))] + "TARGET_NUMERICS" + " + { + i960_compare_op0 = operands[0]; + i960_compare_op1 = operands[1]; + DONE; + }") + + (define_expand "cmpsf" + [(set (reg:CC 36) + (compare:CC (match_operand:SF 0 "register_operand" "r") + (match_operand:SF 1 "nonmemory_operand" "rGH")))] + "TARGET_NUMERICS" + " + { + i960_compare_op0 = operands[0]; + i960_compare_op1 = operands[1]; + DONE; + }") + + ;; Now the DEFINE_INSNs for the compare and scc cases. First the compares. + + (define_insn "" + [(set (reg:CC 36) + (compare:CC (match_operand:SI 0 "register_operand" "d") + (match_operand:SI 1 "arith_operand" "dI")))] + "" + "cmpi %0,%1" + [(set_attr "type" "compare")]) + + (define_insn "" + [(set (reg:CC_UNS 36) + (compare:CC_UNS (match_operand:SI 0 "register_operand" "d") + (match_operand:SI 1 "arith_operand" "dI")))] + "" + "cmpo %0,%1" + [(set_attr "type" "compare")]) + + (define_insn "" + [(set (reg:CC 36) + (compare:CC (match_operand:DF 0 "register_operand" "r") + (match_operand:DF 1 "nonmemory_operand" "rGH")))] + "TARGET_NUMERICS" + "cmprl %0,%1" + [(set_attr "type" "fpcc")]) + + (define_insn "" + [(set (reg:CC 36) + (compare:CC (match_operand:SF 0 "register_operand" "r") + (match_operand:SF 1 "nonmemory_operand" "rGH")))] + "TARGET_NUMERICS" + "cmpr %0,%1" + [(set_attr "type" "fpcc")]) + + ;; Instruction definitions for branch-on-bit-set and clear insns. + + (define_insn "" + [(set (pc) + (if_then_else + (ne (sign_extract:SI (match_operand:SI 1 "register_operand" "d") + (const_int 1) + (match_operand:SI 2 "arith_operand" "dI")) + (const_int 0)) + (label_ref (match_operand 3 "" "")) + (pc)))] + "" + "bbs %2,%1,%l3" + [(set_attr "type" "branch")]) + + (define_insn "" + [(set (pc) + (if_then_else + (eq (sign_extract:SI (match_operand:SI 1 "register_operand" "d") + (const_int 1) + (match_operand:SI 2 "arith_operand" "dI")) + (const_int 0)) + (label_ref (match_operand 3 "" "")) + (pc)))] + "" + "bbc %2,%1,%l3" + [(set_attr "type" "branch")]) + + (define_insn "" + [(set (pc) + (if_then_else + (ne (zero_extract:SI (match_operand:SI 1 "register_operand" "d") + (const_int 1) + (match_operand:SI 2 "arith_operand" "dI")) + (const_int 0)) + (label_ref (match_operand 3 "" "")) + (pc)))] + "" + "bbs %2,%1,%l3" + [(set_attr "type" "branch")]) + + (define_insn "" + [(set (pc) + (if_then_else + (eq (zero_extract:SI (match_operand:SI 1 "register_operand" "d") + (const_int 1) + (match_operand:SI 2 "arith_operand" "dI")) + (const_int 0)) + (label_ref (match_operand 3 "" "")) + (pc)))] + "" + "bbc %2,%1,%l3" + [(set_attr "type" "branch")]) + + ;; ??? These will never match. The LOG_LINKs necessary to make these match + ;; are not created by flow. These remain as a reminder to make this work + ;; some day. + + (define_insn "" + [(set (reg:CC 36) + (compare (match_operand:SI 0 "arith_operand" "d") + (match_operand:SI 1 "arith_operand" "d"))) + (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))] + "0" + "cmpinci %0,%1" + [(set_attr "type" "compare")]) + + (define_insn "" + [(set (reg:CC_UNS 36) + (compare (match_operand:SI 0 "arith_operand" "d") + (match_operand:SI 1 "arith_operand" "d"))) + (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))] + "0" + "cmpinco %0,%1" + [(set_attr "type" "compare")]) + + (define_insn "" + [(set (reg:CC 36) + (compare (match_operand:SI 0 "arith_operand" "d") + (match_operand:SI 1 "arith_operand" "d"))) + (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))] + "0" + "cmpdeci %0,%1" + [(set_attr "type" "compare")]) + + (define_insn "" + [(set (reg:CC_UNS 36) + (compare (match_operand:SI 0 "arith_operand" "d") + (match_operand:SI 1 "arith_operand" "d"))) + (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))] + "0" + "cmpdeco %0,%1" + [(set_attr "type" "compare")]) + + ;; Templates to store result of condition. + ;; '1' is stored if condition is true. + ;; '0' is stored if condition is false. + ;; These should use predicate "general_operand", since + ;; gcc seems to be creating mem references which use these + ;; templates. + + (define_expand "seq" + [(set (match_operand:SI 0 "general_operand" "=d") + (eq (match_dup 1) (const_int 0)))] + "" + " + { + operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1); + }") + + (define_expand "sne" + [(set (match_operand:SI 0 "general_operand" "=d") + (ne (match_dup 1) (const_int 0)))] + "" + " + { + operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1); + }") + + (define_expand "sgt" + [(set (match_operand:SI 0 "general_operand" "=d") + (gt (match_dup 1) (const_int 0)))] + "" + " + { + operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1); + }") + + (define_expand "sgtu" + [(set (match_operand:SI 0 "general_operand" "=d") + (gtu (match_dup 1) (const_int 0)))] + "" + " + { + operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1); + }") + + (define_expand "slt" + [(set (match_operand:SI 0 "general_operand" "=d") + (lt (match_dup 1) (const_int 0)))] + "" + " + { + operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1); + }") + + (define_expand "sltu" + [(set (match_operand:SI 0 "general_operand" "=d") + (ltu (match_dup 1) (const_int 0)))] + "" + " + { + operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1); + }") + + (define_expand "sge" + [(set (match_operand:SI 0 "general_operand" "=d") + (ge (match_dup 1) (const_int 0)))] + "" + " + { + operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1); + }") + + (define_expand "sgeu" + [(set (match_operand:SI 0 "general_operand" "=d") + (geu (match_dup 1) (const_int 0)))] + "" + " + { + operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1); + }") + + (define_expand "sle" + [(set (match_operand:SI 0 "general_operand" "=d") + (le (match_dup 1) (const_int 0)))] + "" + " + { + operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1); + }") + + (define_expand "sleu" + [(set (match_operand:SI 0 "general_operand" "=d") + (leu (match_dup 1) (const_int 0)))] + "" + " + { + operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1); + }") + + (define_insn "" + [(set (match_operand:SI 0 "general_operand" "=d") + (match_operator 1 "comparison_operator" [(reg:CC 36) (const_int 0)]))] + "" + "test%C1 %0" + [(set_attr "type" "compare")]) + + (define_insn "" + [(set (match_operand:SI 0 "general_operand" "=d") + (match_operator 1 "comparison_operator" [(reg:CC_UNS 36) (const_int 0)]))] + "" + "test%C1 %0" + [(set_attr "type" "compare")]) + + ;; These control RTL generation for conditional jump insns + ;; and match them for register allocation. + + (define_expand "beq" + [(set (pc) + (if_then_else (eq (match_dup 1) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " + { operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1); }") + + (define_expand "bne" + [(set (pc) + (if_then_else (ne (match_dup 1) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " + { operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1); }") + + (define_expand "bgt" + [(set (pc) + (if_then_else (gt (match_dup 1) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " + { operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1); }") + + (define_expand "bgtu" + [(set (pc) + (if_then_else (gtu (match_dup 1) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " + { operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1); }") + + (define_expand "blt" + [(set (pc) + (if_then_else (lt (match_dup 1) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " + { operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1); }") + + (define_expand "bltu" + [(set (pc) + (if_then_else (ltu (match_dup 1) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " + { operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1); }") + + (define_expand "bge" + [(set (pc) + (if_then_else (ge (match_dup 1) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " + { operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1); }") + + (define_expand "bgeu" + [(set (pc) + (if_then_else (geu (match_dup 1) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " + { operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1); }") + + (define_expand "ble" + [(set (pc) + (if_then_else (le (match_dup 1) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " + { operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1); }") + + (define_expand "bleu" + [(set (pc) + (if_then_else (leu (match_dup 1) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " + { operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1); }") + + ;; Now the normal branch insns (forward and reverse). + + (define_insn "" + [(set (pc) + (if_then_else (match_operator 0 "comparison_operator" + [(reg:CC 36) (const_int 0)]) + (label_ref (match_operand 1 "" "")) + (pc)))] + "" + "b%C0 %l1" + [(set_attr "type" "branch")]) + + (define_insn "" + [(set (pc) + (if_then_else (match_operator 0 "comparison_operator" + [(reg:CC 36) (const_int 0)]) + (pc) + (label_ref (match_operand 1 "" ""))))] + "" + "b%I0 %l1" + [(set_attr "type" "branch")]) + + (define_insn "" + [(set (pc) + (if_then_else (match_operator 0 "comparison_operator" + [(reg:CC_UNS 36) (const_int 0)]) + (label_ref (match_operand 1 "" "")) + (pc)))] + "" + "b%C0 %l1" + [(set_attr "type" "branch")]) + + (define_insn "" + [(set (pc) + (if_then_else (match_operator 0 "comparison_operator" + [(reg:CC_UNS 36) (const_int 0)]) + (pc) + (label_ref (match_operand 1 "" ""))))] + "" + "b%I0 %l1" + [(set_attr "type" "branch")]) + + (define_insn "" + [(set (pc) + (if_then_else + (match_operator 0 "comparison_operator" + [(match_operand:SI 1 "arith_operand" "d") + (match_operand:SI 2 "arith_operand" "dI")]) + (label_ref (match_operand 3 "" "")) + (pc)))] + "" + "cmp%S0%B0%R0 %2,%1,%l3" + [(set_attr "type" "branch")]) + + (define_insn "" + [(set (pc) + (if_then_else + (match_operator 0 "comparison_operator" + [(match_operand:SI 1 "arith_operand" "d") + (match_operand:SI 2 "arith_operand" "dI")]) + (pc) + (label_ref (match_operand 3 "" ""))))] + "" + "cmp%S0%B0%X0 %2,%1,%l3" + [(set_attr "type" "branch")]) + + ;; Normal move instructions. + ;; This code is based on the sparc machine desciption. + + (define_expand "movsi" + [(set (match_operand:SI 0 "general_operand" "") + (match_operand:SI 1 "general_operand" ""))] + "" + " + { + if (emit_move_sequence (operands, SImode)) + DONE; + }") + + ;; The store case can not be separate, because reload may convert a register + ;; to register move insn to a store (or load) insn without rerecognizing + ;; the insn. + + ;; Special pattern for zero stores to memory for functions which don't use + ;; the arg pointer. + + (define_insn "" + [(set (match_operand:SI 0 "general_operand" "=d,d,d,m") + (match_operand:SI 1 "general_operand" "dI,i,m,dJ"))] + "current_function_args_size == 0 + && (register_operand (operands[0], SImode) + || register_operand (operands[1], SImode) + || operands[1] == const0_rtx)" + "* + { + switch (which_alternative) + { + case 0: + if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) + { + if (GET_CODE (operands[1]) == REG) + return \"lda (%1),%0\"; + else + return \"lda %1,%0\"; + } + return \"mov %1,%0\"; + case 1: + return i960_output_ldconst (operands[0], operands[1]); + case 2: + return \"ld %1,%0\"; + case 3: + if (operands[1] == const0_rtx) + return \"st g14,%0\"; + return \"st %1,%0\"; + } + }" + [(set_attr "type" "move,address,load,store") + (set_attr "length" "*,3,*,*")]) + + (define_insn "" + [(set (match_operand:SI 0 "general_operand" "=d,d,d,m") + (match_operand:SI 1 "general_operand" "dI,i,m,d"))] + "current_function_args_size != 0 + && (register_operand (operands[0], SImode) + || register_operand (operands[1], SImode))" + "* + { + switch (which_alternative) + { + case 0: + if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) + { + if (GET_CODE (operands[1]) == REG) + return \"lda (%1),%0\"; + else + return \"lda %1,%0\"; + } + return \"mov %1,%0\"; + case 1: + return i960_output_ldconst (operands[0], operands[1]); + case 2: + return \"ld %1,%0\"; + case 3: + return \"st %1,%0\"; + } + }" + [(set_attr "type" "move,address,load,store") + (set_attr "length" "*,3,*,*")]) + + (define_expand "movhi" + [(set (match_operand:HI 0 "general_operand" "") + (match_operand:HI 1 "general_operand" ""))] + "" + " + { + if (emit_move_sequence (operands, HImode)) + DONE; + }") + + ;; Special pattern for zero stores to memory for functions which don't use + ;; the arg pointer. + + ;; The store case can not be separate. See above. + (define_insn "" + [(set (match_operand:HI 0 "general_operand" "=d,d,d,m") + (match_operand:HI 1 "general_operand" "dI,i,m,dJ"))] + "current_function_args_size == 0 + && (register_operand (operands[0], HImode) + || register_operand (operands[1], HImode) + || operands[1] == const0_rtx)" + "* + { + switch (which_alternative) + { + case 0: + if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) + { + if (GET_CODE (operands[1]) == REG) + return \"lda (%1),%0\"; + else + return \"lda %1,%0\"; + } + return \"mov %1,%0\"; + case 1: + return i960_output_ldconst (operands[0], operands[1]); + case 2: + return \"ldos %1,%0\"; + case 3: + if (operands[1] == const0_rtx) + return \"stos g14,%0\"; + return \"stos %1,%0\"; + } + }" + [(set_attr "type" "move,misc,load,store") + (set_attr "length" "*,3,*,*")]) + + ;; The store case can not be separate. See above. + (define_insn "" + [(set (match_operand:HI 0 "general_operand" "=d,d,d,m") + (match_operand:HI 1 "general_operand" "dI,i,m,d"))] + "current_function_args_size != 0 + && (register_operand (operands[0], HImode) + || register_operand (operands[1], HImode))" + "* + { + switch (which_alternative) + { + case 0: + if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) + { + if (GET_CODE (operands[1]) == REG) + return \"lda (%1),%0\"; + else + return \"lda %1,%0\"; + } + return \"mov %1,%0\"; + case 1: + return i960_output_ldconst (operands[0], operands[1]); + case 2: + return \"ldos %1,%0\"; + case 3: + return \"stos %1,%0\"; + } + }" + [(set_attr "type" "move,misc,load,store") + (set_attr "length" "*,3,*,*")]) + + (define_expand "movqi" + [(set (match_operand:QI 0 "general_operand" "") + (match_operand:QI 1 "general_operand" ""))] + "" + " + { + if (emit_move_sequence (operands, QImode)) + DONE; + }") + + ;; The store case can not be separate. See comment above. + (define_insn "" + [(set (match_operand:QI 0 "general_operand" "=d,d,d,m") + (match_operand:QI 1 "general_operand" "dI,i,m,dJ"))] + "current_function_args_size == 0 + && (register_operand (operands[0], QImode) + || register_operand (operands[1], QImode) + || operands[1] == const0_rtx)" + "* + { + switch (which_alternative) + { + case 0: + if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) + { + if (GET_CODE (operands[1]) == REG) + return \"lda (%1),%0\"; + else + return \"lda %1,%0\"; + } + return \"mov %1,%0\"; + case 1: + return i960_output_ldconst (operands[0], operands[1]); + case 2: + return \"ldob %1,%0\"; + case 3: + if (operands[1] == const0_rtx) + return \"stob g14,%0\"; + return \"stob %1,%0\"; + } + }" + [(set_attr "type" "move,misc,load,store") + (set_attr "length" "*,3,*,*")]) + + ;; The store case can not be separate. See comment above. + (define_insn "" + [(set (match_operand:QI 0 "general_operand" "=d,d,d,m") + (match_operand:QI 1 "general_operand" "dI,i,m,d"))] + "current_function_args_size != 0 + && (register_operand (operands[0], QImode) + || register_operand (operands[1], QImode))" + "* + { + switch (which_alternative) + { + case 0: + if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) + { + if (GET_CODE (operands[1]) == REG) + return \"lda (%1),%0\"; + else + return \"lda %1,%0\"; + } + return \"mov %1,%0\"; + case 1: + return i960_output_ldconst (operands[0], operands[1]); + case 2: + return \"ldob %1,%0\"; + case 3: + return \"stob %1,%0\"; + } + }" + [(set_attr "type" "move,misc,load,store") + (set_attr "length" "*,3,*,*")]) + + (define_expand "movdi" + [(set (match_operand:DI 0 "general_operand" "") + (match_operand:DI 1 "general_operand" ""))] + "" + " + { + if (emit_move_sequence (operands, DImode)) + DONE; + }") + + ;; The store case can not be separate. See comment above. + (define_insn "" + [(set (match_operand:DI 0 "general_operand" "=d,d,d,m") + (match_operand:DI 1 "general_operand" "dI,i,m,dJ"))] + "current_function_args_size == 0 + && (register_operand (operands[0], DImode) + || register_operand (operands[1], DImode) + || operands[1] == const0_rtx)" + "* + { + switch (which_alternative) + { + case 0: + return \"movl %1,%0\"; + case 1: + return i960_output_ldconst (operands[0], operands[1]); + case 2: + return \"ldl %1,%0\"; + case 3: + if (operands[1] == const0_rtx) + return \"st g14,%0\;st g14,4(%0)\"; + return \"stl %1,%0\"; + } + }" + [(set_attr "type" "move,load,load,store")]) + + ;; The store case can not be separate. See comment above. + (define_insn "" + [(set (match_operand:DI 0 "general_operand" "=d,d,d,m") + (match_operand:DI 1 "general_operand" "dI,i,m,d"))] + "current_function_args_size != 0 + && (register_operand (operands[0], DImode) + || register_operand (operands[1], DImode))" + "* + { + switch (which_alternative) + { + case 0: + return \"movl %1,%0\"; + case 1: + return i960_output_ldconst (operands[0], operands[1]); + case 2: + return \"ldl %1,%0\"; + case 3: + return \"stl %1,%0\"; + } + }" + [(set_attr "type" "move,load,load,store")]) + + (define_expand "movti" + [(set (match_operand:TI 0 "general_operand" "") + (match_operand:TI 1 "general_operand" ""))] + "" + " + { + if (emit_move_sequence (operands, TImode)) + DONE; + }") + + ;; The store case can not be separate. See comment above. + (define_insn "" + [(set (match_operand:TI 0 "general_operand" "=d,d,d,m") + (match_operand:TI 1 "general_operand" "dI,i,m,dJ"))] + "current_function_args_size == 0 + && (register_operand (operands[0], TImode) + || register_operand (operands[1], TImode) + || operands[1] == const0_rtx)" + "* + { + switch (which_alternative) + { + case 0: + return \"movq %1,%0\"; + case 1: + return i960_output_ldconst (operands[0], operands[1]); + case 2: + return \"ldq %1,%0\"; + case 3: + if (operands[1] == const0_rtx) + return \"st g14,%0\;st g14,4(%0)\;st g14,8(%0)\;st g14,12(%0)\"; + return \"stq %1,%0\"; + } + }" + [(set_attr "type" "move,load,load,store")]) + + ;; The store case can not be separate. See comment above. + (define_insn "" + [(set (match_operand:TI 0 "general_operand" "=d,d,d,m") + (match_operand:TI 1 "general_operand" "dI,i,m,d"))] + "current_function_args_size != 0 + && (register_operand (operands[0], TImode) + || register_operand (operands[1], TImode))" + "* + { + switch (which_alternative) + { + case 0: + return \"movq %1,%0\"; + case 1: + return i960_output_ldconst (operands[0], operands[1]); + case 2: + return \"ldq %1,%0\"; + case 3: + return \"stq %1,%0\"; + } + }" + [(set_attr "type" "move,load,load,store")]) + + (define_expand "store_multiple" + [(set (match_operand:SI 0 "" "") ;;- dest + (match_operand:SI 1 "" "")) ;;- src + (use (match_operand:SI 2 "" ""))] ;;- nregs + "" + " + { + int regno; + int count; + rtx from; + int i; + + if (GET_CODE (operands[0]) != MEM + || GET_CODE (operands[1]) != REG + || GET_CODE (operands[2]) != CONST_INT) + FAIL; + + count = INTVAL (operands[2]); + if (count > 12) + FAIL; + + regno = REGNO (operands[1]); + from = memory_address (SImode, XEXP (operands[0], 0)); + while (count >= 4 && ((regno & 3) == 0)) + { + emit_insn (gen_rtx (SET, VOIDmode, + gen_rtx (MEM, TImode, from), + gen_rtx (REG, TImode, regno))); + count -= 4; + regno += 4; + from = memory_address (TImode, plus_constant (from, 16)); + } + while (count >= 2 && ((regno & 1) == 0)) + { + emit_insn (gen_rtx (SET, VOIDmode, + gen_rtx (MEM, DImode, from), + gen_rtx (REG, DImode, regno))); + count -= 2; + regno += 2; + from = memory_address (DImode, plus_constant (from, 8)); + } + while (count > 0) + { + emit_insn (gen_rtx (SET, VOIDmode, + gen_rtx (MEM, SImode, from), + gen_rtx (REG, SImode, regno))); + count -= 1; + regno += 1; + from = memory_address (SImode, plus_constant (from, 4)); + } + DONE; + }") + + ;; Floating point move insns + + (define_expand "movdf" + [(set (match_operand:DF 0 "general_operand" "") + (match_operand:DF 1 "fpmove_src_operand" ""))] + "" + " + { + if (emit_move_sequence (operands, DFmode)) + DONE; + }") + + (define_insn "" + [(set (match_operand:DF 0 "general_operand" "=r,f,d,d,m") + (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,dG"))] + "current_function_args_size == 0 + && (register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode) + || operands[1] == CONST0_RTX (DFmode))" + "* + { + switch (which_alternative) + { + case 0: + if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) + return \"movrl %1,%0\"; + else + return \"movl %1,%0\"; + case 1: + return \"movrl %1,%0\"; + case 2: + return i960_output_ldconst (operands[0], operands[1]); + case 3: + return \"ldl %1,%0\"; + case 4: + if (operands[1] == CONST0_RTX (DFmode)) + return \"st g14,%0\;st g14,4(%0)\"; + return \"stl %1,%0\"; + } + }" + [(set_attr "type" "move,move,load,fpload,fpstore")]) + + (define_insn "" + [(set (match_operand:DF 0 "general_operand" "=r,f,d,d,m") + (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d"))] + "current_function_args_size != 0 + && (register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode))" + "* + { + switch (which_alternative) + { + case 0: + if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) + return \"movrl %1,%0\"; + else + return \"movl %1,%0\"; + case 1: + return \"movrl %1,%0\"; + case 2: + return i960_output_ldconst (operands[0], operands[1]); + case 3: + return \"ldl %1,%0\"; + case 4: + return \"stl %1,%0\"; + } + }" + [(set_attr "type" "move,move,load,fpload,fpstore")]) + + (define_expand "movsf" + [(set (match_operand:SF 0 "general_operand" "") + (match_operand:SF 1 "fpmove_src_operand" ""))] + "" + " + { + if (emit_move_sequence (operands, SFmode)) + DONE; + }") + + (define_insn "" + [(set (match_operand:SF 0 "general_operand" "=r,f,d,d,m") + (match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,dG"))] + "current_function_args_size == 0 + && (register_operand (operands[0], SFmode) + || register_operand (operands[1], SFmode) + || operands[1] == CONST0_RTX (SFmode))" + "* + { + switch (which_alternative) + { + case 0: + if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) + return \"movr %1,%0\"; + else + return \"mov %1,%0\"; + case 1: + return \"movr %1,%0\"; + case 2: + return i960_output_ldconst (operands[0], operands[1]); + case 3: + return \"ld %1,%0\"; + case 4: + if (operands[1] == CONST0_RTX (SFmode)) + return \"st g14,%0\"; + return \"st %1,%0\"; + } + }" + [(set_attr "type" "move,move,load,fpload,fpstore")]) + + (define_insn "" + [(set (match_operand:SF 0 "general_operand" "=r,f,d,d,m") + (match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,d"))] + "current_function_args_size != 0 + && (register_operand (operands[0], SFmode) + || register_operand (operands[1], SFmode))" + "* + { + switch (which_alternative) + { + case 0: + if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) + return \"movr %1,%0\"; + else + return \"mov %1,%0\"; + case 1: + return \"movr %1,%0\"; + case 2: + return i960_output_ldconst (operands[0], operands[1]); + case 3: + return \"ld %1,%0\"; + case 4: + return \"st %1,%0\"; + } + }" + [(set_attr "type" "move,move,load,fpload,fpstore")]) + + ;; Mixed-mode moves with sign and zero-extension. + + ;; Note that the one starting from HImode comes before those for QImode + ;; so that a constant operand will match HImode, not QImode. + + (define_expand "extendhisi2" + [(set (match_operand:SI 0 "register_operand" "") + (sign_extend:SI + (match_operand:HI 1 "nonimmediate_operand" "")))] + "" + " + { + if (GET_CODE (operand1) == REG + || (GET_CODE (operand1) == SUBREG + && GET_CODE (XEXP (operand1, 0)) == REG)) + { + rtx temp = gen_reg_rtx (SImode); + rtx shift_16 = gen_rtx (CONST_INT, VOIDmode, 16); + int op1_subreg_word = 0; + + if (GET_CODE (operand1) == SUBREG) + { + op1_subreg_word = SUBREG_WORD (operand1); + operand1 = SUBREG_REG (operand1); + } + operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); + + emit_insn (gen_ashlsi3 (temp, operand1, shift_16)); + emit_insn (gen_ashrsi3 (operand0, temp, shift_16)); + DONE; + } + }") + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] + "" + "ldis %1,%0" + [(set_attr "type" "load")]) + + (define_expand "extendqisi2" + [(set (match_operand:SI 0 "register_operand" "") + (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] + "" + " + { + if (GET_CODE (operand1) == REG + || (GET_CODE (operand1) == SUBREG + && GET_CODE (XEXP (operand1, 0)) == REG)) + { + rtx temp = gen_reg_rtx (SImode); + rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); + int op1_subreg_word = 0; + + if (GET_CODE (operand1) == SUBREG) + { + op1_subreg_word = SUBREG_WORD (operand1); + operand1 = SUBREG_REG (operand1); + } + operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word), + + emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); + emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); + DONE; + } + }") + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] + "" + "ldib %1,%0" + [(set_attr "type" "load")]) + + (define_expand "extendqihi2" + [(set (match_operand:HI 0 "register_operand" "") + (sign_extend:HI + (match_operand:QI 1 "nonimmediate_operand" "")))] + "" + " + { + if (GET_CODE (operand1) == REG + || (GET_CODE (operand1) == SUBREG + && GET_CODE (XEXP (operand1, 0)) == REG)) + { + rtx temp = gen_reg_rtx (SImode); + rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); + int op0_subreg_word = 0; + int op1_subreg_word = 0; + + if (GET_CODE (operand1) == SUBREG) + { + op1_subreg_word = SUBREG_WORD (operand1); + operand1 = SUBREG_REG (operand1); + } + operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); + + if (GET_CODE (operand0) == SUBREG) + { + op0_subreg_word = SUBREG_WORD (operand0); + operand0 = SUBREG_REG (operand0); + } + if (GET_MODE (operand0) != SImode) + operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subreg_word); + + emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); + emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); + DONE; + } + }") + + (define_insn "" + [(set (match_operand:HI 0 "register_operand" "=d") + (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))] + "" + "ldib %1,%0" + [(set_attr "type" "load")]) + + (define_expand "zero_extendhisi2" + [(set (match_operand:SI 0 "register_operand" "") + (zero_extend:SI + (match_operand:HI 1 "nonimmediate_operand" "")))] + "" + " + { + if (GET_CODE (operand1) == REG + || (GET_CODE (operand1) == SUBREG + && GET_CODE (XEXP (operand1, 0)) == REG)) + { + rtx temp = gen_reg_rtx (SImode); + rtx shift_16 = gen_rtx (CONST_INT, VOIDmode, 16); + int op1_subreg_word = 0; + + if (GET_CODE (operand1) == SUBREG) + { + op1_subreg_word = SUBREG_WORD (operand1); + operand1 = SUBREG_REG (operand1); + } + operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); + + emit_insn (gen_ashlsi3 (temp, operand1, shift_16)); + emit_insn (gen_lshrsi3 (operand0, temp, shift_16)); + DONE; + } + }") + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] + "" + "ldos %1,%0" + [(set_attr "type" "load")]) + + ;; Using shifts here generates much better code than doing an `and 255'. + ;; This is mainly because the `and' requires loading the constant separately, + ;; the constant is likely to get optimized, and then the compiler can't + ;; optimize the `and' because it doesn't know that one operand is a constant. + + (define_expand "zero_extendqisi2" + [(set (match_operand:SI 0 "register_operand" "") + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] + "" + " + { + if (GET_CODE (operand1) == REG + || (GET_CODE (operand1) == SUBREG + && GET_CODE (XEXP (operand1, 0)) == REG)) + { + rtx temp = gen_reg_rtx (SImode); + rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); + int op1_subreg_word = 0; + + if (GET_CODE (operand1) == SUBREG) + { + op1_subreg_word = SUBREG_WORD (operand1); + operand1 = SUBREG_REG (operand1); + } + operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); + + emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); + emit_insn (gen_lshrsi3 (operand0, temp, shift_24)); + DONE; + } + }") + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] + "" + "ldob %1,%0" + [(set_attr "type" "load")]) + + (define_expand "zero_extendqihi2" + [(set (match_operand:HI 0 "register_operand" "") + (zero_extend:HI + (match_operand:QI 1 "nonimmediate_operand" "")))] + "" + " + { + if (GET_CODE (operand1) == REG + || (GET_CODE (operand1) == SUBREG + && GET_CODE (XEXP (operand1, 0)) == REG)) + { + rtx temp = gen_reg_rtx (SImode); + rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); + int op0_subreg_word = 0; + int op1_subreg_word = 0; + + if (GET_CODE (operand1) == SUBREG) + { + op1_subreg_word = SUBREG_WORD (operand1); + operand1 = SUBREG_REG (operand1); + } + operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); + + if (GET_CODE (operand0) == SUBREG) + { + op0_subreg_word = SUBREG_WORD (operand0); + operand0 = SUBREG_REG (operand0); + } + if (GET_MODE (operand0) != SImode) + operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subreg_word); + + emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); + emit_insn (gen_lshrsi3 (operand0, temp, shift_24)); + DONE; + } + }") + + (define_insn "" + [(set (match_operand:HI 0 "register_operand" "=d") + (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] + "" + "ldob %1,%0" + [(set_attr "type" "load")]) + + ;; Conversions between float and double. + + (define_insn "extendsfdf2" + [(set (match_operand:DF 0 "register_operand" "=f,d") + (float_extend:DF (match_operand:SF 1 "fp_arith_operand" "dGH,fGH")))] + "TARGET_NUMERICS" + "@ + movr %1,%0 + movrl %1,%0" + [(set_attr "type" "fpmove")]) + + (define_insn "truncdfsf2" + [(set (match_operand:SF 0 "register_operand" "=d") + (float_truncate:SF + (match_operand:DF 1 "fp_arith_operand" "fGH")))] + "TARGET_NUMERICS" + "movr %1,%0" + [(set_attr "type" "fpmove")]) + + ;; Conversion between fixed point and floating point. + + (define_insn "floatsidf2" + [(set (match_operand:DF 0 "register_operand" "=f") + (float:DF (match_operand:SI 1 "register_operand" "d")))] + "TARGET_NUMERICS" + "cvtir %1,%0" + [(set_attr "type" "fpcvt")]) + + (define_insn "floatsisf2" + [(set (match_operand:SF 0 "register_operand" "=df") + (float:SF (match_operand:SI 1 "register_operand" "d")))] + "TARGET_NUMERICS" + "cvtir %1,%0" + [(set_attr "type" "fpcvt")]) + + ;; Convert a float to an actual integer. + ;; Truncation is performed as part of the conversion. + ;; The i960 requires conversion from DFmode to DImode to make + ;; unsigned conversions work properly. + + (define_insn "fixuns_truncdfdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (unsigned_fix:DI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))] + "TARGET_NUMERICS" + "cvtzril %1,%0" + [(set_attr "type" "fpcvt")]) + + (define_insn "fixuns_truncsfdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (unsigned_fix:DI (fix:SF (match_operand:SF 1 "fp_arith_operand" "fGH"))))] + "TARGET_NUMERICS" + "cvtzril %1,%0" + [(set_attr "type" "fpcvt")]) + + (define_insn "fix_truncdfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))] + "TARGET_NUMERICS" + "cvtzri %1,%0" + [(set_attr "type" "fpcvt")]) + + (define_expand "fixuns_truncdfsi2" + [(set (match_operand:SI 0 "register_operand" "") + (unsigned_fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" ""))))] + "TARGET_NUMERICS" + " + { + rtx temp = gen_reg_rtx (DImode); + emit_insn (gen_rtx (SET, VOIDmode, temp, + gen_rtx (UNSIGNED_FIX, DImode, + gen_rtx (FIX, DFmode, operands[1])))); + emit_insn (gen_rtx (SET, VOIDmode, operands[0], + gen_rtx (SUBREG, SImode, temp, 0))); + DONE; + }") + + (define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" "dfGH"))))] + "TARGET_NUMERICS" + "cvtzri %1,%0" + [(set_attr "type" "fpcvt")]) + + (define_expand "fixuns_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "") + (unsigned_fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" ""))))] + "TARGET_NUMERICS" + " + { + rtx temp = gen_reg_rtx (DImode); + emit_insn (gen_rtx (SET, VOIDmode, temp, + gen_rtx (UNSIGNED_FIX, DImode, + gen_rtx (FIX, SFmode, operands[1])))); + emit_insn (gen_rtx (SET, VOIDmode, operands[0], + gen_rtx (SUBREG, SImode, temp, 0))); + DONE; + }") + + ;; Arithmetic instructions. + + (define_insn "subsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (minus:SI (match_operand:SI 1 "arith_operand" "dI") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "subo %2,%1,%0") + + ;; Try to generate an lda instruction when it would be faster than an + ;; add instruction. + ;; Some assemblers apparently won't accept two addresses added together. + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (plus:SI (match_operand:SI 1 "arith32_operand" "%dn,i,dn") + (match_operand:SI 2 "arith32_operand" "dn,dn,i")))] + "(TARGET_C_SERIES) && (CONSTANT_P (operands[1]) || CONSTANT_P (operands[2]))" + "* + { + if (GET_CODE (operands[1]) == CONST_INT) + { + rtx tmp = operands[1]; + operands[1] = operands[2]; + operands[2] = tmp; + } + if (GET_CODE (operands[2]) == CONST_INT + && GET_CODE (operands[1]) == REG + && i960_last_insn_type != I_TYPE_REG) + { + if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) > -32) + return \"subo %n2,%1,%0\"; + else if (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32) + return \"addo %1,%2,%0\"; + } + if (CONSTANT_P (operands[1])) + return \"lda %1+%2,%0\"; + return \"lda %2(%1),%0\"; + }") + + (define_insn "addsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (plus:SI (match_operand:SI 1 "signed_arith_operand" "%dI") + (match_operand:SI 2 "signed_arith_operand" "dIK")))] + "" + "* + { + if (GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) < 0 && INTVAL (operands[2]) > -32) + return \"subo %n2,%1,%0\"; + if (i960_bypass (insn, operands[1], operands[2], 0)) + return \"addo %2,%1,%0\"; + return \"addo %1,%2,%0\"; + }") + + (define_insn "mulsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (mult:SI (match_operand:SI 1 "arith_operand" "%dI") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "* + { + if (i960_bypass (insn, operands[1], operands[2], 0)) + return \"mulo %2,%1,%0\"; + return \"mulo %1,%2,%0\"; + }" + [(set_attr "type" "mult")]) + + ;; This goes after the move/add/sub/mul instructions + ;; because those instructions are better when they apply. + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (match_operand:SI 1 "address_operand" "p"))] + "" + "lda %a1,%0" + [(set_attr "type" "load")]) + + ;; This will never be selected because of an "optimization" that GCC does. + ;; It always converts divides by a power of 2 into a sequence of instructions + ;; that does a right shift, and then corrects the result if it was negative. + + ;; (define_insn "" + ;; [(set (match_operand:SI 0 "register_operand" "=d") + ;; (div:SI (match_operand:SI 1 "arith_operand" "dI") + ;; (match_operand:SI 2 "power2_operand" "nI")))] + ;; "" + ;; "*{ + ;; operands[2] = gen_rtx(CONST_INT, VOIDmode,bitpos (INTVAL (operands[2]))); + ;; return \"shrdi %2,%1,%0\"; + ;; }" + + (define_insn "divsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (div:SI (match_operand:SI 1 "arith_operand" "dI") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "divi %2,%1,%0" + [(set_attr "type" "div")]) + + (define_insn "udivsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (udiv:SI (match_operand:SI 1 "arith_operand" "dI") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "divo %2,%1,%0" + [(set_attr "type" "div")]) + + ;; We must use `remi' not `modi' here, to ensure that `%' has the effects + ;; specified by the ANSI C standard. + + (define_insn "modsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (mod:SI (match_operand:SI 1 "arith_operand" "dI") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "remi %2,%1,%0" + [(set_attr "type" "div")]) + + (define_insn "umodsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (umod:SI (match_operand:SI 1 "arith_operand" "dI") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "remo %2,%1,%0" + [(set_attr "type" "div")]) + + ;; And instructions (with complement also). + + (define_insn "andsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (and:SI (match_operand:SI 1 "arith_operand" "%dI") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "* + { + if (i960_bypass (insn, operands[1], operands[2], 0)) + return \"and %2,%1,%0\"; + return \"and %1,%2,%0\"; + }") + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (and:SI (not:SI (match_operand:SI 1 "arith_operand" "dI")) + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "* + { + if (i960_bypass (insn, operands[1], operands[2], 0)) + return \"notand %2,%1,%0\"; + return \"andnot %1,%2,%0\"; + }") + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (ior:SI (not:SI (match_operand:SI 1 "arith_operand" "%dI")) + (not:SI (match_operand:SI 2 "arith_operand" "dI"))))] + "" + "* + { + if (i960_bypass (insn, operands[1], operands[2], 0)) + return \"nand %2,%1,%0\"; + return \"nand %1,%2,%0\"; + }") + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (not:SI (and:SI (match_operand:SI 1 "arith_operand" "%dI") + (match_operand:SI 2 "arith_operand" "dI"))))] + "" + "* + { + if (i960_bypass (insn, operands[1], operands[2], 0)) + return \"nand %2,%1,%0\"; + return \"nand %1,%2,%0\"; + }") + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (ior:SI (match_operand:SI 1 "arith_operand" "dI") + (match_operand:SI 2 "power2_operand" "n")))] + "" + "* + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + bitpos (INTVAL (operands[2]))); + return \"setbit %2,%1,%0\"; + }") + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (ior:SI (match_operand:SI 1 "power2_operand" "n") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "* + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, + bitpos (INTVAL (operands[1]))); + return \"setbit %1,%2,%0\"; + }") + + (define_insn "iorsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (ior:SI (match_operand:SI 1 "arith_operand" "%dI") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "* + { + if (i960_bypass (insn, operands[1], operands[2], 0)) + return \"or %2,%1,%0\"; + return \"or %1,%2,%0\"; + }") + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (ior:SI (not:SI (match_operand:SI 1 "arith_operand" "dI")) + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "* + { + if (i960_bypass (insn, operands[1], operands[2], 0)) + return \"notor %2,%1,%0\"; + return \"ornot %1,%2,%0\"; + }") + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (and:SI (not:SI (match_operand:SI 1 "arith_operand" "%dI")) + (not:SI (match_operand:SI 2 "arith_operand" "dI"))))] + "" + "* + { + if (i960_bypass (insn, operands[1], operands[2], 0)) + return \"nor %2,%1,%0\"; + return \"nor %1,%2,%0\"; + }") + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (not:SI (ior:SI (match_operand:SI 1 "arith_operand" "%dI") + (match_operand:SI 2 "arith_operand" "dI"))))] + "" + "* + { + if (i960_bypass (insn, operands[1], operands[2], 0)) + return \"nor %2,%1,%0\"; + return \"nor %1,%2,%0\"; + }") + + (define_insn "xorsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (xor:SI (match_operand:SI 1 "arith_operand" "%dI") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "* + { + if (i960_bypass (insn, operands[1], operands[2], 0)) + return \"xor %2,%1,%0\"; + return \"xor %1,%2,%0\"; + }") + + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (not:SI (xor:SI (match_operand:SI 1 "arith_operand" "%dI") + (match_operand:SI 2 "arith_operand" "dI"))))] + "" + "* + { + if (i960_bypass (insn, operands[1], operands[2], 0)) + return \"xnor %2,%1,%0\"; + return \"xnor %2,%1,%0\"; + }") + + (define_insn "negsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (neg:SI (match_operand:SI 1 "arith_operand" "dI")))] + "" + "subo %1,0,%0" + [(set_attr "length" "1")]) + + (define_insn "one_cmplsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (not:SI (match_operand:SI 1 "arith_operand" "dI")))] + "" + "not %1,%0" + [(set_attr "length" "1")]) + + ;; Floating point arithmetic instructions. + + (define_insn "adddf3" + [(set (match_operand:DF 0 "register_operand" "=d") + (plus:DF (match_operand:DF 1 "fp_arith_operand" "%rGH") + (match_operand:DF 2 "fp_arith_operand" "rGH")))] + "TARGET_NUMERICS" + "addrl %1,%2,%0" + [(set_attr "type" "fpadd")]) + + (define_insn "addsf3" + [(set (match_operand:SF 0 "register_operand" "=d") + (plus:SF (match_operand:SF 1 "fp_arith_operand" "%rGH") + (match_operand:SF 2 "fp_arith_operand" "rGH")))] + "TARGET_NUMERICS" + "addr %1,%2,%0" + [(set_attr "type" "fpadd")]) + + + (define_insn "subdf3" + [(set (match_operand:DF 0 "register_operand" "=d") + (minus:DF (match_operand:DF 1 "fp_arith_operand" "rGH") + (match_operand:DF 2 "fp_arith_operand" "rGH")))] + "TARGET_NUMERICS" + "subrl %2,%1,%0" + [(set_attr "type" "fpadd")]) + + (define_insn "subsf3" + [(set (match_operand:SF 0 "register_operand" "=d") + (minus:SF (match_operand:SF 1 "fp_arith_operand" "rGH") + (match_operand:SF 2 "fp_arith_operand" "rGH")))] + "TARGET_NUMERICS" + "subr %2,%1,%0" + [(set_attr "type" "fpadd")]) + + + (define_insn "muldf3" + [(set (match_operand:DF 0 "register_operand" "=d") + (mult:DF (match_operand:DF 1 "fp_arith_operand" "rGH") + (match_operand:DF 2 "fp_arith_operand" "rGH")))] + "TARGET_NUMERICS" + "mulrl %1,%2,%0" + [(set_attr "type" "fpmul")]) + + (define_insn "mulsf3" + [(set (match_operand:SF 0 "register_operand" "=d") + (mult:SF (match_operand:SF 1 "fp_arith_operand" "rGH") + (match_operand:SF 2 "fp_arith_operand" "rGH")))] + "TARGET_NUMERICS" + "mulr %1,%2,%0" + [(set_attr "type" "fpmul")]) + + + (define_insn "divdf3" + [(set (match_operand:DF 0 "register_operand" "=d") + (div:DF (match_operand:DF 1 "fp_arith_operand" "rGH") + (match_operand:DF 2 "fp_arith_operand" "rGH")))] + "TARGET_NUMERICS" + "divrl %2,%1,%0" + [(set_attr "type" "fpdiv")]) + + (define_insn "divsf3" + [(set (match_operand:SF 0 "register_operand" "=d") + (div:SF (match_operand:SF 1 "fp_arith_operand" "rGH") + (match_operand:SF 2 "fp_arith_operand" "rGH")))] + "TARGET_NUMERICS" + "divr %2,%1,%0" + [(set_attr "type" "fpdiv")]) + + (define_insn "negdf2" + [(set (match_operand:DF 0 "register_operand" "=d,f") + (neg:DF (match_operand:DF 1 "register_operand" "d,r")))] + "" + "* + { + if (which_alternative == 0) + { + if (REGNO (operands[0]) == REGNO (operands[1])) + return \"notbit 31,%D1,%D0\"; + return \"mov %1,%0\;notbit 31,%D1,%D0\"; + } + return \"subrl %1,0f0.0,%0\"; + }" + [(set_attr "type" "fpadd")]) + + (define_insn "negsf2" + [(set (match_operand:SF 0 "register_operand" "=d,f") + (neg:SF (match_operand:SF 1 "register_operand" "d,r")))] + "" + "@ + notbit 31,%1,%0 + subr %1,0f0.0,%0" + [(set_attr "type" "fpadd")]) + + ;;; The abs patterns also work even if the target machine doesn't have + ;;; floating point, because in that case dstreg and srcreg will always be + ;;; less than 32. + + (define_insn "absdf2" + [(set (match_operand:DF 0 "register_operand" "=df") + (abs:DF (match_operand:DF 1 "register_operand" "df")))] + "" + "* + { + int dstreg = REGNO (operands[0]); + int srcreg = REGNO (operands[1]); + + if (dstreg < 32) + { + if (srcreg < 32) + { + if (dstreg != srcreg) + output_asm_insn (\"mov %1,%0\", operands); + return \"clrbit 31,%D1,%D0\"; + } + /* Src is an fp reg. */ + return \"movrl %1,%0\;clrbit 31,%D1,%D0\"; + } + if (srcreg >= 32) + return \"cpysre %1,0f0.0,%0\"; + return \"movrl %1,%0\;cpysre %0,0f0.0,%0\"; + }" + [(set_attr "type" "multi")]) + + (define_insn "abssf2" + [(set (match_operand:SF 0 "register_operand" "=df") + (abs:SF (match_operand:SF 1 "register_operand" "df")))] + "" + "* + { + int dstreg = REGNO (operands[0]); + int srcreg = REGNO (operands[1]); + + if (dstreg < 32 && srcreg < 32) + return \"clrbit 31,%1,%0\"; + + if (dstreg >= 32 && srcreg >= 32) + return \"cpysre %1,0f0.0,%0\"; + + if (dstreg < 32) + return \"movr %1,%0\;clrbit 31,%0,%0\"; + + return \"movr %1,%0\;cpysre %0,0f0.0,%0\"; + }" + [(set_attr "type" "multi")]) + + ;; Tetra (16 byte) float support. + + (define_insn "cmptf" + [(set (reg:CC 36) + (compare:CC (match_operand:TF 0 "register_operand" "f") + (match_operand:TF 1 "nonmemory_operand" "fG")))] + "TARGET_NUMERICS" + "cmpr %0,%1" + [(set_attr "type" "fpcc")]) + + (define_expand "movtf" + [(set (match_operand:TF 0 "general_operand" "") + (match_operand:TF 1 "fpmove_src_operand" ""))] + "" + " + { + if (emit_move_sequence (operands, TFmode)) + DONE; + }") + + (define_insn "" + [(set (match_operand:TF 0 "general_operand" "=r,f,d,d,m") + (match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,dG"))] + "current_function_args_size == 0 + && (register_operand (operands[0], TFmode) + || register_operand (operands[1], TFmode) + || operands[1] == CONST0_RTX (TFmode))" + "* + { + switch (which_alternative) + { + case 0: + if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) + return \"movre %1,%0\"; + else + return \"movq %1,%0\"; + case 1: + return \"movre %1,%0\"; + case 2: + return i960_output_ldconst (operands[0], operands[1]); + case 3: + return \"ldq %1,%0\"; + case 4: + if (operands[1] == CONST0_RTX (TFmode)) + return \"st g14,%0\;st g14,4(%0)\;st g14,8(%0)\;st g14,12(%0)\"; + return \"stq %1,%0\"; + } + }" + [(set_attr "type" "move,move,load,fpload,fpstore")]) + + (define_insn "" + [(set (match_operand:TF 0 "general_operand" "=r,f,d,d,m") + (match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,d"))] + "current_function_args_size != 0 + && (register_operand (operands[0], TFmode) + || register_operand (operands[1], TFmode))" + "* + { + switch (which_alternative) + { + case 0: + if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) + return \"movre %1,%0\"; + else + return \"movq %1,%0\"; + case 1: + return \"movre %1,%0\"; + case 2: + return i960_output_ldconst (operands[0], operands[1]); + case 3: + return \"ldq %1,%0\"; + case 4: + return \"stq %1,%0\"; + } + }" + [(set_attr "type" "move,move,load,fpload,fpstore")]) + + (define_insn "extendsftf2" + [(set (match_operand:TF 0 "register_operand" "=f,d") + (float_extend:TF + (match_operand:SF 1 "register_operand" "d,f")))] + "TARGET_NUMERICS" + "@ + movr %1,%0 + movre %1,%0" + [(set_attr "type" "fpmove")]) + + (define_insn "extenddftf2" + [(set (match_operand:TF 0 "register_operand" "=f,d") + (float_extend:TF + (match_operand:DF 1 "register_operand" "d,f")))] + "TARGET_NUMERICS" + "@ + movrl %1,%0 + movre %1,%0" + [(set_attr "type" "fpmove")]) + + (define_insn "trunctfdf2" + [(set (match_operand:DF 0 "register_operand" "=d") + (float_truncate:DF + (match_operand:TF 1 "register_operand" "f")))] + "TARGET_NUMERICS" + "movrl %1,%0" + [(set_attr "type" "fpmove")]) + + (define_insn "trunctfsf2" + [(set (match_operand:SF 0 "register_operand" "=d") + (float_truncate:SF + (match_operand:TF 1 "register_operand" "f")))] + "TARGET_NUMERICS" + "movr %1,%0" + [(set_attr "type" "fpmove")]) + + (define_insn "floatsitf2" + [(set (match_operand:TF 0 "register_operand" "=f") + (float:TF (match_operand:SI 1 "register_operand" "d")))] + "TARGET_NUMERICS" + "cvtir %1,%0" + [(set_attr "type" "fpcvt")]) + + (define_insn "fix_trunctfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))] + "TARGET_NUMERICS" + "cvtzri %1,%0" + [(set_attr "type" "fpcvt")]) + + (define_insn "fixuns_trunctfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (unsigned_fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))] + "TARGET_NUMERICS" + "cvtzri %1,%0" + [(set_attr "type" "fpcvt")]) + + (define_insn "addtf3" + [(set (match_operand:TF 0 "register_operand" "=f") + (plus:TF (match_operand:TF 1 "nonmemory_operand" "%fG") + (match_operand:TF 2 "nonmemory_operand" "fG")))] + "TARGET_NUMERICS" + "addr %1,%2,%0" + [(set_attr "type" "fpadd")]) + + (define_insn "subtf3" + [(set (match_operand:TF 0 "register_operand" "=f") + (minus:TF (match_operand:TF 1 "nonmemory_operand" "fG") + (match_operand:TF 2 "nonmemory_operand" "fG")))] + "TARGET_NUMERICS" + "subr %2,%1,%0" + [(set_attr "type" "fpadd")]) + + (define_insn "multf3" + [(set (match_operand:TF 0 "register_operand" "=f") + (mult:TF (match_operand:TF 1 "nonmemory_operand" "fG") + (match_operand:TF 2 "nonmemory_operand" "fG")))] + "TARGET_NUMERICS" + "mulr %1,%2,%0" + [(set_attr "type" "fpmul")]) + + (define_insn "divtf3" + [(set (match_operand:TF 0 "register_operand" "=f") + (div:TF (match_operand:TF 1 "nonmemory_operand" "fG") + (match_operand:TF 2 "nonmemory_operand" "fG")))] + "TARGET_NUMERICS" + "divr %2,%1,%0" + [(set_attr "type" "fpdiv")]) + + (define_insn "negtf2" + [(set (match_operand:TF 0 "register_operand" "=f") + (neg:TF (match_operand:TF 1 "register_operand" "f")))] + "TARGET_NUMERICS" + "subr %1,0f0.0,%0" + [(set_attr "type" "fpadd")]) + + (define_insn "abstf2" + [(set (match_operand:TF 0 "register_operand" "=f") + (abs:TF (match_operand:TF 1 "register_operand" "f")))] + "(TARGET_NUMERICS)" + "cpysre %1,0f0.0,%0" + [(set_attr "type" "fpmove")]) + + ;; Arithmetic shift instructions. + + (define_insn "ashlsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashift:SI (match_operand:SI 1 "arith_operand" "dI") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "shli %2,%1,%0" + [(set_attr "type" "alu2")]) + + (define_insn "ashrsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashiftrt:SI (match_operand:SI 1 "arith_operand" "dI") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "shri %2,%1,%0" + [(set_attr "type" "alu2")]) + + (define_insn "lshrsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (lshiftrt:SI (match_operand:SI 1 "arith_operand" "dI") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "shro %2,%1,%0" + [(set_attr "type" "alu2")]) + + ;; Unconditional and other jump instructions. + + (define_insn "jump" + [(set (pc) + (label_ref (match_operand 0 "" "")))] + "" + "b %l0" + [(set_attr "type" "branch")]) + + (define_insn "indirect_jump" + [(set (pc) (match_operand:SI 0 "register_operand" "r"))] + "" + "b* %0" + [(set_attr "type" "branch")]) + + (define_insn "tablejump" + [(set (pc) (match_operand:SI 0 "register_operand" "d")) + (use (label_ref (match_operand 1 "" "")))] + "" + "bx (%0)" + [(set_attr "type" "branch")]) + + ;;- jump to subroutine + + (define_expand "call" + [(call (match_operand:SI 0 "general_operand" "") + (match_operand:SI 1 "immediate_operand" ""))] + "" + " + { + i960_expand_call (operand0, operand1, 0); + DONE; + }") + + (define_insn "" + [(call (match_operand:SI 0 "general_operand" "g") + (match_operand:SI 1 "immediate_operand" "i"))] + "" + "* return i960_output_call_insn (operands[0], operands[1], insn);" + [(set_attr "type" "call")]) + + (define_expand "call_value" + [(set (match_operand 0 "register_operand" "=d") + (call (match_operand:SI 1 "general_operand" "g") + (match_operand:SI 2 "immediate_operand" "i")))] + "" + " + { + i960_expand_call (operand1, operand2, operand0); + DONE; + }") + + (define_insn "" + [(set (match_operand 0 "register_operand" "=d") + (call (match_operand:SI 1 "general_operand" "g") + (match_operand:SI 2 "immediate_operand" "i")))] + "" + "* return i960_output_call_insn (operands[1], operands[2], insn);" + [(set_attr "type" "call")]) + + (define_insn "return" + [(return)] + "" + "* return i960_output_ret_insn (insn);" + [(set_attr "type" "branch")]) + + (define_insn "nop" + [(const_int 0)] + "" + "") + + ;; Various peephole optimizations for multiple-word moves, loads, and stores. + ;; Multiple register moves. + + ;; Matched 5/28/91 + (define_peephole + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:SI 1 "register_operand" "r")) + (set (match_operand:SI 2 "register_operand" "=r") + (match_operand:SI 3 "register_operand" "r")) + (set (match_operand:SI 4 "register_operand" "=r") + (match_operand:SI 5 "register_operand" "r")) + (set (match_operand:SI 6 "register_operand" "=r") + (match_operand:SI 7 "register_operand" "r"))] + "((REGNO (operands[0]) & 3) == 0) + && ((REGNO (operands[1]) & 3) == 0) + && (REGNO (operands[0]) + 1 == REGNO (operands[2])) + && (REGNO (operands[1]) + 1 == REGNO (operands[3])) + && (REGNO (operands[0]) + 2 == REGNO (operands[4])) + && (REGNO (operands[1]) + 2 == REGNO (operands[5])) + && (REGNO (operands[0]) + 3 == REGNO (operands[6])) + && (REGNO (operands[1]) + 3 == REGNO (operands[7]))" + "movq %1,%0") + + ;; Matched 4/17/92 + (define_peephole + [(set (match_operand:DI 0 "register_operand" "=r") + (match_operand:DI 1 "register_operand" "r")) + (set (match_operand:DI 2 "register_operand" "=r") + (match_operand:DI 3 "register_operand" "r"))] + "((REGNO (operands[0]) & 3) == 0) + && ((REGNO (operands[1]) & 3) == 0) + && (REGNO (operands[0]) + 2 == REGNO (operands[2])) + && (REGNO (operands[1]) + 2 == REGNO (operands[3]))" + "movq %1,%0") + + ;; Matched 4/17/92 + (define_peephole + [(set (match_operand:DI 0 "register_operand" "=r") + (match_operand:DI 1 "register_operand" "r")) + (set (match_operand:SI 2 "register_operand" "=r") + (match_operand:SI 3 "register_operand" "r")) + (set (match_operand:SI 4 "register_operand" "=r") + (match_operand:SI 5 "register_operand" "r"))] + "((REGNO (operands[0]) & 3) == 0) + && ((REGNO (operands[1]) & 3) == 0) + && (REGNO (operands[0]) + 2 == REGNO (operands[2])) + && (REGNO (operands[1]) + 2 == REGNO (operands[3])) + && (REGNO (operands[0]) + 3 == REGNO (operands[4])) + && (REGNO (operands[1]) + 3 == REGNO (operands[5]))" + "movq %1,%0") + + ;; Matched 4/17/92 + (define_peephole + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:SI 1 "register_operand" "r")) + (set (match_operand:SI 2 "register_operand" "=r") + (match_operand:SI 3 "register_operand" "r")) + (set (match_operand:DI 4 "register_operand" "=r") + (match_operand:DI 5 "register_operand" "r"))] + "((REGNO (operands[0]) & 3) == 0) + && ((REGNO (operands[1]) & 3) == 0) + && (REGNO (operands[0]) + 1 == REGNO (operands[2])) + && (REGNO (operands[1]) + 1 == REGNO (operands[3])) + && (REGNO (operands[0]) + 2 == REGNO (operands[4])) + && (REGNO (operands[1]) + 2 == REGNO (operands[5]))" + "movq %1,%0") + + ;; Matched 4/17/92 + (define_peephole + [(set (match_operand:DI 0 "register_operand" "=r") + (match_operand:DI 1 "register_operand" "r")) + (set (match_operand:SI 2 "register_operand" "=r") + (match_operand:SI 3 "register_operand" "r"))] + "((REGNO (operands[0]) & 3) == 0) + && ((REGNO (operands[1]) & 3) == 0) + && (REGNO (operands[0]) + 2 == REGNO (operands[2])) + && (REGNO (operands[1]) + 2 == REGNO (operands[3]))" + "movt %1,%0") + + ;; Matched 5/28/91 + (define_peephole + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:SI 1 "register_operand" "r")) + (set (match_operand:SI 2 "register_operand" "=r") + (match_operand:SI 3 "register_operand" "r")) + (set (match_operand:SI 4 "register_operand" "=r") + (match_operand:SI 5 "register_operand" "r"))] + "((REGNO (operands[0]) & 3) == 0) + && ((REGNO (operands[1]) & 3) == 0) + && (REGNO (operands[0]) + 1 == REGNO (operands[2])) + && (REGNO (operands[1]) + 1 == REGNO (operands[3])) + && (REGNO (operands[0]) + 2 == REGNO (operands[4])) + && (REGNO (operands[1]) + 2 == REGNO (operands[5]))" + "movt %1,%0") + + ;; Matched 5/28/91 + (define_peephole + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:SI 1 "register_operand" "r")) + (set (match_operand:SI 2 "register_operand" "=r") + (match_operand:SI 3 "register_operand" "r"))] + "((REGNO (operands[0]) & 1) == 0) + && ((REGNO (operands[1]) & 1) == 0) + && (REGNO (operands[0]) + 1 == REGNO (operands[2])) + && (REGNO (operands[1]) + 1 == REGNO (operands[3]))" + "movl %1,%0") + + ; Multiple register loads. + + ;; Matched 6/15/91 + (define_peephole + [(set (match_operand:SI 0 "register_operand" "=r") + (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "immediate_operand" "n")))) + (set (match_operand:SI 3 "register_operand" "=r") + (mem:SI (plus:SI (match_dup 1) + (match_operand:SI 4 "immediate_operand" "n")))) + (set (match_operand:SI 5 "register_operand" "=r") + (mem:SI (plus:SI (match_dup 1) + (match_operand:SI 6 "immediate_operand" "n")))) + (set (match_operand:SI 7 "register_operand" "=r") + (mem:SI (plus:SI (match_dup 1) + (match_operand:SI 8 "immediate_operand" "n"))))] + "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) + && (REGNO (operands[1]) != REGNO (operands[0])) + && (REGNO (operands[0]) + 1 == REGNO (operands[3])) + && (REGNO (operands[1]) != REGNO (operands[3])) + && (REGNO (operands[0]) + 2 == REGNO (operands[5])) + && (REGNO (operands[1]) != REGNO (operands[5])) + && (REGNO (operands[0]) + 3 == REGNO (operands[7])) + && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])) + && (INTVAL (operands[2]) + 8 == INTVAL (operands[6])) + && (INTVAL (operands[2]) + 12 == INTVAL (operands[8])))" + "ldq %2(%1),%0") + + ;; Matched 5/28/91 + (define_peephole + [(set (match_operand:DF 0 "register_operand" "=d") + (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "n")))) + (set (match_operand:DF 3 "register_operand" "=d") + (mem:DF (plus:SI (match_dup 1) + (match_operand:SI 4 "immediate_operand" "n"))))] + "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) + && (REGNO (operands[1]) != REGNO (operands[0])) + && (REGNO (operands[0]) + 2 == REGNO (operands[3])) + && (REGNO (operands[1]) != REGNO (operands[3])) + && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))" + "ldq %2(%1),%0") + + ;; Matched 1/24/92 + (define_peephole + [(set (match_operand:DI 0 "register_operand" "=d") + (mem:DI (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "n")))) + (set (match_operand:DI 3 "register_operand" "=d") + (mem:DI (plus:SI (match_dup 1) + (match_operand:SI 4 "immediate_operand" "n"))))] + "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) + && (REGNO (operands[1]) != REGNO (operands[0])) + && (REGNO (operands[0]) + 2 == REGNO (operands[3])) + && (REGNO (operands[1]) != REGNO (operands[3])) + && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))" + "ldq %2(%1),%0") + + ;; Matched 4/17/92 + (define_peephole + [(set (match_operand:SI 0 "register_operand" "=d") + (mem:SI (match_operand:SI 1 "register_operand" "d"))) + (set (match_operand:SI 2 "register_operand" "=d") + (mem:SI (plus:SI (match_dup 1) + (match_operand:SI 3 "immediate_operand" "n")))) + (set (match_operand:SI 4 "register_operand" "=d") + (mem:SI (plus:SI (match_dup 1) + (match_operand:SI 5 "immediate_operand" "n")))) + (set (match_operand:SI 6 "register_operand" "=d") + (mem:SI (plus:SI (match_dup 1) + (match_operand:SI 7 "immediate_operand" "n"))))] + "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0) + && (REGNO (operands[1]) != REGNO (operands[0])) + && (REGNO (operands[0]) + 1 == REGNO (operands[2])) + && (REGNO (operands[1]) != REGNO (operands[2])) + && (REGNO (operands[0]) + 2 == REGNO (operands[4])) + && (REGNO (operands[1]) != REGNO (operands[4])) + && (REGNO (operands[0]) + 3 == REGNO (operands[6])) + && (INTVAL (operands[3]) == 4) + && (INTVAL (operands[5]) == 8) + && (INTVAL (operands[7]) == 12))" + "ldq (%1),%0") + + ;; Matched 5/28/91 + (define_peephole + [(set (match_operand:SI 0 "register_operand" "=d") + (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "n")))) + (set (match_operand:SI 3 "register_operand" "=d") + (mem:SI (plus:SI (match_dup 1) + (match_operand:SI 4 "immediate_operand" "n")))) + (set (match_operand:SI 5 "register_operand" "=d") + (mem:SI (plus:SI (match_dup 1) + (match_operand:SI 6 "immediate_operand" "n"))))] + "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) + && (REGNO (operands[1]) != REGNO (operands[0])) + && (REGNO (operands[0]) + 1 == REGNO (operands[3])) + && (REGNO (operands[1]) != REGNO (operands[3])) + && (REGNO (operands[0]) + 2 == REGNO (operands[5])) + && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])) + && (INTVAL (operands[2]) + 8 == INTVAL (operands[6])))" + "ldt %2(%1),%0") + + ;; Matched 6/15/91 + (define_peephole + [(set (match_operand:SI 0 "register_operand" "=d") + (mem:SI (match_operand:SI 1 "register_operand" "d"))) + (set (match_operand:SI 2 "register_operand" "=d") + (mem:SI (plus:SI (match_dup 1) + (match_operand:SI 3 "immediate_operand" "n")))) + (set (match_operand:SI 4 "register_operand" "=d") + (mem:SI (plus:SI (match_dup 1) + (match_operand:SI 5 "immediate_operand" "n"))))] + "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0) + && (REGNO (operands[1]) != REGNO (operands[0])) + && (REGNO (operands[0]) + 1 == REGNO (operands[2])) + && (REGNO (operands[1]) != REGNO (operands[2])) + && (REGNO (operands[0]) + 2 == REGNO (operands[4])) + && (INTVAL (operands[3]) == 4) + && (INTVAL (operands[5]) == 8))" + "ldt (%1),%0") + + ;; Matched 5/28/91 + (define_peephole + [(set (match_operand:SI 0 "register_operand" "=d") + (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "n")))) + (set (match_operand:SI 3 "register_operand" "=d") + (mem:SI (plus:SI (match_dup 1) + (match_operand:SI 4 "immediate_operand" "n"))))] + "(i960_si_di (operands[1], operands[2]) && ((REGNO (operands[0]) & 1) == 0) + && (REGNO (operands[1]) != REGNO (operands[0])) + && (REGNO (operands[0]) + 1 == REGNO (operands[3])) + && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])))" + "ldl %2(%1),%0") + + ;; Matched 5/28/91 + (define_peephole + [(set (match_operand:SI 0 "register_operand" "=d") + (mem:SI (match_operand:SI 1 "register_operand" "d"))) + (set (match_operand:SI 2 "register_operand" "=d") + (mem:SI (plus:SI (match_dup 1) + (match_operand:SI 3 "immediate_operand" "n"))))] + "(i960_si_di (operands[1], 0) && ((REGNO (operands[0]) & 1) == 0) + && (REGNO (operands[1]) != REGNO (operands[0])) + && (REGNO (operands[0]) + 1 == REGNO (operands[2])) + && (INTVAL (operands[3]) == 4))" + "ldl (%1),%0") + + ; Multiple register stores. + + ;; Matched 5/28/91 + (define_peephole + [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d") + (match_operand:SI 1 "immediate_operand" "n"))) + (match_operand:SI 2 "register_operand" "d")) + (set (mem:SI (plus:SI (match_dup 0) + (match_operand:SI 3 "immediate_operand" "n"))) + (match_operand:SI 4 "register_operand" "d")) + (set (mem:SI (plus:SI (match_dup 0) + (match_operand:SI 5 "immediate_operand" "n"))) + (match_operand:SI 6 "register_operand" "d")) + (set (mem:SI (plus:SI (match_dup 0) + (match_operand:SI 7 "immediate_operand" "n"))) + (match_operand:SI 8 "register_operand" "d"))] + "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) + && (REGNO (operands[2]) + 1 == REGNO (operands[4])) + && (REGNO (operands[2]) + 2 == REGNO (operands[6])) + && (REGNO (operands[2]) + 3 == REGNO (operands[8])) + && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])) + && (INTVAL (operands[1]) + 8 == INTVAL (operands[5])) + && (INTVAL (operands[1]) + 12 == INTVAL (operands[7])))" + "stq %2,%1(%0)") + + ;; Matched 6/16/91 + (define_peephole + [(set (mem:DF (plus:SI (match_operand:SI 0 "register_operand" "d") + (match_operand:SI 1 "immediate_operand" "n"))) + (match_operand:DF 2 "register_operand" "d")) + (set (mem:DF (plus:SI (match_dup 0) + (match_operand:SI 3 "immediate_operand" "n"))) + (match_operand:DF 4 "register_operand" "d"))] + "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) + && (REGNO (operands[2]) + 2 == REGNO (operands[4])) + && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))" + "stq %2,%1(%0)") + + ;; Matched 4/17/92 + (define_peephole + [(set (mem:DI (plus:SI (match_operand:SI 0 "register_operand" "d") + (match_operand:SI 1 "immediate_operand" "n"))) + (match_operand:DI 2 "register_operand" "d")) + (set (mem:DI (plus:SI (match_dup 0) + (match_operand:SI 3 "immediate_operand" "n"))) + (match_operand:DI 4 "register_operand" "d"))] + "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) + && (REGNO (operands[2]) + 2 == REGNO (operands[4])) + && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))" + "stq %2,%1(%0)") + + ;; Matched 1/23/92 + (define_peephole + [(set (mem:SI (match_operand:SI 0 "register_operand" "d")) + (match_operand:SI 1 "register_operand" "d")) + (set (mem:SI (plus:SI (match_dup 0) + (match_operand:SI 2 "immediate_operand" "n"))) + (match_operand:SI 3 "register_operand" "d")) + (set (mem:SI (plus:SI (match_dup 0) + (match_operand:SI 4 "immediate_operand" "n"))) + (match_operand:SI 5 "register_operand" "d")) + (set (mem:SI (plus:SI (match_dup 0) + (match_operand:SI 6 "immediate_operand" "n"))) + (match_operand:SI 7 "register_operand" "d"))] + "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0) + && (REGNO (operands[1]) + 1 == REGNO (operands[3])) + && (REGNO (operands[1]) + 2 == REGNO (operands[5])) + && (REGNO (operands[1]) + 3 == REGNO (operands[7])) + && (INTVAL (operands[2]) == 4) + && (INTVAL (operands[4]) == 8) + && (INTVAL (operands[6]) == 12))" + "stq %1,(%0)") + + ;; Matched 5/29/91 + (define_peephole + [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d") + (match_operand:SI 1 "immediate_operand" "n"))) + (match_operand:SI 2 "register_operand" "d")) + (set (mem:SI (plus:SI (match_dup 0) + (match_operand:SI 3 "immediate_operand" "n"))) + (match_operand:SI 4 "register_operand" "d")) + (set (mem:SI (plus:SI (match_dup 0) + (match_operand:SI 5 "immediate_operand" "n"))) + (match_operand:SI 6 "register_operand" "d"))] + "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) + && (REGNO (operands[2]) + 1 == REGNO (operands[4])) + && (REGNO (operands[2]) + 2 == REGNO (operands[6])) + && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])) + && (INTVAL (operands[1]) + 8 == INTVAL (operands[5])))" + "stt %2,%1(%0)") + + ;; Matched 5/29/91 + (define_peephole + [(set (mem:SI (match_operand:SI 0 "register_operand" "d")) + (match_operand:SI 1 "register_operand" "d")) + (set (mem:SI (plus:SI (match_dup 0) + (match_operand:SI 2 "immediate_operand" "n"))) + (match_operand:SI 3 "register_operand" "d")) + (set (mem:SI (plus:SI (match_dup 0) + (match_operand:SI 4 "immediate_operand" "n"))) + (match_operand:SI 5 "register_operand" "d"))] + "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0) + && (REGNO (operands[1]) + 1 == REGNO (operands[3])) + && (REGNO (operands[1]) + 2 == REGNO (operands[5])) + && (INTVAL (operands[2]) == 4) + && (INTVAL (operands[4]) == 8))" + "stt %1,(%0)") + + ;; Matched 5/28/91 + (define_peephole + [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d") + (match_operand:SI 1 "immediate_operand" "n"))) + (match_operand:SI 2 "register_operand" "d")) + (set (mem:SI (plus:SI (match_dup 0) + (match_operand:SI 3 "immediate_operand" "n"))) + (match_operand:SI 4 "register_operand" "d"))] + "(i960_si_di (operands[0], operands[1]) && ((REGNO (operands[2]) & 1) == 0) + && (REGNO (operands[2]) + 1 == REGNO (operands[4])) + && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])))" + "stl %2,%1(%0)") + + ;; Matched 5/28/91 + (define_peephole + [(set (mem:SI (match_operand:SI 0 "register_operand" "d")) + (match_operand:SI 1 "register_operand" "d")) + (set (mem:SI (plus:SI (match_dup 0) + (match_operand:SI 2 "immediate_operand" "n"))) + (match_operand:SI 3 "register_operand" "d"))] + "(i960_si_di (operands[0], 0) && ((REGNO (operands[1]) & 1) == 0) + && (REGNO (operands[1]) + 1 == REGNO (operands[3])) + && (INTVAL (operands[2]) == 4))" + "stl %1,(%0)") + + ;;- Local variables: + ;;- mode:emacs-lisp + ;;- comment-start: ";;- " + ;;- eval: (set-syntax-table (copy-sequence (syntax-table))) + ;;- eval: (modify-syntax-entry ?[ "(]") + ;;- eval: (modify-syntax-entry ?] ")[") + ;;- eval: (modify-syntax-entry ?{ "(}") + ;;- eval: (modify-syntax-entry ?} "){") + ;;- End: diff -rc2N gcc-2.1/config/iris.h gcc-2.2.1/config/iris.h *** gcc-2.1/config/iris.h Sat Mar 21 18:29:03 1992 --- gcc-2.2.1/config/iris.h Mon May 18 23:01:34 1992 *************** *** 85,87 **** --- 85,99 ---- #define NO_DOLLAR_IN_LABEL 1 + /* Specify size_t, ptrdiff_t, and wchar_t types. */ + #define SIZE_TYPE "unsigned int" + #define PTRDIFF_TYPE "int" + #define WCHAR_TYPE "unsigned char" + #define WCHAR_TYPE_SIZE BITS_PER_UNIT + + /* Generate calls to memcpy, etc., not bcopy, etc. */ + #define TARGET_MEM_FUNCTIONS + + /* Plain char is unsigned in the SGI compiler. */ + #define DEFAULT_SIGNED_CHAR 0 + #include "mips.h" diff -rc2N gcc-2.1/config/iris4.h gcc-2.2.1/config/iris4.h *** gcc-2.1/config/iris4.h --- gcc-2.2.1/config/iris4.h Fri Apr 10 15:44:26 1992 *************** *** 0 **** --- 1,24 ---- + /* Definitions of target machine for GNU compiler. Iris version 4. + Copyright (C) 1991 Free Software Foundation, Inc. + + This file is part of GNU CC. + + GNU CC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GNU CC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GNU CC; see the file COPYING. If not, write to + the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + /* Use atexit for static constructors/destructors, instead of defining + our own exit function. */ + #define HAVE_ATEXIT + + #include "iris.h" diff -rc2N gcc-2.1/config/m68k.h gcc-2.2.1/config/m68k.h *** gcc-2.1/config/m68k.h Fri Mar 20 14:17:48 1992 --- gcc-2.2.1/config/m68k.h Sun Apr 19 17:22:51 1992 *************** *** 913,918 **** /* On the 68k, the trampoline looks like this: mov @#.,a0 ! jsr @#__trampoline ! jsr @#__trampoline .long STATIC .long FUNCTION --- 913,918 ---- /* On the 68k, the trampoline looks like this: mov @#.,a0 ! jsr @#___trampoline ! jsr @#___trampoline .long STATIC .long FUNCTION *************** *** 919,924 **** The reason for having three jsr insns is so that an entire line of the instruction cache is filled in a predictable way ! that will always be the same. */ #define TRAMPOLINE_TEMPLATE(FILE) \ { \ --- 919,927 ---- The reason for having three jsr insns is so that an entire line of the instruction cache is filled in a predictable way ! that will always be the same. + We always use the assembler label ___trampoline + regardless of whether the system adds underscores. */ + #define TRAMPOLINE_TEMPLATE(FILE) \ { \ *************** *** 926,933 **** ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ! ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4ef9)); \ ! ASM_OUTPUT_INT (FILE, gen_rtx (SYMBOL_REF, SImode, "__trampoline")); \ ! ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4ef9)); \ ! ASM_OUTPUT_INT (FILE, gen_rtx (SYMBOL_REF, SImode, "__trampoline")); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ --- 929,936 ---- ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ! ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4eb9)); \ ! ASM_OUTPUT_INT (FILE, gen_rtx (SYMBOL_REF, SImode, "*___trampoline"));\ ! ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4eb9)); \ ! ASM_OUTPUT_INT (FILE, gen_rtx (SYMBOL_REF, SImode, "*___trampoline"));\ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ *************** *** 970,973 **** --- 973,977 ---- { \ register char *a0 asm ("%a0"); \ + asm (GLOBAL_ASM_OP " ___trampoline"); \ asm ("___trampoline:"); \ asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ *************** *** 1282,1286 **** return it with a return statement. Otherwise, break from the switch. */ ! #define CONST_COSTS(RTX,CODE) \ case CONST_INT: \ /* Constant zero is super cheap due to clr instruction. */ \ --- 1286,1290 ---- return it with a return statement. Otherwise, break from the switch. */ ! #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ /* Constant zero is super cheap due to clr instruction. */ \ *************** *** 1290,1294 **** /* Constants between -136 and 254 are easily generated */ \ /* by intelligent uses of moveq, add[q], and subq */ \ ! if (INTVAL (RTX) >= -136 && INTVAL (RTX) <= 254) return 2; \ case CONST: \ case LABEL_REF: \ --- 1294,1299 ---- /* Constants between -136 and 254 are easily generated */ \ /* by intelligent uses of moveq, add[q], and subq */ \ ! if ((OUTER_CODE) == SET && INTVAL (RTX) >= -136 \ ! && INTVAL (RTX) <= 254) return 2; \ case CONST: \ case LABEL_REF: \ *************** *** 1304,1309 **** relative to an average of the time for add and the time for shift, taking away a little more because sometimes move insns are needed. */ ! #define RTX_COSTS(X,CODE) \ case PLUS: \ /* An lea costs about three times as much as a simple add. */ \ --- 1309,1316 ---- relative to an average of the time for add and the time for shift, taking away a little more because sometimes move insns are needed. */ + #define MULL_COST (TARGET_68040 ? 5 : 13) + #define MULW_COST (TARGET_68040 ? 3 : 8) ! #define RTX_COSTS(X,CODE,OUTER_CODE) \ case PLUS: \ /* An lea costs about three times as much as a simple add. */ \ *************** *** 1346,1352 **** } \ else if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ ! return COSTS_N_INSNS (8); /* mul.w */ \ else \ ! return COSTS_N_INSNS (13); /* mul.l */ \ break; \ case DIV: \ --- 1353,1359 ---- } \ else if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ ! return COSTS_N_INSNS (MULW_COST); \ else \ ! return COSTS_N_INSNS (MULL_COST); \ break; \ case DIV: \ *************** *** 1474,1479 **** defined for reference from other files. */ #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ ! do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) /* This is how to output a reference to a user-level label named NAME. --- 1481,1489 ---- defined for reference from other files. */ + #define GLOBAL_ASM_OP ".globl" #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ ! do { fprintf (FILE, "%s ", GLOBAL_ASM_OP); \ ! assemble_name (FILE, NAME); \ ! fputs ("\n", FILE);} while (0) /* This is how to output a reference to a user-level label named NAME. *************** *** 1520,1524 **** } while (0) ! #endif /* not CROSS_COMPILER */ /* This is how to output an assembler line defining an `int' constant. */ --- 1530,1534 ---- } while (0) ! #endif /* not CROSS_COMPILE */ /* This is how to output an assembler line defining an `int' constant. */ *************** *** 1674,1678 **** #endif ! #ifdef CROSS_COMPILER #define PRINT_OPERAND_PRINT_FLOAT(CODE, FILE) \ ASM_OUTPUT_FLOAT_OPERAND (FILE, u1.f); --- 1684,1688 ---- #endif ! #ifdef CROSS_COMPILE #define PRINT_OPERAND_PRINT_FLOAT(CODE, FILE) \ ASM_OUTPUT_FLOAT_OPERAND (FILE, u1.f); diff -rc2N gcc-2.1/config/m68k.md gcc-2.2.1/config/m68k.md *** gcc-2.1/config/m68k.md Fri Mar 20 14:17:44 1992 --- gcc-2.2.1/config/m68k.md Tue May 19 20:27:34 1992 *************** *** 395,399 **** return \"cmp%.l %d1,%d0\"; #else ! return \"cmp%.l %d0,%d1\"; #endif } --- 395,399 ---- return \"cmp%.l %d1,%d0\"; #else ! return \"cmp%.l %d0,%d1\"; #endif } *************** *** 420,424 **** return \"cmp%.w %d1,%d0\"; #else ! return \"cmp%.w %d0,%d1\"; #endif } --- 420,424 ---- return \"cmp%.w %d1,%d0\"; #else ! return \"cmp%.w %d0,%d1\"; #endif } *************** *** 760,766 **** operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); #if defined(MOTOROLA) && !defined(CRDS) ! return \"moveq%.l %1,%0;addq%.w %#8,%0\"; #else ! return \"moveq %1,%0;addq%.w %#8,%0\"; #endif } --- 760,766 ---- operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); #if defined(MOTOROLA) && !defined(CRDS) ! return \"moveq%.l %1,%0\;addq%.w %#8,%0\"; #else ! return \"moveq %1,%0\;addq%.w %#8,%0\"; #endif } *************** *** 787,793 **** operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) / 2); #if defined(MOTOROLA) && !defined(CRDS) ! return \"moveq%.l %1,%0;add%.w %0,%0\"; #else ! return \"moveq %1,%0;add%.w %0,%0\"; #endif } --- 787,793 ---- operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) / 2); #if defined(MOTOROLA) && !defined(CRDS) ! return \"moveq%.l %1,%0\;add%.w %0,%0\"; #else ! return \"moveq %1,%0\;add%.w %0,%0\"; #endif } *************** *** 873,879 **** ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\", CODE_LABEL_NUMBER (XEXP (labelref, 0))); ! /* For sake of 3b1, set flag saying we need to define the symbol ! LD%n (with value L%n-LI%n) at the end of the switch table. */ ! RTX_INTEGRATED_P (next_real_insn (XEXP (labelref, 0))) = 1; #endif /* SGS_SWITCH_TABLES or not MOTOROLA */ } --- 873,881 ---- ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\", CODE_LABEL_NUMBER (XEXP (labelref, 0))); ! #ifdef SGS_SWITCH_TABLES ! /* Set flag saying we need to define the symbol ! LD%n (with value L%n-LI%n) at the end of the switch table. */ ! switch_table_difference_label_flag = 1; ! #endif /* SGS_SWITCH_TABLES */ #endif /* SGS_SWITCH_TABLES or not MOTOROLA */ } *************** *** 1266,1274 **** ;; Patterns to recognize zero-extend insns produced by the combiner. ;; We don't allow both operands in memory, because of aliasing problems. (define_insn "" [(set (match_operand:SI 0 "general_operand" "=do<>,d<") ! (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rn,m")))] ! "" "* { --- 1268,1278 ---- ;; Patterns to recognize zero-extend insns produced by the combiner. ;; We don't allow both operands in memory, because of aliasing problems. + ;; Explicitly disallow two memory operands via the condition since reloading + ;; of this case will result in worse code than the uncombined patterns. (define_insn "" [(set (match_operand:SI 0 "general_operand" "=do<>,d<") ! (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] ! "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" "* { *************** *** 1298,1303 **** (define_insn "" [(set (match_operand:HI 0 "general_operand" "=do<>,d") ! (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "dn,m")))] ! "" "* { --- 1302,1307 ---- (define_insn "" [(set (match_operand:HI 0 "general_operand" "=do<>,d") ! (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] ! "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" "* { *************** *** 1338,1343 **** (define_insn "" [(set (match_operand:SI 0 "general_operand" "=do<>,d") ! (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "dn,m")))] ! "" "* { --- 1342,1347 ---- (define_insn "" [(set (match_operand:SI 0 "general_operand" "=do<>,d") ! (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] ! "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" "* { *************** *** 1392,1396 **** [(set (match_operand:SI 0 "general_operand" "=*d,a") (sign_extend:SI ! (match_operand:HI 1 "nonimmediate_operand" "0,rmn")))] "" "* --- 1396,1400 ---- [(set (match_operand:SI 0 "general_operand" "=*d,a") (sign_extend:SI ! (match_operand:HI 1 "nonimmediate_operand" "0,rm")))] "" "* *************** *** 1756,1760 **** { operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); ! return \"addq%.w %#8,%0; addq%.w %2,%0\"; } if (INTVAL (operands[2]) < -8 --- 1760,1764 ---- { operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); ! return \"addq%.w %#8,%0\;addq%.w %2,%0\"; } if (INTVAL (operands[2]) < -8 *************** *** 1765,1769 **** operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]) - 8); ! return \"subq%.w %#8,%0; subq%.w %2,%0\"; } #endif --- 1769,1773 ---- operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]) - 8); ! return \"subq%.w %#8,%0\;subq%.w %2,%0\"; } #endif *************** *** 1814,1818 **** } /* On everything except the 68000 it is faster to use two ! addqw insttuctions to add a small integer (8 < N <= 16) to an address register. Likewise for subqw. */ if (INTVAL (operands[2]) > 8 --- 1818,1822 ---- } /* On everything except the 68000 it is faster to use two ! addqw instructions to add a small integer (8 < N <= 16) to an address register. Likewise for subqw. */ if (INTVAL (operands[2]) > 8 *************** *** 1822,1826 **** { operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); ! return \"addq%.w %#8,%0; addq%.w %2,%0\"; } if (INTVAL (operands[2]) < -8 --- 1826,1830 ---- { operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); ! return \"addq%.w %#8,%0\;addq%.w %2,%0\"; } if (INTVAL (operands[2]) < -8 *************** *** 1831,1835 **** operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]) - 8); ! return \"subq%.w %#8,%0; subq%.w %2,%0\"; } } --- 1835,1839 ---- operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]) - 8); ! return \"subq%.w %#8,%0\;subq%.w %2,%0\"; } } *************** *** 1874,1878 **** } /* On everything except the 68000 it is faster to use two ! addqw instuctions to add a small integer (8 < N <= 16) to an address register. Likewise for subqw. */ if (INTVAL (operands[1]) > 8 --- 1878,1882 ---- } /* On everything except the 68000 it is faster to use two ! addqw instructions to add a small integer (8 < N <= 16) to an address register. Likewise for subqw. */ if (INTVAL (operands[1]) > 8 *************** *** 1882,1886 **** { operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); ! return \"addq%.w %#8,%0; addq%.w %1,%0\"; } if (INTVAL (operands[1]) < -8 --- 1886,1890 ---- { operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); ! return \"addq%.w %#8,%0\;addq%.w %1,%0\"; } if (INTVAL (operands[1]) < -8 *************** *** 1891,1895 **** operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]) - 8); ! return \"subq%.w %#8,%0; subq%.w %1,%0\"; } } --- 1895,1899 ---- operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]) - 8); ! return \"subq%.w %#8,%0\;subq%.w %1,%0\"; } } *************** *** 1928,1932 **** } /* On everything except the 68000 it is faster to use two ! addqw instuctions to add a small integer (8 < N <= 16) to an address register. Likewise for subqw. */ if (INTVAL (operands[1]) > 8 --- 1932,1936 ---- } /* On everything except the 68000 it is faster to use two ! addqw instructions to add a small integer (8 < N <= 16) to an address register. Likewise for subqw. */ if (INTVAL (operands[1]) > 8 *************** *** 1936,1940 **** { operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); ! return \"addq%.w %#8,%0; addq%.w %1,%0\"; } if (INTVAL (operands[1]) < -8 --- 1940,1944 ---- { operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); ! return \"addq%.w %#8,%0\;addq%.w %1,%0\"; } if (INTVAL (operands[1]) < -8 *************** *** 1945,1949 **** operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]) - 8); ! return \"subq%.w %#8,%0; subq%.w %1,%0\"; } } --- 1949,1953 ---- operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]) - 8); ! return \"subq%.w %#8,%0\;subq%.w %1,%0\"; } } *************** *** 2155,2159 **** { operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); ! return \"subq%.w %#8,%0; subq%.w %2,%0\"; } #endif --- 2159,2163 ---- { operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); ! return \"subq%.w %#8,%0\;subq%.w %2,%0\"; } #endif *************** *** 2170,2174 **** (minus:SI (match_operand:SI 1 "general_operand" "0") (sign_extend:SI ! (match_operand:HI 2 "nonimmediate_operand" "rmn"))))] "" "sub%.w %2,%0") --- 2174,2178 ---- (minus:SI (match_operand:SI 1 "general_operand" "0") (sign_extend:SI ! (match_operand:HI 2 "nonimmediate_operand" "rm"))))] "" "sub%.w %2,%0") *************** *** 2293,2297 **** (match_operand:HI 1 "nonimmediate_operand" "%0")) (sign_extend:SI ! (match_operand:HI 2 "nonimmediate_operand" "dmn"))))] "" "* --- 2297,2301 ---- (match_operand:HI 1 "nonimmediate_operand" "%0")) (sign_extend:SI ! (match_operand:HI 2 "nonimmediate_operand" "dm"))))] "" "* *************** *** 2331,2335 **** (match_operand:HI 1 "nonimmediate_operand" "%0")) (zero_extend:SI ! (match_operand:HI 2 "nonimmediate_operand" "dmn"))))] "" "* --- 2335,2339 ---- (match_operand:HI 1 "nonimmediate_operand" "%0")) (zero_extend:SI ! (match_operand:HI 2 "nonimmediate_operand" "dm"))))] "" "* *************** *** 2367,2371 **** (match_operand:SI 1 "register_operand" "")) (zero_extend:DI ! (match_operand:SI 2 "general_operand" ""))) 1)) (set (subreg:SI (match_dup 0) 0) (subreg:SI --- 2371,2375 ---- (match_operand:SI 1 "register_operand" "")) (zero_extend:DI ! (match_operand:SI 2 "nonimmediate_operand" ""))) 1)) (set (subreg:SI (match_dup 0) 0) (subreg:SI *************** *** 2383,2387 **** (match_operand:SI 1 "register_operand" "%0")) (zero_extend:DI ! (match_operand:SI 2 "general_operand" "dmsK"))) 1)) (set (match_operand:SI 3 "register_operand" "=d") (subreg:SI --- 2387,2391 ---- (match_operand:SI 1 "register_operand" "%0")) (zero_extend:DI ! (match_operand:SI 2 "nonimmediate_operand" "dm"))) 1)) (set (match_operand:SI 3 "register_operand" "=d") (subreg:SI *************** *** 2393,2396 **** --- 2397,2416 ---- "mulu%.l %2,%3:%0") + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (subreg:SI + (mult:DI (zero_extend:DI + (match_operand:SI 1 "register_operand" "%0")) + (match_operand:SI 2 "immediate_operand" "sK")) 1)) + (set (match_operand:SI 3 "register_operand" "=d") + (subreg:SI + (mult:DI (zero_extend:DI + (match_dup 1)) + (match_dup 2)) 0))] + "TARGET_68020 + && (GET_CODE (operands[2]) != CONST_INT + || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))" + "mulu%.l %2,%3:%0") + (define_expand "mulsidi3" [(parallel *************** *** 2400,2404 **** (match_operand:SI 1 "register_operand" "")) (sign_extend:DI ! (match_operand:SI 2 "general_operand" ""))) 1)) (set (subreg:SI (match_dup 0) 0) (subreg:SI --- 2420,2424 ---- (match_operand:SI 1 "register_operand" "")) (sign_extend:DI ! (match_operand:SI 2 "nonimmediate_operand" ""))) 1)) (set (subreg:SI (match_dup 0) 0) (subreg:SI *************** *** 2416,2420 **** (match_operand:SI 1 "register_operand" "%0")) (sign_extend:DI ! (match_operand:SI 2 "general_operand" "dmKs"))) 1)) (set (match_operand:SI 3 "register_operand" "=d") (subreg:SI --- 2436,2440 ---- (match_operand:SI 1 "register_operand" "%0")) (sign_extend:DI ! (match_operand:SI 2 "nonimmediate_operand" "dm"))) 1)) (set (match_operand:SI 3 "register_operand" "=d") (subreg:SI *************** *** 2426,2429 **** --- 2446,2465 ---- "muls%.l %2,%3:%0") + (define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (subreg:SI + (mult:DI (sign_extend:DI + (match_operand:SI 1 "register_operand" "%0")) + (match_operand:SI 2 "immediate_operand" "sK")) 1)) + (set (match_operand:SI 3 "register_operand" "=d") + (subreg:SI + (mult:DI (sign_extend:DI + (match_dup 1)) + (match_dup 2)) 0))] + "TARGET_68020 + && (GET_CODE (operands[2]) != CONST_INT + || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))" + "muls%.l %2,%3:%0") + (define_expand "muldf3" [(set (match_operand:DF 0 "general_operand" "") *************** *** 2447,2451 **** return \"fpmul%.d %y1,%0\"; if (which_alternative == 0) ! return \"fpmul3%.d %w2,%w1,%0\"; return \"fpmul3%.d %x2,%x1,%0\"; }") --- 2483,2487 ---- return \"fpmul%.d %y1,%0\"; if (which_alternative == 0) ! return \"fpmul3%.d %w2,%w1,%0\"; return \"fpmul3%.d %x2,%x1,%0\"; }") *************** *** 2666,2669 **** --- 2702,2711 ---- "* { + #ifdef FSGLDIV_USE_S + if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) + return (TARGET_68040_ONLY + ? \"fsdiv%.s %2,%0\" + : \"fsgldiv%.s %2,%0\"); + #else if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) return (TARGET_68040_ONLY *************** *** 2670,2673 **** --- 2712,2716 ---- ? \"fsdiv%.x %2,%0\" : \"fsgldiv%.x %2,%0\"); + #endif return (TARGET_68040_ONLY ? \"fsdiv%.s %f2,%0\" *************** *** 3132,3135 **** --- 3175,3192 ---- }") + ;; Sqrt instruction for the 68881 + + (define_insn "sqrtdf2" + [(set (match_operand:DF 0 "general_operand" "=f") + (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))] + "TARGET_68881" + "* + { + if (FP_REG_P (operands[1])) + return \"fsqrt%.x %1,%0\"; + else + return \"fsqrt%.d %1,%0\"; + }") + ;; Absolute value instructions *************** *** 4752,4756 **** xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xoperands[1]) - 8); ! output_asm_insn (\"addq%.w %#8,%0; addq%.w %1,%0\", xoperands); } else --- 4809,4813 ---- xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xoperands[1]) - 8); ! output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands); } else *************** *** 4789,4793 **** xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xoperands[1]) - 8); ! output_asm_insn (\"addq%.w %#8,%0; addq%.w %1,%0\", xoperands); } else --- 4846,4850 ---- xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xoperands[1]) - 8); ! output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands); } else *************** *** 4842,4846 **** ;; ;; Which moves the jCC condition outside the inner loop for free. ! ;; (define_peephole [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" --- 4899,4903 ---- ;; ;; Which moves the jCC condition outside the inner loop for free. ! ;; (define_peephole [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" diff -rc2N gcc-2.1/config/m68ksgs.h gcc-2.2.1/config/m68ksgs.h *** gcc-2.1/config/m68ksgs.h Mon Mar 16 04:45:34 1992 --- gcc-2.2.1/config/m68ksgs.h Thu Apr 16 22:05:20 1992 *************** *** 39,42 **** --- 39,43 ---- #define SPACE_ASM_OP ".space" #define ALIGN_ASM_OP ".align" + #undef GLOBAL_ASM_OP #define GLOBAL_ASM_OP ".global" #define SWBEG_ASM_OP ".swbeg" *************** *** 200,214 **** #define TARGET_VERSION fprintf (stderr, " (68k, SGS/AT&T syntax)"); - /* This is how to output a command to make the user-level label named NAME - defined for reference from other files. */ - - #undef ASM_GLOBALIZE_LABEL - #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ - do { \ - fprintf ((FILE), "\t%s ", GLOBAL_ASM_OP); \ - assemble_name ((FILE), NAME); \ - fputs ("\n", FILE); \ - } while (0) - #undef PRINT_OPERAND_PRINT_FLOAT #define PRINT_OPERAND_PRINT_FLOAT(CODE,FILE) \ --- 201,204 ---- *************** *** 393,398 **** /* At end of a switch table, define LDnnn iff the symbol LInnn was defined. Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" ! fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results ! we want. This difference can be accommodated by using an assembler define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END --- 383,388 ---- /* At end of a switch table, define LDnnn iff the symbol LInnn was defined. Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" ! fails to assemble. Luckily "LDnnn(pc,d0.l*2)" produces the results ! we want. This difference can be accommodated by making the assembler define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END *************** *** 401,407 **** #undef ASM_OUTPUT_CASE_END #define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \ ! if (RTX_INTEGRATED_P (TABLE)) \ asm_fprintf (FILE, "\t%s %LLD%d,%LL%d-%LLI%d-2.b\n",\ ! SET_ASM_OP, (NUM), (NUM), (NUM)) /* This is how to output an element of a case-vector that is relative. */ --- 391,400 ---- #undef ASM_OUTPUT_CASE_END #define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \ ! { if (switch_table_difference_label_flag) \ asm_fprintf (FILE, "\t%s %LLD%d,%LL%d-%LLI%d-2.b\n",\ ! SET_ASM_OP, (NUM), (NUM), (NUM)) \ ! switch_table_difference_label_flag = 0; } ! ! int switch_table_difference_label_flag; /* This is how to output an element of a case-vector that is relative. */ diff -rc2N gcc-2.1/config/m88k.c gcc-2.2.1/config/m88k.c *** gcc-2.1/config/m88k.c Fri Mar 20 07:22:46 1992 --- gcc-2.2.1/config/m88k.c Fri May 29 13:36:29 1992 *************** *** 39,43 **** #include "c-tree.h" #include "expr.h" - #include "hard-reg-set.h" #include "flags.h" --- 39,42 ---- *************** *** 48,52 **** extern FILE *asm_out_file; ! static char out_sccs_id[] = "@(#)m88k.c 2.0.3.4 19 Mar 1992 11:11:58"; static char tm_sccs_id [] = TM_SCCS_ID; --- 47,51 ---- extern FILE *asm_out_file; ! static char out_sccs_id[] = "@(#)m88k.c 2.1.11.11 29 May 1992 11:12:23"; static char tm_sccs_id [] = TM_SCCS_ID; *************** *** 213,217 **** else if (GET_CODE (operand0) == MEM) { ! if (register_operand (operand1, mode) || operand1 == const0_rtx) { /* Run this case quickly. */ --- 212,217 ---- else if (GET_CODE (operand0) == MEM) { ! if (register_operand (operand1, mode) ! || (operand1 == const0_rtx && GET_MODE_SIZE (mode) <= UNITS_PER_WORD)) { /* Run this case quickly. */ *************** *** 719,722 **** --- 719,723 ---- { rtx jump; + rtx seq_insn; /* This can be generalized, but there is currently no need. */ *************** *** 724,727 **** --- 725,730 ---- abort (); + /* The address of interior insns is not computed, so use the sequence. */ + seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); jump = XVECEXP (final_sequence, 0, 1); if (GET_CODE (jump) == JUMP_INSN) *************** *** 731,735 **** rtx dest = XEXP (SET_SRC (PATTERN (jump)), 0); int delta = 4 * (insn_addresses[INSN_UID (dest)] ! - insn_addresses[INSN_UID (jump)]); #if (MONITOR_GCC & 0x2) /* How often do long branches happen? */ if ((unsigned) (delta + 0x8000) >= 0x10000) --- 734,739 ---- rtx dest = XEXP (SET_SRC (PATTERN (jump)), 0); int delta = 4 * (insn_addresses[INSN_UID (dest)] ! - insn_addresses[INSN_UID (seq_insn)] ! - 2); #if (MONITOR_GCC & 0x2) /* How often do long branches happen? */ if ((unsigned) (delta + 0x8000) >= 0x10000) *************** *** 813,817 **** /* This will change as the assembler requirements become known. */ fprintf (stream, "\t%s\t %s,%s-%s\n", ! DEF_ASM_OP, &name[1], &high[1], &low[1]); } if (sb_name || sb_high || sb_low) --- 817,821 ---- /* This will change as the assembler requirements become known. */ fprintf (stream, "\t%s\t %s,%s-%s\n", ! SET_ASM_OP, &name[1], &high[1], &low[1]); } if (sb_name || sb_high || sb_low) *************** *** 819,865 **** } ! /* Report errors on floating point, if we are given NaN's, or such. Leave ! the number as is, though, since we output the number in hex, and the ! assembler won't choke on it. */ ! void ! check_float_value (mode, value) ! enum machine_mode mode; ! REAL_VALUE_TYPE value; { ! union { ! REAL_VALUE_TYPE d; ! struct { ! unsigned sign : 1; ! unsigned exponent : 11; ! unsigned mantissa1 : 20; ! unsigned mantissa2; ! } s; ! } u; ! if (mode == DFmode) ! { ! u.d = value; ! if (u.s.mantissa1 != 0 || u.s.mantissa2 != 0) { ! if (u.s.exponent == 0x7ff) /* Not a Number */ ! warning ("floating point number is not valid for IEEE double precision"); ! else if (u.s.exponent == 0) ! warning ("denormalized double precision floating point number"); } } ! else if (mode == SFmode) ! { ! u.d = REAL_VALUE_TRUNCATE (mode, value); ! if (u.s.mantissa1 != 0 || u.s.mantissa2 != 0) { ! if (u.s.exponent == 0x7ff) /* Not a Number */ ! warning ("floating point number is not valid for IEEE double precision"); ! else if (u.s.exponent == 0) ! warning ("denormalized single precision floating point number"); } ! else if (u.s.exponent == 0x7ff) /* Infinity */ ! warning ("floating point number exceeds range of `float'"); } } --- 823,935 ---- } ! /* Return truth value of the statement that this conditional branch is likely ! to fall through. CONDITION, is the condition that JUMP_INSN is testing. */ ! int ! mostly_false_jump (jump_insn, condition) ! rtx jump_insn, condition; { ! rtx target_label = JUMP_LABEL (jump_insn); ! rtx insnt, insnj; ! /* Much of this isn't computed unless we're optimizing. */ ! if (optimize == 0) ! return 0; ! ! /* Determine if one path or the other leads to a return. */ ! for (insnt = NEXT_INSN (target_label); ! insnt; ! insnt = NEXT_INSN (insnt)) ! { ! if (GET_CODE (insnt) == JUMP_INSN) ! break; ! else if (GET_CODE (insnt) == SEQUENCE ! && GET_CODE (XVECEXP (insnt, 0, 0)) == JUMP_INSN) { ! insnt = XVECEXP (insnt, 0, 0); ! break; } } ! if (insnt ! && (GET_CODE (PATTERN (insnt)) == RETURN ! || (GET_CODE (PATTERN (insnt)) == SET ! && GET_CODE (SET_SRC (PATTERN (insnt))) == REG ! && REGNO (SET_SRC (PATTERN (insnt))) == 1))) ! insnt = 0; ! ! for (insnj = NEXT_INSN (jump_insn); ! insnj; ! insnj = NEXT_INSN (insnj)) ! { ! if (GET_CODE (insnj) == JUMP_INSN) ! break; ! else if (GET_CODE (insnj) == SEQUENCE ! && GET_CODE (XVECEXP (insnj, 0, 0)) == JUMP_INSN) { ! insnj = XVECEXP (insnj, 0, 0); ! break; } ! } ! if (insnj ! && (GET_CODE (PATTERN (insnj)) == RETURN ! || (GET_CODE (PATTERN (insnj)) == SET ! && GET_CODE (SET_SRC (PATTERN (insnj))) == REG ! && REGNO (SET_SRC (PATTERN (insnj))) == 1))) ! insnt = 0; ! ! /* Predict to not return. */ ! if ((insnt == 0) != (insnj == 0)) ! return (insnt == 0); ! ! /* Predict loops to loop. */ ! for (insnt = PREV_INSN (target_label); ! insnt && GET_CODE (insnt) == NOTE; ! insnt = PREV_INSN (insnt)) ! if (NOTE_LINE_NUMBER (insnt) == NOTE_INSN_LOOP_END) ! return 1; ! else if (NOTE_LINE_NUMBER (insnt) == NOTE_INSN_LOOP_BEG) ! return 0; ! else if (NOTE_LINE_NUMBER (insnt) == NOTE_INSN_LOOP_CONT) ! return 0; ! ! /* Predict backward branches usually take. */ ! if (final_sequence) ! insnj = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); ! else ! insnj = jump_insn; ! if (insn_addresses[INSN_UID (insnj)] ! > insn_addresses[INSN_UID (target_label)]) ! return 0; ! ! /* EQ tests are usually false and NE tests are usually true. Also, ! most quantities are positive, so we can make the appropriate guesses ! about signed comparisons against zero. Consider unsigned comparsions ! to be a range check and assume quantities to be in range. */ ! switch (GET_CODE (condition)) ! { ! case CONST_INT: ! /* Unconditional branch. */ ! return 0; ! case EQ: ! return 1; ! case NE: ! return 0; ! case LE: ! case LT: ! case GEU: ! case GTU: /* Must get casesi right at least. */ ! if (XEXP (condition, 1) == const0_rtx) ! return 1; ! break; ! case GE: ! case GT: ! case LEU: ! case LTU: ! if (XEXP (condition, 1) == const0_rtx) ! return 0; ! break; } + + return 0; } *************** *** 1261,1264 **** --- 1331,1336 ---- if (profile_flag) pos = output_option (file, sep, "-p", "", indent, pos, max); + if (profile_block_flag) + pos = output_option (file, sep, "-a", "", indent, pos, max); for (j = 0; j < f_len; j++) *************** *** 1323,1328 **** void ! output_ascii (file, p, size) FILE *file; unsigned char *p; int size; --- 1395,1402 ---- void ! output_ascii (file, opcode, max, p, size) FILE *file; + char *opcode; + int max; unsigned char *p; int size; *************** *** 1332,1336 **** register int num = 0; ! fprintf (file, "\t%s\t \"", ASCII_DATA_ASM_OP); for (i = 0; i < size; i++) { --- 1406,1410 ---- register int num = 0; ! fprintf (file, "\t%s\t \"", opcode); for (i = 0; i < size; i++) { *************** *** 1337,1343 **** register int c = p[i]; ! if (num > 48) { ! fprintf (file, "\"\n\t%s\t \"", ASCII_DATA_ASM_OP); num = 0; } --- 1411,1417 ---- register int c = p[i]; ! if (num > max) { ! fprintf (file, "\"\n\t%s\t \"", opcode); num = 0; } *************** *** 1364,1368 **** can get it to parse the data properly. */ if (i < size - 1 && p[i + 1] >= '0' && p[i + 1] <= '9') ! num = 32767; /* next pass will start a new string */ } } --- 1438,1442 ---- can get it to parse the data properly. */ if (i < size - 1 && p[i + 1] >= '0' && p[i + 1] <= '9') ! num = max + 1; /* next pass will start a new string */ } } *************** *** 1412,1416 **** if (state == ps_value) { ! fprintf (asm_out_file, "\t%s\t ", DEF_ASM_OP); ASM_OUTPUT_LABELREF (asm_out_file, name); fputc (',', asm_out_file); --- 1486,1490 ---- if (state == ps_value) { ! fprintf (asm_out_file, "\t%s\t ", SET_ASM_OP); ASM_OUTPUT_LABELREF (asm_out_file, name); fputc (',', asm_out_file); *************** *** 1528,1531 **** --- 1602,1607 ---- |==============================================| <- fp | [preserved registers (r25..r14)] | + |----------------------------------------------| + | [preserved registers (x29..x22)] | |==============================================| | [dynamically allocated space (alloca)] | *************** *** 1549,1552 **** --- 1625,1629 ---- static int nregs; + static int nxregs; static char save_regs[FIRST_PSEUDO_REGISTER]; static int frame_laid_out; *************** *** 1562,1565 **** --- 1639,1645 ---- #define LAST_OCS_PRESERVE_REGISTER 30 + #define FIRST_OCS_EXTENDED_PRESERVE_REGISTER (32 + 22) + #define LAST_OCS_EXTENDED_PRESERVE_REGISTER (32 + 31) + #define STACK_UNIT_BOUNDARY (STACK_BOUNDARY / BITS_PER_UNIT) #define ROUND_CALL_BLOCK_SIZE(BYTES) \ *************** *** 1577,1585 **** bzero ((char *) &save_regs[0], sizeof (save_regs)); ! sp_size = nregs = 0; frame_size = get_frame_size (); /* Since profiling requires a call, make sure r1 is saved. */ ! if (profile_flag) save_regs[1] = 1; --- 1657,1665 ---- bzero ((char *) &save_regs[0], sizeof (save_regs)); ! sp_size = nregs = nxregs = 0; frame_size = get_frame_size (); /* Since profiling requires a call, make sure r1 is saved. */ ! if (profile_flag || profile_block_flag) save_regs[1] = 1; *************** *** 1610,1616 **** /* If a frame is requested, save the previous FP, and the return address (r1), so that a traceback can be done without using tdesc ! information. */ if (frame_pointer_needed) save_regs[FRAME_POINTER_REGNUM] = save_regs[1] = 1; /* Figure out which normal register(s) needs to be saved. */ --- 1690,1708 ---- /* If a frame is requested, save the previous FP, and the return address (r1), so that a traceback can be done without using tdesc ! information. Otherwise, simply save the FP if it is used as ! a preserve register. */ if (frame_pointer_needed) save_regs[FRAME_POINTER_REGNUM] = save_regs[1] = 1; + else if (regs_ever_live[FRAME_POINTER_REGNUM]) + save_regs[FRAME_POINTER_REGNUM] = 1; + + /* Figure out which extended register(s) needs to be saved. */ + for (regno = FIRST_EXTENDED_REGISTER + 1; regno < FIRST_PSEUDO_REGISTER; + regno++) + if (regs_ever_live[regno] && ! call_used_regs[regno]) + { + save_regs[regno] = 1; + nxregs++; + } /* Figure out which normal register(s) needs to be saved. */ *************** *** 1623,1627 **** /* Achieve greatest use of double memory ops. Either we end up saving ! r30 or we use that slot to align the regsters we do save. */ if (nregs >= 2 && save_regs[1] && !save_regs[FRAME_POINTER_REGNUM]) sp_size += 4; --- 1715,1719 ---- /* Achieve greatest use of double memory ops. Either we end up saving ! r30 or we use that slot to align the registers we do save. */ if (nregs >= 2 && save_regs[1] && !save_regs[FRAME_POINTER_REGNUM]) sp_size += 4; *************** *** 1628,1632 **** --- 1720,1728 ---- nregs += save_regs[1] + save_regs[FRAME_POINTER_REGNUM]; + /* if we need to align extended registers, add a word */ + if (nxregs > 0 && (nregs & 1) != 0) + sp_size +=4; sp_size += 4 * nregs; + sp_size += 8 * nxregs; sp_size += current_function_outgoing_args_size; *************** *** 1634,1645 **** if any. In the only case this matters, they are r1 and r30. */ if (frame_pointer_needed || sp_size) ! { ! m88k_fp_offset = ROUND_CALL_BLOCK_SIZE (sp_size - STARTING_FRAME_OFFSET); ! m88k_stack_size = m88k_fp_offset + STARTING_FRAME_OFFSET; ! } else ! { ! m88k_stack_size = m88k_fp_offset = 0; ! } /* First, combine m88k_stack_size and size. If m88k_stack_size is --- 1730,1737 ---- if any. In the only case this matters, they are r1 and r30. */ if (frame_pointer_needed || sp_size) ! m88k_fp_offset = ROUND_CALL_BLOCK_SIZE (sp_size - STARTING_FRAME_OFFSET); else ! m88k_fp_offset = -STARTING_FRAME_OFFSET; ! m88k_stack_size = m88k_fp_offset + STARTING_FRAME_OFFSET; /* First, combine m88k_stack_size and size. If m88k_stack_size is *************** *** 1675,1678 **** --- 1767,1771 ---- return (! frame_pointer_needed && nregs == 0 + && nxregs == 0 && m88k_stack_size == 0); } *************** *** 1763,1767 **** case TYPE_ARITH: case TYPE_MARITH: - case TYPE_MSTORE: return ok_for_epilogue_p (PATTERN (insn)); default: --- 1856,1859 ---- *************** *** 1835,1839 **** output_reg_adjust (stream, 31, 31, -m88k_stack_size, 0); ! if (nregs) preserve_registers (stream, m88k_fp_offset + 4, 1); --- 1927,1931 ---- output_reg_adjust (stream, 31, 31, -m88k_stack_size, 0); ! if (nregs || nxregs) preserve_registers (stream, m88k_fp_offset + 4, 1); *************** *** 1909,1913 **** output_reg_adjust (stream, 31, 30, -m88k_fp_offset, 0); ! if (nregs) preserve_registers (stream, m88k_fp_offset + 4, 0); --- 2001,2005 ---- output_reg_adjust (stream, 31, 30, -m88k_fp_offset, 0); ! if (nregs || nxregs) preserve_registers (stream, m88k_fp_offset + 4, 0); *************** *** 2048,2051 **** --- 2140,2158 ---- } } + + /* Walk the extended registers to record all memory operations. */ + /* Be sure the offset is double word aligned. */ + offset = (offset - 1) & ~7; + for (regno = FIRST_PSEUDO_REGISTER - 1; regno > FIRST_EXTENDED_REGISTER; + regno--) + if (save_regs[regno]) + { + mo_ptr->nregs = 2; + mo_ptr->regno = regno; + mo_ptr->offset = offset; + mo_ptr++; + offset -= 2*4; + } + mo_ptr->regno = 0; *************** *** 2070,2077 **** if (mo_ptr->nregs) { rtx ok_insns = delay_insns; int i; ! for (i = 0; i < mo_ptr->nregs; i++) epilogue_dead_regs[mo_ptr->regno + i] = 1; --- 2177,2186 ---- if (mo_ptr->nregs) { + int nregs = (mo_ptr->regno < FIRST_EXTENDED_REGISTER + ? mo_ptr->nregs : 1); rtx ok_insns = delay_insns; int i; ! for (i = 0; i < nregs; i++) epilogue_dead_regs[mo_ptr->regno + i] = 1; *************** *** 2083,2087 **** if (! ok_for_epilogue_p (PATTERN (insn))) { ! for (i = 0; i < mo_ptr->nregs; i++) epilogue_dead_regs[mo_ptr->regno + i] = 0; insn = 0; --- 2192,2196 ---- if (! ok_for_epilogue_p (PATTERN (insn))) { ! for (i = 0; i < nregs; i++) epilogue_dead_regs[mo_ptr->regno + i] = 0; insn = 0; *************** *** 2147,2156 **** The information is: 0 8: zero ! 0 22: info-byte-length (16 bytes) 0 2: info-alignment (word 2) ! 1 32: info-protocol (version 1) 2 32: starting-address (inclusive, not counting prologue) 3 32: ending-address (exclusive, not counting epilog) ! 4 8: info-variant (version 1) 4 17: register-save-mask (from register 14 to 30) 4 1: zero --- 2256,2265 ---- The information is: 0 8: zero ! 0 22: info-byte-length (16 or 20 bytes) 0 2: info-alignment (word 2) ! 1 32: info-protocol (version 1 or 2(pic)) 2 32: starting-address (inclusive, not counting prologue) 3 32: ending-address (exclusive, not counting epilog) ! 4 8: info-variant (version 1 or 3(extended registers)) 4 17: register-save-mask (from register 14 to 30) 4 1: zero *************** *** 2159,2163 **** 5 32: frame-address-offset 6 32: return-address-info ! 7 32: register-save-offset */ static void --- 2268,2274 ---- 5 32: frame-address-offset 6 32: return-address-info ! 7 32: register-save-offset ! 8 16: extended-register-save-mask (x16 - x31) ! 8 16: extended-register-save-offset (WORDS from register-save-offset) */ static void *************** *** 2166,2171 **** int offset; { ! int regno, i; long mask, return_address_info, register_save_offset; char buf[256]; --- 2277,2283 ---- int offset; { ! int regno, i, j; long mask, return_address_info, register_save_offset; + long xmask, xregister_save_offset; char buf[256]; *************** *** 2182,2188 **** } if (save_regs[1]) { ! if (nregs > 2 && !save_regs[FRAME_POINTER_REGNUM]) offset -= 4; return_address_info = - m88k_stack_size + offset; --- 2294,2312 ---- } + for (xmask = 0, j = 0, regno = FIRST_OCS_EXTENDED_PRESERVE_REGISTER; + regno <= LAST_OCS_EXTENDED_PRESERVE_REGISTER; + regno++) + { + xmask <<= 1; + if (save_regs[regno]) + { + xmask |= 1; + j++; + } + } + if (save_regs[1]) { ! if ((nxregs > 0 || nregs > 2) && !save_regs[FRAME_POINTER_REGNUM]) offset -= 4; return_address_info = - m88k_stack_size + offset; *************** *** 2195,2202 **** } tdesc_section (); ! fprintf (file, "\t%s\t %d", INT_ASM_OP, (16 << 2) | 2 /* 8:0,22:16,2:2 */); ! fprintf (file, ",%d", flag_pic ? 2 : 1); ASM_GENERATE_INTERNAL_LABEL (buf, OCS_START_PREFIX, m88k_function_number); --- 2319,2329 ---- } + xregister_save_offset = - (j * 2 + ((register_save_offset >> 2) & 1)); + tdesc_section (); ! fprintf (file, "\t%s\t %d,%d", INT_ASM_OP, /* 8:0,22:(20 or 16),2:2 */ ! (((xmask != 0) ? 20 : 16) << 2) | 2, ! flag_pic ? 2 : 1); ASM_GENERATE_INTERNAL_LABEL (buf, OCS_START_PREFIX, m88k_function_number); *************** *** 2205,2220 **** fprintf (file, ",%s%s", buf+1, flag_pic ? "#rel" : ""); ! fprintf (file, ",0x%x", /* 8:1,17:0x%.3x,1:0,1:%d,5:%d */ ! (1 << (17+1+1+5)) | ! (mask << (1+1+5)) | ! ((!!save_regs[1]) << 5) | ! ((frame_pointer_needed ! ? FRAME_POINTER_REGNUM ! : STACK_POINTER_REGNUM))); ! ! fprintf (file, ",0x%x", (m88k_stack_size ! - (frame_pointer_needed ? m88k_fp_offset : 0))); ! fprintf (file, ",0x%x", return_address_info); ! fprintf (file, ",0x%x\n", register_save_offset); text_section (); --- 2332,2349 ---- fprintf (file, ",%s%s", buf+1, flag_pic ? "#rel" : ""); ! fprintf (file, ",0x%x,0x%x,0x%x,0x%x", ! /* 8:1,17:0x%.3x,1:0,1:%d,5:%d */ ! (((xmask ? 3 : 1) << (17+1+1+5)) ! | (mask << (1+1+5)) ! | ((!!save_regs[1]) << 5) ! | (frame_pointer_needed ! ? FRAME_POINTER_REGNUM ! : STACK_POINTER_REGNUM)), ! (m88k_stack_size - (frame_pointer_needed ? m88k_fp_offset : 0)), ! return_address_info, ! register_save_offset); ! if (xmask) ! fprintf (file, ",0x%x%04x", xmask, (0xffff & xregister_save_offset)); ! fputc ('\n', file); text_section (); *************** *** 2307,2310 **** --- 2436,2444 ---- fprintf (file, "\tbcnd\t %sne0,%s,%s\n", m88k_pound_sign, reg_names[26], &label[1]); + fprintf (file, "\tsubu\t %s,%s,64\n", reg_names[31], reg_names[31]); + fprintf (file, "\tst.d\t %s,%s,32\n", reg_names[2], reg_names[31]); + fprintf (file, "\tst.d\t %s,%s,40\n", reg_names[4], reg_names[31]); + fprintf (file, "\tst.d\t %s,%s,48\n", reg_names[6], reg_names[31]); + fprintf (file, "\tst.d\t %s,%s,56\n", reg_names[8], reg_names[31]); fputs ("\tbsr.n\t ", file); ASM_OUTPUT_LABELREF (file, "__bb_init_func"); *************** *** 2312,2315 **** --- 2446,2454 ---- fprintf (file, "\tor\t %s,%s,%slo16(%s)\n", reg_names[2], reg_names[27], m88k_pound_sign, &block[1]); + fprintf (file, "\tld.d\t %s,%s,32\n", reg_names[2], reg_names[31]); + fprintf (file, "\tld.d\t %s,%s,40\n", reg_names[4], reg_names[31]); + fprintf (file, "\tld.d\t %s,%s,48\n", reg_names[6], reg_names[31]); + fprintf (file, "\tld.d\t %s,%s,56\n", reg_names[8], reg_names[31]); + fprintf (file, "\taddu\t %s,%s,64\n", reg_names[31], reg_names[31]); ASM_OUTPUT_INTERNAL_LABEL (file, "LPY", labelno); } *************** *** 2325,2329 **** char block[256]; ! ASM_GENERATE_INTERNAL_LABEL (block, "LPBX", 0); /* @@ Need to deal with PIC. I'm not sure what the requirements are on --- 2464,2468 ---- char block[256]; ! ASM_GENERATE_INTERNAL_LABEL (block, "LPBX", 2); /* @@ Need to deal with PIC. I'm not sure what the requirements are on *************** *** 2469,2474 **** copy_to_reg (XEXP (addr, 0))); ! /* Now store the incoming registers and return the address of the ! va_list constructor. */ if (fixed < 8) move_block_from_reg --- 2608,2612 ---- copy_to_reg (XEXP (addr, 0))); ! /* Now store the incoming registers. */ if (fixed < 8) move_block_from_reg *************** *** 2479,2483 **** 8 - fixed); ! return copy_to_reg (XEXP (block, 0)); } --- 2617,2624 ---- 8 - fixed); ! /* Return the address of the va_list constructor, but don't put it in a ! register. This fails when not optimizing and produces worse code when ! optimizing. */ ! return XEXP (block, 0); } diff -rc2N gcc-2.1/config/m88k.h gcc-2.2.1/config/m88k.h *** gcc-2.1/config/m88k.h Fri Mar 20 11:19:32 1992 --- gcc-2.2.1/config/m88k.h Fri May 29 13:36:11 1992 *************** *** 105,109 **** extern void emit_bcnd (); extern void expand_block_move (); - extern void check_float_value (); extern void m88k_layout_frame (); extern void m88k_output_prologue (); --- 105,108 ---- *************** *** 205,211 **** Redefined in m88kv4.h, and m88kluna.h. */ #define VERSION_INFO1 "88open OCS/BCS, " ! #define VERSION_INFO2 "20 Mar 1992" #define VERSION_STRING version_string ! #define TM_SCCS_ID "@(#)m88k.h 2.0.3.6 20 Mar 1992 08:33:40" /* Run-time compilation parameters selecting different hardware subsets. */ --- 204,210 ---- Redefined in m88kv4.h, and m88kluna.h. */ #define VERSION_INFO1 "88open OCS/BCS, " ! #define VERSION_INFO2 "29 May 1992" #define VERSION_STRING version_string ! #define TM_SCCS_ID "@(#)m88k.h 2.1.11.11 29 May 1992 13:20:31" /* Run-time compilation parameters selecting different hardware subsets. */ *************** *** 426,433 **** /* #define MAX_FIXED_MODE_SIZE 0 */ ! /* Report errors on floating point, if we are given NaN's, or such. Leave ! the number as is, though, since we output the number in hex, and the ! assembler won't choke on it. */ ! #define CHECK_FLOAT_VALUE(MODE,VALUE) check_float_value (MODE, VALUE) /* A code distinguishing the floating point format of the target machine. */ --- 425,432 ---- /* #define MAX_FIXED_MODE_SIZE 0 */ ! /* Check a `double' value for validity for a particular machine mode. ! This is defined to avoid crashes outputting certain constants. ! Since we output the number in hex, the assembler won't choke on it. */ ! /* #define CHECK_FLOAT_VALUE(MODE,VALUE) */ /* A code distinguishing the floating point format of the target machine. */ *************** *** 442,460 **** even those that are not normally considered general registers. ! The m88100 has 32 fullword registers. ! The pseudo argument pointer is said to be register 0. This prohibits ! the use of r0 as a general register and causes no trouble. ! Using register 0 is useful, in that it keeps the number of ! registers down to 32, and GNU can use a long as a bitmask ! for the registers. */ ! #define FIRST_PSEUDO_REGISTER 32 ! ! /* 1 for registers that have pervasive standard uses ! and are not available for the register allocator. ! Registers 14-25 are expected to be preserved across ! function calls. ! ! On the 88000, these are: Reg 0 = Pseudo argument pointer (hardware fixed to 0). Reg 1 = Subroutine return pointer (hardware). --- 441,545 ---- even those that are not normally considered general registers. ! The m88100 has a General Register File (GRF) of 32 32-bit registers. ! The m88110 adds an Extended Register File (XRF) of 32 80-bit registers. */ ! #define FIRST_PSEUDO_REGISTER 64 ! #define FIRST_EXTENDED_REGISTER 32 ! ! /* General notes on extended registers, their use and misuse. ! ! Possible good uses: ! ! spill area instead of memory. ! -waste if only used once ! ! floating point caluclations ! -probably a waste unless we have run out of general purpose registers ! ! freeing up general purpose registers ! -e.g. may be able to have more loop invariants if floating ! point is moved into extended registers. ! ! ! I've noticed wasteful moves into and out of extended registers; e.g. a load ! into x21, then inside a loop a move into r24, then r24 used as input to ! an fadd. Why not just load into r24 to begin with? Maybe the new cse.c ! will address this. This wastes a move, but the load,store and move could ! have been saved had extended registers been used throughout. ! E.g. in the code following code, if z and xz are placed in extended ! registers, there is no need to save preserve registers. ! ! long c=1,d=1,e=1,f=1,g=1,h=1,i=1,j=1,k; ! ! double z=0,xz=4.5; ! ! foo(a,b) ! long a,b; ! { ! while (a < b) ! { ! k = b + c + d + e + f + g + h + a + i + j++; ! z += xz; ! a++; ! } ! printf("k= %d; z=%f;\n", k, z); ! } ! ! I've found that it is possible to change the constraints (putting * before ! the 'r' constraints int the fadd.ddd instruction) and get the entire ! addition and store to go into extended registers. However, this also ! forces simple addition and return of floating point arguments to a ! function into extended registers. Not the correct solution. ! ! Found the following note in local-alloc.c which may explain why I can't ! get both registers to be in extended registers since two are allocated in ! local-alloc and one in global-alloc. Doesn't explain (I don't believe) ! why an extended register is used instead of just using the preserve ! register. ! ! from local-alloc.c: ! We have provision to exempt registers, even when they are contained ! within the block, that can be tied to others that are not contained in it. ! This is so that global_alloc could process them both and tie them then. ! But this is currently disabled since tying in global_alloc is not ! yet implemented. ! ! The explaination of why the preserved register is not used is as follows, ! I believe. The registers are being allocated in order. Tieing is not ! done so efficiently, so when it comes time to do the first allocation, ! there are no registers left to use without spilling except extended ! registers. Then when the next pseudo register needs a hard reg, there ! are still no registers to be had for free, but this one must be a GRF ! reg instead of an extended reg, so a preserve register is spilled. Thus ! the move from extended to GRF is necessitated. I do not believe this can ! be 'fixed' through the config/*m88k* files. ! ! gcc seems to sometimes make worse use of register allocation -- not counting ! moves -- whenever extended registers are present. For example in the ! whetstone, the simple for loop (slightly modified) ! for(i = 1; i <= n1; i++) ! { ! x1 = (x1 + x2 + x3 - x4) * t; ! x2 = (x1 + x2 - x3 + x4) * t; ! x3 = (x1 - x2 + x3 + x4) * t; ! x4 = (x1 + x2 + x3 + x4) * t; ! } ! in general loads the high bits of the addresses of x2-x4 and i into registers ! outside the loop. Whenever extended registers are used, it loads all of ! these inside the loop. My conjecture is that since the 88110 has so many ! registers, and gcc makes no distinction at this point -- just that they are ! not fixed, that in loop.c it believes it can expect a number of registers ! to be available. Then it allocates 'too many' in local-alloc which causes ! problems later. 'Too many' are allocated because a large portion of the ! registers are extended registers and cannot be used for certain purposes ! ( e.g. hold the address of a variable). When this loop is compiled on its ! own, the problem does not occur. I don't know the solution yet, though it ! is probably in the base sources. Possibly a different way to calculate ! "threshold". */ ! ! /* 1 for registers that have pervasive standard uses and are not available ! for the register allocator. Registers r14-r25 and x22-x29 are expected ! to be preserved across function calls. ! On the 88000, the standard uses of the General Register File (GRF) are: Reg 0 = Pseudo argument pointer (hardware fixed to 0). Reg 1 = Subroutine return pointer (hardware). *************** *** 467,475 **** Reg 26-29 = Reserved by OCS and ABI. Reg 30 = Frame pointer (Common use). ! Reg 31 = Stack pointer. */ #define FIXED_REGISTERS \ ! {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ! 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1} /* 1 for registers not available across function calls. --- 552,578 ---- Reg 26-29 = Reserved by OCS and ABI. Reg 30 = Frame pointer (Common use). ! Reg 31 = Stack pointer. ! ! The following follows the current 88open UCS specification for the ! Extended Register File (XRF): ! Reg 32 = x0 Always equal to zero ! Reg 33-53 = x1-x21 Tempory registers (Caller Save) ! Reg 54-61 = x22-x29 Preserver registers (Callee Save) ! Reg 62-63 = x30-x31 Reserved for future ABI use. ! ! Note: The current 88110 extended register mapping is subject to change. ! The bias towards caller-save registers is based on the ! presumption that memory traffic can potentially be reduced by ! allowing the "caller" to save only that part of the register ! which is actually being used. (i.e. don't do a st.x if a st.d ! is sufficient). Also, in scientific code (a.k.a. Fortran), the ! large number of variables defined in common blocks may require ! that almost all registers be saved across calls anyway. */ #define FIXED_REGISTERS \ ! {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ! 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ ! 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ! 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1} /* 1 for registers not available across function calls. *************** *** 482,486 **** #define CALL_USED_REGISTERS \ {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ ! 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1} /* Macro to conditionally modify fixed_regs/call_used_regs. */ --- 585,591 ---- #define CALL_USED_REGISTERS \ {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ ! 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ ! 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ ! 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1} /* Macro to conditionally modify fixed_regs/call_used_regs. */ *************** *** 487,492 **** #define CONDITIONAL_REGISTER_USAGE \ { \ if (flag_pic) \ ! fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ } --- 592,611 ---- #define CONDITIONAL_REGISTER_USAGE \ { \ + if (! TARGET_88110) \ + { \ + register int i; \ + for (i = FIRST_EXTENDED_REGISTER; i < FIRST_PSEUDO_REGISTER; i++) \ + { \ + fixed_regs[i] = 1; \ + call_used_regs[i] = 1; \ + } \ + } \ if (flag_pic) \ ! { \ ! /* Current hack to deal with -fpic -O2 problems. */ \ ! fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ ! call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ ! global_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ ! } \ } *************** *** 501,509 **** but can be less for certain modes in special long registers. ! On the m88000, ordinary registers hold 32 bits worth; ! a single floating point register is always enough for ! anything that can be stored in them at all. */ ! #define HARD_REGNO_NREGS(REGNO, MODE) \ ! ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. --- 620,629 ---- but can be less for certain modes in special long registers. ! On the m88000, GRF registers hold 32-bits and XRF registers hold 80-bits. ! An XRF register can hold any mode, but two GRF registers are required ! for larger modes. */ ! #define HARD_REGNO_NREGS(REGNO, MODE) \ ! ((REGNO < FIRST_PSEUDO_REGISTER && REGNO >= FIRST_EXTENDED_REGISTER) \ ! ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. *************** *** 511,519 **** For double integers, we never put the value into an odd register so that the operators don't run into the situation where the high part of one of ! the inputs is the low part of the result register (it's ok if the output ! registers are the same as the input registers. */ ! #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ! (((MODE) != DImode && (MODE) != DFmode && (MODE) != DCmode) || \ ! ((REGNO) & 1) == 0) /* Value is 1 if it is a good idea to tie two pseudo registers --- 631,644 ---- For double integers, we never put the value into an odd register so that the operators don't run into the situation where the high part of one of ! the inputs is the low part of the result register. (It's ok if the output ! registers are the same as the input registers.) The XRF registers can ! hold all modes, but only DF and SF modes can be manipulated in these ! registers. The compiler should be allowed to use these as a fast spill ! area. */ ! #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ! ((REGNO < FIRST_PSEUDO_REGISTER && REGNO >= FIRST_EXTENDED_REGISTER) \ ! ? TARGET_88110 \ ! : (((MODE) != DImode && (MODE) != DFmode && (MODE) != DCmode) \ ! || ((REGNO) & 1) == 0)) /* Value is 1 if it is a good idea to tie two pseudo registers *************** *** 557,567 **** registers, then param registers top down. Preserve registers are top down to maximize use of double memory ops for register save. ! The 88open reserved registers (26-29) may commonly be used in most ! environments with the -fcall-used- or -fcall-saved- options. */ ! #define REG_ALLOC_ORDER \ ! {13, 12, 11, 10, 29, 28, 27, 26, \ ! 1, 9, 8, 7, 6, 5, 4, 3, \ ! 2, 25, 24, 23, 22, 21, 20, 19, \ ! 18, 17, 16, 15, 14, 30, 31, 0} /*** Register Classes ***/ --- 682,720 ---- registers, then param registers top down. Preserve registers are top down to maximize use of double memory ops for register save. ! The 88open reserved registers (r26-r29 and x30-x31) may commonly be used ! in most environments with the -fcall-used- or -fcall-saved- options. */ ! #define REG_ALLOC_ORDER \ ! { \ ! 13, 12, 11, 10, 29, 28, 27, 26, \ ! 62, 63, 9, 8, 7, 6, 5, 4, \ ! 3, 2, 1, 53, 52, 51, 50, 49, \ ! 48, 47, 46, 45, 44, 43, 42, 41, \ ! 40, 39, 38, 37, 36, 35, 34, 33, \ ! 25, 24, 23, 22, 21, 20, 19, 18, \ ! 17, 16, 15, 14, 61, 60, 59, 58, \ ! 57, 56, 55, 54, 30, 31, 0, 32} ! ! /* Order for leaf functions. */ ! #define REG_LEAF_ALLOC_ORDER \ ! { \ ! 9, 8, 7, 6, 13, 12, 11, 10, \ ! 29, 28, 27, 26, 62, 63, 5, 4, \ ! 3, 2, 0, 53, 52, 51, 50, 49, \ ! 48, 47, 46, 45, 44, 43, 42, 41, \ ! 40, 39, 38, 37, 36, 35, 34, 33, \ ! 25, 24, 23, 22, 21, 20, 19, 18, \ ! 17, 16, 15, 14, 61, 60, 59, 58, \ ! 57, 56, 55, 54, 30, 31, 1, 32} ! ! /* Switch between the leaf and non-leaf orderings. The purpose is to avoid ! write-over scoreboard delays between caller and callee. */ ! #define ORDER_REGS_FOR_LOCAL_ALLOC \ ! { \ ! static int leaf[] = REG_LEAF_ALLOC_ORDER; \ ! static int nonleaf[] = REG_ALLOC_ORDER; \ ! \ ! bcopy (regs_ever_live[1] ? nonleaf : leaf, reg_alloc_order, \ ! FIRST_PSEUDO_REGISTER * sizeof (int)); \ ! } /*** Register Classes ***/ *************** *** 587,594 **** class that represents their union. */ ! /* The m88100 hardware has one kind of register. However, we denote the arg pointer as a separate class. */ ! enum reg_class { NO_REGS, AP_REG, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES --- 740,748 ---- class that represents their union. */ ! /* The m88000 hardware has two kinds of registers. In addition, we denote the arg pointer as a separate class. */ ! enum reg_class { NO_REGS, AP_REG, XRF_REGS, GENERAL_REGS, AGRF_REGS, ! XGRF_REGS, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES *************** *** 595,599 **** /* Give names of register classes as strings for dump file. */ ! #define REG_CLASS_NAMES {"NO_REGS", "AP_REG", "GENERAL_REGS", "ALL_REGS" } /* Define which registers fit in which classes. --- 749,754 ---- /* Give names of register classes as strings for dump file. */ ! #define REG_CLASS_NAMES {"NO_REGS", "AP_REG", "XRF_REGS", "GENERAL_REGS", \ ! "AGRF_REGS", "XGRF_REGS", "ALL_REGS" } /* Define which registers fit in which classes. *************** *** 600,604 **** This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ ! #define REG_CLASS_CONTENTS {0, 1, -2, -1} /* The same information, inverted: --- 755,765 ---- This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ ! #define REG_CLASS_CONTENTS {{0x00000000, 0x00000000}, \ ! {0x00000001, 0x00000000}, \ ! {0x00000000, 0xffffffff}, \ ! {0xfffffffe, 0x00000000}, \ ! {0xffffffff, 0x00000000}, \ ! {0xfffffffe, 0xffffffff}, \ ! {0xffffffff, 0xffffffff}} /* The same information, inverted: *************** *** 606,618 **** reg number REGNO. This could be a conditional expression or could index an array. */ ! #define REGNO_REG_CLASS(REGNO) ((REGNO) ? GENERAL_REGS : AP_REG) /* The class value for index registers, and the one for base regs. */ ! #define BASE_REG_CLASS ALL_REGS #define INDEX_REG_CLASS GENERAL_REGS ! /* Get reg_class from a letter such as appears in the machine description. */ ! ! #define REG_CLASS_FROM_LETTER(C) NO_REGS /* Macros to check register numbers against specific register classes. --- 767,782 ---- reg number REGNO. This could be a conditional expression or could index an array. */ ! #define REGNO_REG_CLASS(REGNO) \ ! ((REGNO) ? ((REGNO < 32) ? GENERAL_REGS : XRF_REGS) : AP_REG) /* The class value for index registers, and the one for base regs. */ ! #define BASE_REG_CLASS AGRF_REGS #define INDEX_REG_CLASS GENERAL_REGS ! /* Get reg_class from a letter such as appears in the machine description. ! For the 88000, the following class/letter is defined for the XRF: ! x - Extended register file */ ! #define REG_CLASS_FROM_LETTER(C) \ ! (((C) == 'x') ? XRF_REGS : NO_REGS) /* Macros to check register numbers against specific register classes. *************** *** 622,631 **** Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. */ ! #define REGNO_OK_FOR_BASE_P(REGNO) \ ! ((REGNO) < FIRST_PSEUDO_REGISTER || \ ! (unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER) ! #define REGNO_OK_FOR_INDEX_P(REGNO) \ ! (((REGNO) && (REGNO) < FIRST_PSEUDO_REGISTER) || \ ! (unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER) /* Given an rtx X being reloaded into a reg required to be --- 786,795 ---- Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. */ ! #define REGNO_OK_FOR_BASE_P(REGNO) \ ! ((REGNO) < FIRST_EXTENDED_REGISTER \ ! || (unsigned) reg_renumber[REGNO] < FIRST_EXTENDED_REGISTER) ! #define REGNO_OK_FOR_INDEX_P(REGNO) \ ! (((REGNO) && (REGNO) < FIRST_EXTENDED_REGISTER) \ ! || (unsigned) reg_renumber[REGNO] < FIRST_EXTENDED_REGISTER) /* Given an rtx X being reloaded into a reg required to be *************** *** 634,643 **** in some cases it is preferable to use a more restrictive class. Double constants should be in a register iff they can be made cheaply. */ ! #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ ! #define CLASS_MAX_NREGS(CLASS, MODE) \ ! ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* Letters in the range `I' through `P' in a register constraint string can --- 798,809 ---- in some cases it is preferable to use a more restrictive class. Double constants should be in a register iff they can be made cheaply. */ ! #define PREFERRED_RELOAD_CLASS(X,CLASS) \ ! (CONSTANT_P(X) && (CLASS == XRF_REGS) ? NO_REGS : (CLASS)) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ ! #define CLASS_MAX_NREGS(CLASS, MODE) \ ! ((((CLASS) == XRF_REGS) ? 1 \ ! : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) /* Letters in the range `I' through `P' in a register constraint string can *************** *** 1222,1225 **** --- 1388,1396 ---- {"pc_or_label_ref", {PC, LABEL_REF}}, + /* The case table contains either words or branch instructions. This says + which. We always claim that the vector is PC-relative. It is position + independent when -fpic is used. */ + #define CASE_VECTOR_INSNS (TARGET_88100 || flag_pic) + /* An alias for a machine mode name. This is the machine mode that elements of a jump-table should have. */ *************** *** 1326,1329 **** --- 1497,1505 ---- #define FUNCTION_MODE SImode + /* A barrier will be aligned so account for the possible expansion. */ + #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ + if (GET_CODE (INSN) == BARRIER) \ + LENGTH += 1; + /* Compute the cost of computing a constant rtl expression RTX whose rtx-code is CODE. The body of this macro is a portion *************** *** 1339,1343 **** won't do anything in cse, but it will cause expand_binop to pass the constant to the define_expands). */ ! #define CONST_COSTS(RTX,CODE) \ case CONST_INT: \ if (SMALL_INT (RTX)) \ --- 1515,1519 ---- won't do anything in cse, but it will cause expand_binop to pass the constant to the define_expands). */ ! #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ if (SMALL_INT (RTX)) \ *************** *** 1373,1377 **** /* Provide the costs of a rtl expression. This is in the body of a switch on CODE. */ ! #define RTX_COSTS(X,CODE) \ case MEM: \ return COSTS_N_INSNS (2); \ --- 1549,1553 ---- /* Provide the costs of a rtl expression. This is in the body of a switch on CODE. */ ! #define RTX_COSTS(X,CODE,OUTER_CODE) \ case MEM: \ return COSTS_N_INSNS (2); \ *************** *** 1408,1412 **** #undef INT_ASM_OP #undef ASCII_DATA_ASM_OP - #undef INIT_SECTION_ASM_OP #undef CONST_SECTION_ASM_OP #undef CTORS_SECTION_ASM_OP --- 1584,1587 ---- *************** *** 1416,1419 **** --- 1591,1598 ---- #undef TYPE_ASM_OP #undef SIZE_ASM_OP + #undef WEAK_ASM_OP + #undef SET_ASM_OP + #undef SKIP_ASM_OP + #undef COMMON_ASM_OP /* These are used in varasm.c as well. */ *************** *** 1439,1443 **** #define FILE_ASM_OP "file" #define SECTION_ASM_OP "section" ! #define DEF_ASM_OP "def" #define GLOBAL_ASM_OP "global" #define ALIGN_ASM_OP "align" --- 1618,1622 ---- #define FILE_ASM_OP "file" #define SECTION_ASM_OP "section" ! #define SET_ASM_OP "def" #define GLOBAL_ASM_OP "global" #define ALIGN_ASM_OP "align" *************** *** 1444,1448 **** #define SKIP_ASM_OP "zero" #define COMMON_ASM_OP "comm" ! #define LOCAL_ASM_OP "bss" #define FLOAT_ASM_OP "float" #define DOUBLE_ASM_OP "double" --- 1623,1627 ---- #define SKIP_ASM_OP "zero" #define COMMON_ASM_OP "comm" ! #define BSS_ASM_OP "bss" #define FLOAT_ASM_OP "float" #define DOUBLE_ASM_OP "double" *************** *** 1470,1476 **** #define INTERNAL_ASM_OP "local" #define VERSION_ASM_OP "version" - #define ASM_DWARF_POP_SECTION(FILE) fputs ("\tprevious\n", FILE) #define UNALIGNED_SHORT_ASM_OP "uahalf" #define UNALIGNED_INT_ASM_OP "uaword" /* Output any initial stuff to the assembly file. Always put out --- 1649,1656 ---- #define INTERNAL_ASM_OP "local" #define VERSION_ASM_OP "version" #define UNALIGNED_SHORT_ASM_OP "uahalf" #define UNALIGNED_INT_ASM_OP "uaword" + #define PUSHSECTION_ASM_OP "section" + #define POPSECTION_ASM_OP "previous" /* Output any initial stuff to the assembly file. Always put out *************** *** 1543,1547 **** #else #define ASM_OUTPUT_IDENT(FILE, NAME) \ ! fprintf (FILE, "\t%s\t \"%s\"\n", IDENT_ASM_OP, NAME) #endif --- 1723,1727 ---- #else #define ASM_OUTPUT_IDENT(FILE, NAME) \ ! output_ascii (FILE, IDENT_ASM_OP, 4000, NAME, strlen (NAME)); #endif *************** *** 1580,1584 **** "#r8"+1, "#r9"+1, "#r10"+1,"#r11"+1,"#r12"+1,"#r13"+1,"#r14"+1,"#r15"+1,\ "#r16"+1,"#r17"+1,"#r18"+1,"#r19"+1,"#r20"+1,"#r21"+1,"#r22"+1,"#r23"+1,\ ! "#r24"+1,"#r25"+1,"#r26"+1,"#r27"+1,"#r28"+1,"#r29"+1,"#r30"+1,"#r31"+1} /* How to renumber registers for dbx and gdb. */ --- 1760,1768 ---- "#r8"+1, "#r9"+1, "#r10"+1,"#r11"+1,"#r12"+1,"#r13"+1,"#r14"+1,"#r15"+1,\ "#r16"+1,"#r17"+1,"#r18"+1,"#r19"+1,"#r20"+1,"#r21"+1,"#r22"+1,"#r23"+1,\ ! "#r24"+1,"#r25"+1,"#r26"+1,"#r27"+1,"#r28"+1,"#r29"+1,"#r30"+1,"#r31"+1,\ ! "#x0"+1, "#x1"+1, "#x2"+1, "#x3"+1, "#x4"+1, "#x5"+1, "#x6"+1, "#x7"+1, \ ! "#x8"+1, "#x9"+1, "#x10"+1,"#x11"+1,"#x12"+1,"#x13"+1,"#x14"+1,"#x15"+1,\ ! "#x16"+1,"#x17"+1,"#x18"+1,"#x19"+1,"#x20"+1,"#x21"+1,"#x22"+1,"#x23"+1,\ ! "#x24"+1,"#x25"+1,"#x26"+1,"#x27"+1,"#x28"+1,"#x29"+1,"#x30"+1,"#x31"+1} /* How to renumber registers for dbx and gdb. */ *************** *** 1675,1678 **** --- 1859,1863 ---- For V.4, labels use `.' rather than `@'. */ + #undef ASM_OUTPUT_INTERNAL_LABEL #ifdef AS_BUG_DOT_LABELS /* The assembler requires a declaration of local. */ #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ *************** *** 1691,1694 **** --- 1876,1880 ---- with an `*'. */ + #undef ASM_GENERATE_INTERNAL_LABEL #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ sprintf (LABEL, VERSION_0300_SYNTAX ? "*.%s%d" : "*@%s%d", PREFIX, NUM) *************** *** 1768,1777 **** fprintf (FILE, "\t%s\t 0x%x\n", CHAR_ASM_OP, (VALUE)) ! /* The singl-byte pseudo-op is the default. Override svr[34].h. */ #undef ASM_BYTE_OP ! #define ASM_BYTE_OP "\tbyte" #undef ASM_OUTPUT_ASCII #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \ ! output_ascii ((FILE), (P), (SIZE)) /* Epilogue for case labels. This jump instruction is called by casesi --- 1954,1963 ---- fprintf (FILE, "\t%s\t 0x%x\n", CHAR_ASM_OP, (VALUE)) ! /* The single-byte pseudo-op is the default. Override svr[34].h. */ #undef ASM_BYTE_OP ! #define ASM_BYTE_OP "byte" #undef ASM_OUTPUT_ASCII #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \ ! output_ascii (FILE, ASCII_DATA_ASM_OP, 48, P, SIZE) /* Epilogue for case labels. This jump instruction is called by casesi *************** *** 1780,1790 **** #define ASM_OUTPUT_CASE_END(FILE, NUM, TABLE) \ do { \ ! char label[256]; \ ! ASM_GENERATE_INTERNAL_LABEL (label, "L", NUM); \ ! fprintf (FILE, "%se:\n", &label[1]); \ ! if (! flag_delayed_branch) \ ! fprintf (FILE, "\tlda\t %s,%s[%s]\n", reg_names[1], reg_names[1], \ ! reg_names[m88k_case_index]); \ ! fprintf (FILE, "\tjmp\t %s\n", reg_names[1]); \ } while (0) --- 1966,1979 ---- #define ASM_OUTPUT_CASE_END(FILE, NUM, TABLE) \ do { \ ! if (CASE_VECTOR_INSNS) \ ! { \ ! char label[256]; \ ! ASM_GENERATE_INTERNAL_LABEL (label, "L", NUM); \ ! fprintf (FILE, "%se:\n", &label[1]); \ ! if (! flag_delayed_branch) \ ! fprintf (FILE, "\tlda\t %s,%s[%s]\n", reg_names[1], \ ! reg_names[1], reg_names[m88k_case_index]); \ ! fprintf (FILE, "\tjmp\t %s\n", reg_names[1]); \ ! } \ } while (0) *************** *** 1794,1798 **** char buffer[256]; \ ASM_GENERATE_INTERNAL_LABEL (buffer, "L", VALUE); \ ! fprintf (FILE, "\tbr\t %s\n", &buffer[1]); \ } while (0) --- 1983,1988 ---- char buffer[256]; \ ASM_GENERATE_INTERNAL_LABEL (buffer, "L", VALUE); \ ! fprintf (FILE, CASE_VECTOR_INSNS ? "\tbr\t %s\n" : "\tword\t %s\n", \ ! &buffer[1]); \ } while (0) *************** *** 1838,1842 **** #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( fprintf ((FILE), "\t%s\t ", \ ! ((SIZE) ? (SIZE) : 1) <= m88k_gp_threshold ? SBSS_ASM_OP : LOCAL_ASM_OP), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u,%d\n", (SIZE) ? (SIZE) : 1, (SIZE) <= 4 ? 4 : 8)) --- 2028,2032 ---- #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( fprintf ((FILE), "\t%s\t ", \ ! ((SIZE) ? (SIZE) : 1) <= m88k_gp_threshold ? SBSS_ASM_OP : BSS_ASM_OP), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u,%d\n", (SIZE) ? (SIZE) : 1, (SIZE) <= 4 ? 4 : 8)) *************** *** 2109,2112 **** --- 2299,2303 ---- #else /* m88kluna or other not based on svr[34].h. */ + #undef INIT_SECTION_ASM_OP #define EXTRA_SECTIONS in_const, in_tdesc, in_sdata #define CONST_SECTION_FUNCTION \ diff -rc2N gcc-2.1/config/m88k.md gcc-2.2.1/config/m88k.md *** gcc-2.1/config/m88k.md Fri Mar 20 15:12:24 1992 --- gcc-2.2.1/config/m88k.md Fri May 29 13:35:35 1992 *************** *** 29,33 **** [(match_operand:SI 0 "" "")] "" ! "{ static char sccs_id[] = \"@(#)m88k.md 2.0.3.4 20 Mar 1992 15:09:03\"; FAIL; }") --- 29,33 ---- [(match_operand:SI 0 "" "")] "" ! "{ static char sccs_id[] = \"@(#)m88k.md 2.1.11.6 29 May 1992 10:55:49\"; FAIL; }") *************** *** 43,60 **** ; "branch,jump,call, ; flow-control instructions ; load,store,loada, ; data unit instructions ! ; spadd,dpadd,spdiv,dpdiv,idiv, ; FPU add instructions ; spmul,dpmul,imul, ; FPU multiply instructions ! ; arith, ; integer unit instructions ! ; marith,mstore,mfp,weird" ; multi-word instructions ; Classification of each insn. Some insns of TYPE_BRANCH are multi-word. (define_attr "type" ! "branch,jump,call,load,store,loada,spadd,dpadd,spdiv,dpdiv,idiv,spmul,dpmul,imul,arith,marith,mstore,mfp,weird" (const_string "arith")) ; Convenience attributes. (define_attr "fpu" "yes,no" (if_then_else ! (eq_attr "type" "spmul,dpmul,imul,spadd,dpadd,spdiv,dpdiv,idiv,mfp") (const_string "yes") (const_string "no"))) --- 43,68 ---- ; "branch,jump,call, ; flow-control instructions ; load,store,loada, ; data unit instructions ! ; spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv, ; FPU add instructions ; spmul,dpmul,imul, ; FPU multiply instructions ! ; arith,bit,mov ; integer unit instructions ! ; marith,mbit,mfp,weird" ; multi-word instructions ; Classification of each insn. Some insns of TYPE_BRANCH are multi-word. (define_attr "type" ! "branch,jump,call,load,store,loada,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv,spmul,dpmul,imul,arith,bit,mov,marith,mbit,mfp,weird" (const_string "arith")) ; Convenience attributes. + (define_attr "unit" "bit,memory,multiply,divide,fpadd,other" + (cond [(eq_attr "type" "bit,mbit") (const_string "bit") + (eq_attr "type" "load,store") (const_string "memory") + (eq_attr "type" "spmul,dpmul,imul") (const_string "multiply") + (eq_attr "type" "spdiv,dpdiv,idiv") (const_string "divide") + (eq_attr "type" "spadd,dpadd,spcmp,dpcmp,mfp") (const_string "fpadd")] + (const_string "other"))) + (define_attr "fpu" "yes,no" (if_then_else ! (eq_attr "type" "spmul,dpmul,imul,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv,mfp") (const_string "yes") (const_string "no"))) *************** *** 62,66 **** ; are safe. (define_attr "length" "" ! (cond [(eq_attr "type" "marith,mstore,mfp") (const_int 2)] (const_int 1))) --- 70,74 ---- ; are safe. (define_attr "length" "" ! (cond [(eq_attr "type" "marith,mbit,mfp") (const_int 2)] (const_int 1))) *************** *** 81,85 **** [(and (and ! (eq_attr "type" "!branch,jump,call,marith,mstore,mfp,weird") ; required. (eq_attr "type" "!load")) ; issue as-soon-as-possible. (eq_attr "fpu" "no")) ; issue as-soon-as-possible. --- 89,93 ---- [(and (and ! (eq_attr "type" "!branch,jump,call,marith,mbit,mfp,weird") ; required. (eq_attr "type" "!load")) ; issue as-soon-as-possible. (eq_attr "fpu" "no")) ; issue as-soon-as-possible. *************** *** 90,94 **** (define_delay (eq_attr "type" "call") ! [(eq_attr "type" "!branch,call,marith,mstore,mfp,weird") ; required. (nil) (nil)]) --- 98,102 ---- (define_delay (eq_attr "type" "call") ! [(eq_attr "type" "!branch,call,marith,mbit,mfp,weird") ; required. (nil) (nil)]) *************** *** 138,145 **** ; Describing the alu is currently not useful. ;(define_function_unit "alu" 1 0 (eq_attr "type" ! ; "!store,mstore,marith,mfp,weird") 1 0) ! ;(define_function_unit "alu" 1 0 (eq_attr "type" "marith,weird") 2 0) ! (define_function_unit "memory" 1 3 (eq_attr "type" "load") 3 2) ; The fp1 and fplast descriptions currently have no effect. --- 146,161 ---- ; Describing the alu is currently not useful. ;(define_function_unit "alu" 1 0 (eq_attr "type" ! ; "!store,marith,mbit,mfp,weird") 1 0) ! ;(define_function_unit "alu" 1 0 (eq_attr "type" "marith,mbit,weird") 2 0) ! (define_function_unit "alu" 1 0 ! (and (eq_attr "type" "loada,arith,bit,mov") (eq_attr "cpu" "!m88100")) 2 0) ! (define_function_unit "alu" 1 0 ! (and (eq_attr "type" "marith,mbit,weird") (eq_attr "cpu" "!m88100")) 4 0) ! ! (define_function_unit "memory" 1 3 ! (and (eq_attr "type" "load") (eq_attr "cpu" "m88100")) 3 2) ! (define_function_unit "memory" 1 3 ! (and (eq_attr "type" "load") (eq_attr "cpu" "!m88100")) 4 2) ; The fp1 and fplast descriptions currently have no effect. *************** *** 150,162 **** ; is the total latency. A range denotes a group of instructions and/or ; conditions (the extra clock of fplast time with some sequences). ! (define_function_unit "fpmul" 1 4 (eq_attr "type" "spmul") 4 2) ; 6-8 ! (define_function_unit "fpmul" 1 4 (eq_attr "type" "dpmul,mfp") 7 2) ; 9-10 ! (define_function_unit "fpmul" 1 4 (eq_attr "type" "imul") 3 2) ; 4 ! ! (define_function_unit "fpadd" 1 3 (eq_attr "type" "spadd") 3 2) ; 5-6 ! (define_function_unit "fpadd" 1 3 (eq_attr "type" "dpadd") 4 2) ; 6-7 ! (define_function_unit "fpadd" 1 3 (eq_attr "type" "spdiv") 30 2) ; 30-31 ! (define_function_unit "fpadd" 1 3 (eq_attr "type" "dpdiv") 60 2) ; 60-61 ! (define_function_unit "fpadd" 1 3 (eq_attr "type" "idiv") 38 2) ; 38 ;(define_function_unit "fplast" 1 1 (eq_attr "fpu" "yes") 1 2) --- 166,201 ---- ; is the total latency. A range denotes a group of instructions and/or ; conditions (the extra clock of fplast time with some sequences). ! (define_function_unit "fpmul" 1 4 ! (and (eq_attr "type" "spmul") (eq_attr "cpu" "m88100")) 4 2) ; 6-8 ! (define_function_unit "fpmul" 1 4 ! (and (eq_attr "type" "dpmul,mfp") (eq_attr "cpu" "m88100")) 7 2) ; 9-10 ! (define_function_unit "fpmul" 1 4 ! (and (eq_attr "type" "imul") (eq_attr "cpu" "m88100")) 3 2) ; 4 ! ! (define_function_unit "fpmul" 1 4 ! (and (eq_attr "type" "imul,spmul,dpmul,mfp") ! (eq_attr "cpu" "!m88100")) 6 2) ; 3 ! ! (define_function_unit "fpadd" 1 3 ! (and (eq_attr "type" "spadd,spcmp") (eq_attr "cpu" "m88100")) 3 2) ; 5-6 ! (define_function_unit "fpadd" 1 3 ! (and (eq_attr "type" "dpadd,dpcmp") (eq_attr "cpu" "m88100")) 4 2) ; 6-7 ! (define_function_unit "fpadd" 1 3 ! (and (eq_attr "type" "spdiv") (eq_attr "cpu" "m88100")) 30 2) ; 30-31 ! (define_function_unit "fpadd" 1 3 ! (and (eq_attr "type" "dpdiv") (eq_attr "cpu" "m88100")) 60 2) ; 60-61 ! (define_function_unit "fpadd" 1 3 ! (and (eq_attr "type" "idiv") (eq_attr "cpu" "m88100")) 38 2) ; 38 ! ! (define_function_unit "fpadd" 1 3 ! (and (eq_attr "type" "spadd,dpadd") (eq_attr "cpu" "!m88100")) 6 2) ; 3 ! (define_function_unit "fpadd" 1 3 ! (and (eq_attr "type" "spcmp,dpcmp") (eq_attr "cpu" "!m88100")) 2 2) ; 3 ! (define_function_unit "fpadd" 1 3 ! (and (eq_attr "type" "spdiv") (eq_attr "cpu" "!m88100")) 26 2) ; 13 ! (define_function_unit "fpadd" 1 3 ! (and (eq_attr "type" "dpdiv") (eq_attr "cpu" "!m88100")) 46 2) ; 23 ! (define_function_unit "fpadd" 1 3 ! (and (eq_attr "type" "idiv") (eq_attr "cpu" "!m88100")) 36 2) ; 18 ;(define_function_unit "fplast" 1 1 (eq_attr "fpu" "yes") 1 2) *************** *** 164,168 **** ; Describing writeback contention is currently not useful. ;(define_function_unit "writeback" 1 1 ! ; (eq_attr "type" "!store,mstore,branch,jump,call") 0 1) ; Describing stores is currently not useful. The suggestion here is that the --- 203,207 ---- ; Describing writeback contention is currently not useful. ;(define_function_unit "writeback" 1 1 ! ; (eq_attr "type" "!store,branch,jump,call") 0 1) ; Describing stores is currently not useful. The suggestion here is that the *************** *** 169,174 **** ; function unit ordering has already been established (writeback is last) and ; that store insns use the units in an unusual order. ! ;(define_function_unit "writeback" 1 1 (eq_attr "type" "store,mstore") 0 1) ! ;(define_function_unit "memory" 1 3 (eq_attr "type" "store,mstore") 1 2) ;; This rich set of complex patterns are mostly due to Torbjorn Granlund --- 208,213 ---- ; function unit ordering has already been established (writeback is last) and ; that store insns use the units in an unusual order. ! ;(define_function_unit "writeback" 1 1 (eq_attr "type" "store") 0 1) ! ;(define_function_unit "memory" 1 3 (eq_attr "type" "store") 1 2) ;; This rich set of complex patterns are mostly due to Torbjorn Granlund *************** *** 195,199 **** INTVAL (operands[3]) - INTVAL (operands[2])); return \"ext %0,%1,%w3<%4>\"; /* <(%3-%2)> */ ! }") (define_insn "" --- 234,239 ---- INTVAL (operands[3]) - INTVAL (operands[2])); return \"ext %0,%1,%w3<%4>\"; /* <(%3-%2)> */ ! }" ! [(set_attr "type" "bit")]) (define_insn "" *************** *** 208,212 **** INTVAL (operands[3]) - INTVAL (operands[2])); return \"extu %0,%1,%w3<%4>\"; /* <(%3-%2)> */ ! }") ;; Optimize possible cases of the set instruction. --- 248,253 ---- INTVAL (operands[3]) - INTVAL (operands[2])); return \"extu %0,%1,%w3<%4>\"; /* <(%3-%2)> */ ! }" ! [(set_attr "type" "bit")]) ;; Optimize possible cases of the set instruction. *************** *** 217,221 **** (match_operand:SI 1 "register_operand" "r")))] "" ! "set %0,%#r0,%1") (define_insn "" --- 258,263 ---- (match_operand:SI 1 "register_operand" "r")))] "" ! "set %0,%#r0,%1" ! [(set_attr "type" "bit")]) (define_insn "" *************** *** 225,229 **** (match_operand:SI 2 "register_operand" "r")))] "" ! "set %0,%2,%1") (define_insn "" --- 267,272 ---- (match_operand:SI 2 "register_operand" "r")))] "" ! "set %0,%2,%1" ! [(set_attr "type" "bit")]) (define_insn "" *************** *** 233,237 **** (match_operand:SI 2 "register_operand" "r"))))] "" ! "set %0,%1,%2") ;; Optimize possible cases of the mak instruction. --- 276,281 ---- (match_operand:SI 2 "register_operand" "r"))))] "" ! "set %0,%1,%2" ! [(set_attr "type" "bit")]) ;; Optimize possible cases of the mak instruction. *************** *** 249,253 **** >> INTVAL(operands[2])))); return \"mak %0,%1,%4<%2>\"; ! }") ;; Optimize possible cases of output_and. --- 293,298 ---- >> INTVAL(operands[2])))); return \"mak %0,%1,%4<%2>\"; ! }" ! [(set_attr "type" "bit")]) ;; Optimize possible cases of output_and. *************** *** 267,271 **** return output_and (operands); }" ! [(set_attr "type" "marith")]) ; length is 1 or 2. ;; Recognize bcnd instructions for integer values. This is distinguished --- 312,316 ---- return output_and (operands); }" ! [(set_attr "type" "marith")]) ; arith,bit,marith. length is 1 or 2. ;; Recognize bcnd instructions for integer values. This is distinguished *************** *** 664,703 **** (define_insn "" ! [(set (match_operand:CC 0 "register_operand" "=r,r") ! (compare:CC (match_operand:SF 1 "register_operand" "r,r") ! (match_operand:SF 2 "real_or_0_operand" "r,G")))] "" "@ fcmp.sss %0,%1,%2 ! fcmp.sss %0,%1,%#r0" ! [(set_attr "type" "spadd")]) (define_insn "" ! [(set (match_operand:CC 0 "register_operand" "=r") ! (compare:CC (match_operand:DF 1 "register_operand" "r") (float_extend:DF ! (match_operand:SF 2 "register_operand" "r"))))] "" "fcmp.sds %0,%1,%2" ! [(set_attr "type" "dpadd")]) (define_insn "" ! [(set (match_operand:CC 0 "register_operand" "=r") (compare:CC (float_extend:DF ! (match_operand:SF 1 "register_operand" "r")) ! (match_operand:DF 2 "register_operand" "r")))] "" "fcmp.ssd %0,%1,%2" ! [(set_attr "type" "dpadd")]) (define_insn "" ! [(set (match_operand:CC 0 "register_operand" "=r,r") ! (compare:CC (match_operand:DF 1 "register_operand" "r,r") ! (match_operand:DF 2 "real_or_0_operand" "r,G")))] "" "@ fcmp.sdd %0,%1,%2 ! fcmp.sds %0,%1,%#r0" ! [(set_attr "type" "dpadd")]) ;; Store condition code insns. The compare insns set a register --- 709,752 ---- (define_insn "" ! [(set (match_operand:CC 0 "register_operand" "=r,r,r,r") ! (compare:CC (match_operand:SF 1 "register_operand" "r,r,x,x") ! (match_operand:SF 2 "real_or_0_operand" "r,G,x,G")))] "" "@ fcmp.sss %0,%1,%2 ! fcmp.sss %0,%1,%#r0 ! fcmp.sss %0,%1,%2 ! fcmp.sss %0,%1,%#x0" ! [(set_attr "type" "spcmp")]) (define_insn "" ! [(set (match_operand:CC 0 "register_operand" "=r,r") ! (compare:CC (match_operand:DF 1 "register_operand" "r,x") (float_extend:DF ! (match_operand:SF 2 "register_operand" "r,x"))))] "" "fcmp.sds %0,%1,%2" ! [(set_attr "type" "dpcmp")]) (define_insn "" ! [(set (match_operand:CC 0 "register_operand" "=r,r") (compare:CC (float_extend:DF ! (match_operand:SF 1 "register_operand" "r,x")) ! (match_operand:DF 2 "register_operand" "r,x")))] "" "fcmp.ssd %0,%1,%2" ! [(set_attr "type" "dpcmp")]) (define_insn "" ! [(set (match_operand:CC 0 "register_operand" "=r,r,r,r") ! (compare:CC (match_operand:DF 1 "register_operand" "r,r,x,x") ! (match_operand:DF 2 "real_or_0_operand" "r,G,x,G")))] "" "@ fcmp.sdd %0,%1,%2 ! fcmp.sds %0,%1,%#r0 ! fcmp.sdd %0,%1,%2 ! fcmp.sds %0,%1,%#x0" ! [(set_attr "type" "dpcmp")]) ;; Store condition code insns. The compare insns set a register *************** *** 705,708 **** --- 754,759 ---- ;; for the special treatment of cmpsi with a constant operand. + ;; @@ For the m88110, use fcmpu for bxx sxx inequality comparisons. + (define_expand "seq" [(set (match_operand:SI 0 "register_operand" "") *************** *** 773,777 **** (const_int 0)]))] "" ! "ext %0,%2,1<%C1>") (define_insn "" --- 824,829 ---- (const_int 0)]))] "" ! "ext %0,%2,1<%C1>" ! [(set_attr "type" "bit")]) (define_insn "" *************** *** 782,786 **** (const_int 0)])))] "" ! "extu %0,%2,1<%C1>") ;; Conditional branch insns. The compare insns set a register --- 834,839 ---- (const_int 0)])))] "" ! "extu %0,%2,1<%C1>" ! [(set_attr "type" "bit")]) ;; Conditional branch insns. The compare insns set a register *************** *** 948,952 **** (match_operand 3 "pc_or_label_ref" "")))] "" ! "bb1%. %R3%C0,%1,%P2%P3" [(set_attr "type" "branch")]) --- 1001,1011 ---- (match_operand 3 "pc_or_label_ref" "")))] "" ! "* ! { ! if (mostly_false_jump (insn, operands[0])) ! return \"bb0%. %R2%C0,%1,%P2%P3\"; ! else ! return \"bb1%. %R3%C0,%1,%P2%P3\"; ! }" [(set_attr "type" "branch")]) *************** *** 964,969 **** (define_insn "" ! [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r") ! (match_operand:SI 1 "move_operand" "rI,m,rO,J,M"))] "(register_operand (operands[0], SImode) || register_operand (operands[1], SImode) --- 1023,1028 ---- (define_insn "" ! [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,x,x,x,m") ! (match_operand:SI 1 "move_operand" "rI,m,rO,J,M,x,r,x,m,x"))] "(register_operand (operands[0], SImode) || register_operand (operands[1], SImode) *************** *** 974,979 **** st %r1,%0 subu %0,%#r0,%n1 ! set %0,%#r0,%s1" ! [(set_attr "type" "arith,load,store,arith,arith")]) (define_insn "" --- 1033,1043 ---- st %r1,%0 subu %0,%#r0,%n1 ! set %0,%#r0,%s1 ! mov.s %0,%1 ! mov.s %0,%1 ! mov %0,%1 ! ld %0,%1 ! st %1,%0" ! [(set_attr "type" "arith,load,store,arith,bit,mov,mov,mov,load,store")]) (define_insn "" *************** *** 987,991 **** set %0,%#r0,%s1 or.u %0,%#r0,%X1\;or %0,%0,%x1" ! [(set_attr "type" "arith,arith,arith,arith,marith")]) ;; @@ Why the constraint "in"? Doesn't `i' include `n'? --- 1051,1055 ---- set %0,%#r0,%s1 or.u %0,%#r0,%X1\;or %0,%0,%x1" ! [(set_attr "type" "arith,arith,arith,bit,marith")]) ;; @@ Why the constraint "in"? Doesn't `i' include `n'? *************** *** 1080,1092 **** (define_insn "" ! [(set (match_operand:DI 0 "register_operand" "=r") (const_int 0))] "" ! "or %0,%#r0,0\;or %d0,%#r0,0" ! [(set_attr "type" "marith")]) (define_insn "" ! [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m") ! (match_operand:DI 1 "nonimmediate_operand" "r,m,r"))] "" "@ --- 1144,1158 ---- (define_insn "" ! [(set (match_operand:DI 0 "register_operand" "=r,x") (const_int 0))] "" ! "@ ! or %0,%#r0,0\;or %d0,%#r0,0 ! mov %0,%#x0" ! [(set_attr "type" "marith,mov")]) (define_insn "" ! [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,x,x,x,m") ! (match_operand:DI 1 "nonimmediate_operand" "r,m,r,x,r,x,m,x"))] "" "@ *************** *** 1093,1098 **** or %0,%#r0,%1\;or %d0,%#r0,%d1 ld.d %0,%1 st.d %1,%0" ! [(set_attr "type" "marith,load,store")]) (define_insn "" --- 1159,1169 ---- or %0,%#r0,%1\;or %d0,%#r0,%d1 ld.d %0,%1 + st.d %1,%0 + mov.d %0,%1 + mov.d %0,%1 + mov %0,%1 + ld.d %0,%1 st.d %1,%0" ! [(set_attr "type" "marith,load,store,mov,mov,mov,load,store")]) (define_insn "" *************** *** 1146,1158 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") (const_int 0))] "" ! "or %0,%#r0,0\;or %d0,%#r0,0" ! [(set_attr "type" "marith")]) (define_insn "" ! [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m") ! (match_operand:DF 1 "nonimmediate_operand" "r,m,r"))] "" "@ --- 1217,1231 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") (const_int 0))] "" ! "@ ! or %0,%#r0,0\;or %d0,%#r0,0 ! mov %0,%#x0" ! [(set_attr "type" "marith,mov")]) (define_insn "" ! [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,x,r,x,x,m") ! (match_operand:DF 1 "nonimmediate_operand" "r,m,r,r,x,x,m,x"))] "" "@ *************** *** 1159,1164 **** or %0,%#r0,%1\;or %d0,%#r0,%d1 ld.d %0,%1 st.d %1,%0" ! [(set_attr "type" "marith,load,store")]) (define_insn "" --- 1232,1242 ---- or %0,%#r0,%1\;or %d0,%#r0,%d1 ld.d %0,%1 + st.d %1,%0 + mov.d %0,%1 + mov.d %0,%1 + mov %0,%1 + ld.d %0,%1 st.d %1,%0" ! [(set_attr "type" "marith,load,store,mov,mov,mov,load,store")]) (define_insn "" *************** *** 1191,1202 **** ;; @@ What happens to fconst0_rtx? (define_insn "" ! [(set (match_operand:SF 0 "register_operand" "=r") (const_int 0))] "" ! "or %0,%#r0,0") (define_insn "" ! [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m") ! (match_operand:SF 1 "nonimmediate_operand" "r,m,r"))] "" "@ --- 1269,1283 ---- ;; @@ What happens to fconst0_rtx? (define_insn "" ! [(set (match_operand:SF 0 "register_operand" "=r,x") (const_int 0))] "" ! "@ ! or %0,%#r0,0 ! mov %0,%#x0" ! [(set_attr "type" "arith,mov")]) (define_insn "" ! [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,x,r,x,x,m") ! (match_operand:SF 1 "nonimmediate_operand" "r,m,r,r,x,x,m,x"))] "" "@ *************** *** 1203,1208 **** or %0,%#r0,%1 ld %0,%1 st %r1,%0" ! [(set_attr "type" "arith,load,store")]) (define_insn "" --- 1284,1294 ---- or %0,%#r0,%1 ld %0,%1 + st %r1,%0 + mov.s %0,%1 + mov.s %0,%1 + mov %0,%1 + ld %0,%1 st %r1,%0" ! [(set_attr "type" "arith,load,store,mov,mov,mov,load,store")]) (define_insn "" *************** *** 1245,1249 **** ;; operand 4 is the first value to be loaded ;; operand 5 is the register to hold the value (r4 or r5) - ;; Upon completion, r2 and r3 are unchanged (define_expand "call_block_move" --- 1331,1334 ---- *************** *** 1256,1266 **** (use (reg:SI 2)) (use (reg:SI 3)) ! (use (reg:SI 4)) ! (use (reg:SI 5)) (parallel [(call (mem:SI (match_operand 0 "" "")) (const_int 0)) ! (use (reg:SI 1))]) ! (clobber (reg:SI 4)) ! (clobber (reg:SI 5))] "" "") --- 1341,1348 ---- (use (reg:SI 2)) (use (reg:SI 3)) ! (use (match_dup 5)) (parallel [(call (mem:SI (match_operand 0 "" "")) (const_int 0)) ! (clobber (reg:SI 1))])] "" "") *************** *** 1280,1292 **** (use (reg:SI 2)) (use (reg:SI 3)) ! (use (reg:SI 4)) ! (use (reg:SI 5)) (use (reg:SI 6)) (parallel [(call (mem:SI (match_operand 0 "" "")) (const_int 0)) ! (use (reg:SI 1))]) ! (clobber (reg:SI 4)) ! (clobber (reg:SI 5)) ! (clobber (reg:SI 6))] "" "") --- 1362,1370 ---- (use (reg:SI 2)) (use (reg:SI 3)) ! (use (match_dup 5)) (use (reg:SI 6)) (parallel [(call (mem:SI (match_operand 0 "" "")) (const_int 0)) ! (clobber (reg:SI 1))])] "" "") *************** *** 1397,1401 **** subu %0,%#r0,%H1 ld.h %0,%1" ! [(set_attr "type" "arith,arith,arith,load")]) (define_expand "extendqihi2" --- 1475,1479 ---- subu %0,%#r0,%H1 ld.h %0,%1" ! [(set_attr "type" "bit,arith,arith,load")]) (define_expand "extendqihi2" *************** *** 1420,1424 **** subu %0,%#r0,%Q1 ld.b %0,%1" ! [(set_attr "type" "arith,arith,arith,load")]) (define_expand "extendqisi2" --- 1498,1502 ---- subu %0,%#r0,%Q1 ld.b %0,%1" ! [(set_attr "type" "bit,arith,arith,load")]) (define_expand "extendqisi2" *************** *** 1443,1447 **** subu %0,%#r0,%Q1 ld.b %0,%1" ! [(set_attr "type" "arith,arith,arith,load")]) ;; Conversions between float and double. --- 1521,1525 ---- subu %0,%#r0,%Q1 ld.b %0,%1" ! [(set_attr "type" "bit,arith,arith,load")]) ;; Conversions between float and double. *************** *** 1451,1497 **** ;; not preserved. Interestingly, fsub does conform. ! (define_insn "extendsfdf2" [(set (match_operand:DF 0 "register_operand" "=r") (float_extend:DF (match_operand:SF 1 "register_operand" "r")))] "" "fsub.dss %0,%1,%#r0" [(set_attr "type" "spadd")]) ! (define_insn "truncdfsf2" [(set (match_operand:SF 0 "register_operand" "=r") (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))] "" "fsub.sds %0,%1,%#r0" [(set_attr "type" "dpadd")]) ;; Conversions between floating point and integer (define_insn "floatsidf2" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (float:DF (match_operand:SI 1 "register_operand" "r")))] "" "flt.ds %0,%1" ! [(set_attr "type" "spadd")]) (define_insn "floatsisf2" ! [(set (match_operand:SF 0 "register_operand" "=r") ! (float:SF (match_operand:SI 1 "register_operand" "r")))] "" "flt.ss %0,%1" ! [(set_attr "type" "spadd")]) (define_insn "fix_truncdfsi2" ! [(set (match_operand:SI 0 "register_operand" "=r") ! (fix:SI (match_operand:DF 1 "register_operand" "r")))] "" "trnc.sd %0,%1" ! [(set_attr "type" "dpadd")]) (define_insn "fix_truncsfsi2" ! [(set (match_operand:SI 0 "register_operand" "=r") ! (fix:SI (match_operand:SF 1 "register_operand" "r")))] "" "trnc.ss %0,%1" ! [(set_attr "type" "spadd")]) --- 1529,1601 ---- ;; not preserved. Interestingly, fsub does conform. ! (define_expand "extendsfdf2" [(set (match_operand:DF 0 "register_operand" "=r") (float_extend:DF (match_operand:SF 1 "register_operand" "r")))] "" + "") + + (define_insn "" + [(set (match_operand:DF 0 "register_operand" "=r") + (float_extend:DF (match_operand:SF 1 "register_operand" "r")))] + "! TARGET_88110" "fsub.dss %0,%1,%#r0" [(set_attr "type" "spadd")]) ! (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")))] ! "TARGET_88110" ! "fcvt.ds %0,%1" ! [(set_attr "type" "spadd")]) ! ! (define_expand "truncdfsf2" [(set (match_operand:SF 0 "register_operand" "=r") (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))] "" + "") + + (define_insn "" + [(set (match_operand:SF 0 "register_operand" "=r") + (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))] + "! TARGET_88110" "fsub.sds %0,%1,%#r0" [(set_attr "type" "dpadd")]) + (define_insn "" + [(set (match_operand:SF 0 "register_operand" "=r,x") + (float_truncate:SF (match_operand:DF 1 "register_operand" "r,x")))] + "TARGET_88110" + "fcvt.sd %0,%1" + [(set_attr "type" "dpadd")]) + ;; Conversions between floating point and integer (define_insn "floatsidf2" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (float:DF (match_operand:SI 1 "register_operand" "r,r")))] "" "flt.ds %0,%1" ! [(set_attr "type" "spadd,dpadd")]) (define_insn "floatsisf2" ! [(set (match_operand:SF 0 "register_operand" "=r,x") ! (float:SF (match_operand:SI 1 "register_operand" "r,r")))] "" "flt.ss %0,%1" ! [(set_attr "type" "spadd,spadd")]) (define_insn "fix_truncdfsi2" ! [(set (match_operand:SI 0 "register_operand" "=r,x") ! (fix:SI (match_operand:DF 1 "register_operand" "r,r")))] "" "trnc.sd %0,%1" ! [(set_attr "type" "dpadd,dpadd")]) (define_insn "fix_truncsfsi2" ! [(set (match_operand:SI 0 "register_operand" "=r,x") ! (fix:SI (match_operand:SF 1 "register_operand" "r,r")))] "" "trnc.ss %0,%1" ! [(set_attr "type" "spadd,dpadd")]) *************** *** 1540,1546 **** (define_expand "adddf3" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (plus:DF (match_operand:DF 1 "general_operand" "%r") ! (match_operand:DF 2 "general_operand" "r")))] "" " --- 1644,1650 ---- (define_expand "adddf3" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (plus:DF (match_operand:DF 1 "general_operand" "%r,x") ! (match_operand:DF 2 "general_operand" "r,x")))] "" " *************** *** 1551,1557 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r")) ! (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))] "" "fadd.dss %0,%1,%2" --- 1655,1661 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) ! (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fadd.dss %0,%1,%2" *************** *** 1559,1565 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (plus:DF (match_operand:DF 1 "register_operand" "r") ! (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))] "" "fadd.dds %0,%1,%2" --- 1663,1669 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (plus:DF (match_operand:DF 1 "register_operand" "r,x") ! (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fadd.dds %0,%1,%2" *************** *** 1567,1573 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r")) ! (match_operand:DF 2 "register_operand" "r")))] "" "fadd.dsd %0,%1,%2" --- 1671,1677 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) ! (match_operand:DF 2 "register_operand" "r,x")))] "" "fadd.dsd %0,%1,%2" *************** *** 1575,1581 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (plus:DF (match_operand:DF 1 "register_operand" "%r") ! (match_operand:DF 2 "register_operand" "r")))] "" "fadd.ddd %0,%1,%2" --- 1679,1685 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (plus:DF (match_operand:DF 1 "register_operand" "%r,x") ! (match_operand:DF 2 "register_operand" "r,x")))] "" "fadd.ddd %0,%1,%2" *************** *** 1583,1589 **** (define_insn "addsf3" ! [(set (match_operand:SF 0 "register_operand" "=r") ! (plus:SF (match_operand:SF 1 "register_operand" "%r") ! (match_operand:SF 2 "register_operand" "r")))] "" "fadd.sss %0,%1,%2" --- 1687,1693 ---- (define_insn "addsf3" ! [(set (match_operand:SF 0 "register_operand" "=r,x") ! (plus:SF (match_operand:SF 1 "register_operand" "%r,x") ! (match_operand:SF 2 "register_operand" "r,x")))] "" "fadd.sss %0,%1,%2" *************** *** 1631,1637 **** (define_expand "subdf3" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (minus:DF (match_operand:DF 1 "general_operand" "r") ! (match_operand:DF 2 "general_operand" "r")))] "" " --- 1735,1741 ---- (define_expand "subdf3" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (minus:DF (match_operand:DF 1 "general_operand" "r,x") ! (match_operand:DF 2 "general_operand" "r,x")))] "" " *************** *** 1642,1648 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (minus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r")) ! (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))] "" "fsub.dss %0,%1,%2" --- 1746,1752 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (minus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) ! (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fsub.dss %0,%1,%2" *************** *** 1650,1656 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (minus:DF (match_operand:DF 1 "register_operand" "r") ! (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))] "" "fsub.dds %0,%1,%2" --- 1754,1760 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (minus:DF (match_operand:DF 1 "register_operand" "r,x") ! (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fsub.dds %0,%1,%2" *************** *** 1658,1664 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (minus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r")) ! (match_operand:DF 2 "register_operand" "r")))] "" "fsub.dsd %0,%1,%2" --- 1762,1768 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (minus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) ! (match_operand:DF 2 "register_operand" "r,x")))] "" "fsub.dsd %0,%1,%2" *************** *** 1666,1672 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (minus:DF (match_operand:DF 1 "register_operand" "r") ! (match_operand:DF 2 "register_operand" "r")))] "" "fsub.ddd %0,%1,%2" --- 1770,1776 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (minus:DF (match_operand:DF 1 "register_operand" "r,x") ! (match_operand:DF 2 "register_operand" "r,x")))] "" "fsub.ddd %0,%1,%2" *************** *** 1674,1680 **** (define_insn "subsf3" ! [(set (match_operand:SF 0 "register_operand" "=r") ! (minus:SF (match_operand:SF 1 "register_operand" "r") ! (match_operand:SF 2 "register_operand" "r")))] "" "fsub.sss %0,%1,%2" --- 1778,1784 ---- (define_insn "subsf3" ! [(set (match_operand:SF 0 "register_operand" "=r,x") ! (minus:SF (match_operand:SF 1 "register_operand" "r,x") ! (match_operand:SF 2 "register_operand" "r,x")))] "" "fsub.sss %0,%1,%2" *************** *** 1721,1724 **** --- 1825,1836 ---- [(set_attr "type" "imul")]) + (define_insn "umulsidi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))] + "TARGET_88110" + "mulu.d %0,%1,%2" + [(set_attr "type" "imul")]) + ;; patterns for mixed mode floating point ;; Do not define patterns that utilize mixed mode arithmetic that result *************** *** 1727,1733 **** (define_expand "muldf3" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (mult:DF (match_operand:DF 1 "general_operand" "%r") ! (match_operand:DF 2 "general_operand" "r")))] "" " --- 1839,1845 ---- (define_expand "muldf3" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (mult:DF (match_operand:DF 1 "general_operand" "%r,x") ! (match_operand:DF 2 "general_operand" "r,x")))] "" " *************** *** 1738,1744 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r")) ! (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))] "" "fmul.dss %0,%1,%2" --- 1850,1856 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) ! (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fmul.dss %0,%1,%2" *************** *** 1746,1752 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (mult:DF (match_operand:DF 1 "register_operand" "r") ! (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))] "" "fmul.dds %0,%1,%2" --- 1858,1864 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (mult:DF (match_operand:DF 1 "register_operand" "r,x") ! (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fmul.dds %0,%1,%2" *************** *** 1754,1760 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r")) ! (match_operand:DF 2 "register_operand" "r")))] "" "fmul.dsd %0,%1,%2" --- 1866,1872 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) ! (match_operand:DF 2 "register_operand" "r,x")))] "" "fmul.dsd %0,%1,%2" *************** *** 1762,1768 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (mult:DF (match_operand:DF 1 "register_operand" "%r") ! (match_operand:DF 2 "register_operand" "r")))] "" "fmul.ddd %0,%1,%2" --- 1874,1880 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (mult:DF (match_operand:DF 1 "register_operand" "%r,x") ! (match_operand:DF 2 "register_operand" "r,x")))] "" "fmul.ddd %0,%1,%2" *************** *** 1770,1776 **** (define_insn "mulsf3" ! [(set (match_operand:SF 0 "register_operand" "=r") ! (mult:SF (match_operand:SF 1 "register_operand" "%r") ! (match_operand:SF 2 "register_operand" "r")))] "" "fmul.sss %0,%1,%2" --- 1882,1888 ---- (define_insn "mulsf3" ! [(set (match_operand:SF 0 "register_operand" "=r,x") ! (mult:SF (match_operand:SF 1 "register_operand" "%r,x") ! (match_operand:SF 2 "register_operand" "r,x")))] "" "fmul.sss %0,%1,%2" *************** *** 2061,2067 **** (define_expand "divdf3" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (div:DF (match_operand:DF 1 "general_operand" "r") ! (match_operand:DF 2 "general_operand" "r")))] "" " --- 2173,2179 ---- (define_expand "divdf3" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (div:DF (match_operand:DF 1 "general_operand" "r,x") ! (match_operand:DF 2 "general_operand" "r,x")))] "" " *************** *** 2081,2087 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (div:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r")) ! (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))] "" "fdiv.dss %0,%1,%2" --- 2193,2199 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (div:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) ! (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fdiv.dss %0,%1,%2" *************** *** 2089,2095 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (div:DF (match_operand:DF 1 "register_operand" "r") ! (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))] "" "fdiv.dds %0,%1,%2" --- 2201,2207 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (div:DF (match_operand:DF 1 "register_operand" "r,x") ! (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fdiv.dds %0,%1,%2" *************** *** 2097,2103 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (div:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r")) ! (match_operand:DF 2 "register_operand" "r")))] "" "fdiv.dsd %0,%1,%2" --- 2209,2215 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (div:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) ! (match_operand:DF 2 "register_operand" "r,x")))] "" "fdiv.dsd %0,%1,%2" *************** *** 2105,2111 **** (define_insn "divsf3" ! [(set (match_operand:SF 0 "register_operand" "=r") ! (div:SF (match_operand:SF 1 "register_operand" "r") ! (match_operand:SF 2 "register_operand" "r")))] "" "fdiv.sss %0,%1,%2" --- 2217,2223 ---- (define_insn "divsf3" ! [(set (match_operand:SF 0 "register_operand" "=r,x") ! (div:SF (match_operand:SF 1 "register_operand" "r,x") ! (match_operand:SF 2 "register_operand" "r,x")))] "" "fdiv.sss %0,%1,%2" *************** *** 2113,2119 **** (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r") ! (div:DF (match_operand:DF 1 "register_operand" "r") ! (match_operand:DF 2 "register_operand" "r")))] "" "fdiv.ddd %0,%1,%2" --- 2225,2231 ---- (define_insn "" ! [(set (match_operand:DF 0 "register_operand" "=r,x") ! (div:DF (match_operand:DF 1 "register_operand" "r,x") ! (match_operand:DF 2 "register_operand" "r,x")))] "" "fdiv.ddd %0,%1,%2" *************** *** 2289,2293 **** set %0,%1,%s2 or.u %0,%1,%X2\;or %0,%0,%x2" ! [(set_attr "type" "arith,arith,arith,marith")]) (define_insn "" --- 2401,2405 ---- set %0,%1,%s2 or.u %0,%1,%X2\;or %0,%0,%x2" ! [(set_attr "type" "arith,arith,bit,marith")]) (define_insn "" *************** *** 2509,2513 **** "@ mak %0,%1,%2 ! mak %0,%1,0<%2>") (define_expand "ashrsi3" --- 2621,2626 ---- "@ mak %0,%1,%2 ! mak %0,%1,0<%2>" ! [(set_attr "type" "bit")]) (define_expand "ashrsi3" *************** *** 2553,2557 **** "@ ext %0,%1,%2 ! ext %0,%1,0<%2>") ;;- logical shift instructions. Logical shift left becomes arithmetic --- 2666,2671 ---- "@ ext %0,%1,%2 ! ext %0,%1,0<%2>" ! [(set_attr "type" "bit")]) ;;- logical shift instructions. Logical shift left becomes arithmetic *************** *** 2576,2580 **** "@ mak %0,%1,%2 ! mak %0,%1,0<%2>") (define_expand "lshrsi3" --- 2690,2695 ---- "@ mak %0,%1,%2 ! mak %0,%1,0<%2>" ! [(set_attr "type" "bit")]) (define_expand "lshrsi3" *************** *** 2618,2622 **** "@ extu %0,%1,%2 ! extu %0,%1,0<%2>") ;;- rotate instructions --- 2733,2738 ---- "@ extu %0,%1,%2 ! extu %0,%1,0<%2>" ! [(set_attr "type" "bit")]) ;;- rotate instructions *************** *** 2646,2650 **** (match_operand:SI 2 "arith_operand" "rI")))] "" ! "rot %0,%1,%2") ;; Bit field instructions. --- 2762,2767 ---- (match_operand:SI 2 "arith_operand" "rI")))] "" ! "rot %0,%1,%2" ! [(set_attr "type" "bit")]) ;; Bit field instructions. *************** *** 2669,2673 **** (32 - INTVAL (operands[2])) - INTVAL (operands[3])); return \"ext %0,%1,%2<%4>\"; /* <(32-%2-%3)> */ ! }") (define_insn "" --- 2786,2791 ---- (32 - INTVAL (operands[2])) - INTVAL (operands[3])); return \"ext %0,%1,%2<%4>\"; /* <(32-%2-%3)> */ ! }" ! [(set_attr "type" "bit")]) (define_insn "" *************** *** 2690,2694 **** (32 - INTVAL (operands[2])) - INTVAL (operands[3])); return \"extu %0,%1,%2<%4>\"; /* <(32-%2-%3)> */ ! }") (define_insn "" --- 2808,2813 ---- (32 - INTVAL (operands[2])) - INTVAL (operands[3])); return \"extu %0,%1,%2<%4>\"; /* <(32-%2-%3)> */ ! }" ! [(set_attr "type" "bit")]) (define_insn "" *************** *** 2703,2707 **** (32 - INTVAL (operands[1])) - INTVAL (operands[2])); return \"clr %0,%0,%1<%3>\"; /* <(32-%1-%2)> */ ! }") (define_insn "" --- 2822,2827 ---- (32 - INTVAL (operands[1])) - INTVAL (operands[2])); return \"clr %0,%0,%1<%3>\"; /* <(32-%1-%2)> */ ! }" ! [(set_attr "type" "bit")]) (define_insn "" *************** *** 2716,2720 **** (32 - INTVAL (operands[1])) - INTVAL (operands[2])); return \"set %0,%0,%1<%3>\"; /* <(32-%1-%2)> */ ! }") (define_insn "" --- 2836,2841 ---- (32 - INTVAL (operands[1])) - INTVAL (operands[2])); return \"set %0,%0,%1<%3>\"; /* <(32-%1-%2)> */ ! }" ! [(set_attr "type" "bit")]) (define_insn "" *************** *** 2755,2762 **** (define_insn "" ! [(set (match_operand:SF 0 "register_operand" "=r") ! (float_truncate:SF (neg:DF (match_operand:DF 1 "register_operand" "r"))))] "" ! "fsub.ssd %0,%#r0,%1" [(set_attr "type" "dpadd")]) --- 2876,2885 ---- (define_insn "" ! [(set (match_operand:SF 0 "register_operand" "=r,x") ! (float_truncate:SF (neg:DF (match_operand:DF 1 "register_operand" "r,x"))))] "" ! "@ ! fsub.ssd %0,%#r0,%1 ! fsub.ssd %0,%#x0,%1" [(set_attr "type" "dpadd")]) *************** *** 2823,2826 **** --- 2946,2957 ---- register rtx index_diff = gen_reg_rtx (SImode); register rtx low = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[1])); + register rtx label = gen_rtx (LABEL_REF, VOIDmode, operands[3]); + register rtx base; + + if (! CASE_VECTOR_INSNS) + /* These instructions are likely to be scheduled and made loop invariant. + This decreases the cost of the dispatch at the expense of the default + case. */ + base = force_reg (SImode, memory_address_noforce (SImode, label)); /* Compute the index difference and handle the default case. */ *************** *** 2829,2842 **** ADD_INT (low) ? low : force_reg (SImode, low))); emit_insn (gen_cmpsi (index_diff, operands[2])); emit_jump_insn (gen_bgtu (operands[4])); ! /* Call the jump that will branch to the appropriate case. */ ! emit_jump_insn (gen_casesi_enter (gen_rtx (LABEL_REF, VOIDmode, operands[3]), ! index_diff, ! operands[3])); ! /* Claim that flow drops into the table so it will be adjacent. */ DONE; }") ;; The bsr.n instruction is directed to the END of the table. See ;; ASM_OUTPUT_CASE_END. --- 2960,2988 ---- ADD_INT (low) ? low : force_reg (SImode, low))); emit_insn (gen_cmpsi (index_diff, operands[2])); + /* It's possible to replace this branch with sgtu/iorsi3 and adding a -1 + entry to the table. However, that doesn't seem to win on the m88110. */ emit_jump_insn (gen_bgtu (operands[4])); ! if (CASE_VECTOR_INSNS) ! /* Call the jump that will branch to the appropriate case. */ ! emit_jump_insn (gen_casesi_enter (label, index_diff, operands[3])); ! else ! /* Load the table entry and jump to it. */ ! emit_jump_insn (gen_casesi_jump (gen_reg_rtx (SImode), base, index_diff)); ! ! /* Claim that flow drops into the table so it will be adjacent by not ! emitting a barrier. */ DONE; }") + (define_expand "casesi_jump" + [(set (match_operand:SI 0 "" "") + (mem:SI (plus:SI (match_operand:SI 1 "" "") + (mult:SI (match_operand:SI 2 "" "") + (const_int 4))))) + (set (pc) (match_dup 0))] + "" + "") + ;; The bsr.n instruction is directed to the END of the table. See ;; ASM_OUTPUT_CASE_END. *************** *** 2864,2868 **** [(parallel [(call (match_operand:SI 0 "" "") (match_operand 1 "" "")) ! (use (reg:SI 1))])] "" " --- 3010,3014 ---- [(parallel [(call (match_operand:SI 0 "" "") (match_operand 1 "" "")) ! (clobber (reg:SI 1))])] "" " *************** *** 2877,2881 **** [(parallel [(call (mem:SI (match_operand:SI 0 "call_address_operand" "rQ")) (match_operand 1 "" "")) ! (use (reg:SI 1))])] "" "* return output_call (operands, operands[0]);" --- 3023,3027 ---- [(parallel [(call (mem:SI (match_operand:SI 0 "call_address_operand" "rQ")) (match_operand 1 "" "")) ! (clobber (reg:SI 1))])] "" "* return output_call (operands, operands[0]);" *************** *** 2886,2890 **** (call (match_operand:SI 1 "" "") (match_operand 2 "" ""))) ! (use (reg:SI 1))])] "" " --- 3032,3036 ---- (call (match_operand:SI 1 "" "") (match_operand 2 "" ""))) ! (clobber (reg:SI 1))])] "" " *************** *** 2901,2905 **** (match_operand:SI 1 "call_address_operand" "rQ")) (match_operand 2 "" ""))) ! (use (reg:SI 1))])] "" "* return output_call (operands, operands[1]);" --- 3047,3051 ---- (match_operand:SI 1 "call_address_operand" "rQ")) (match_operand 2 "" ""))) ! (clobber (reg:SI 1))])] "" "* return output_call (operands, operands[1]);" *************** *** 2911,2915 **** [(const_int 0)] "" ! "ff0 %#r0,%#r0") (define_insn "return" --- 3057,3062 ---- [(const_int 0)] "" ! "ff0 %#r0,%#r0" ! [(set_attr "type" "bit")]) (define_insn "return" *************** *** 2917,2921 **** "null_epilogue ()" "jmp%. %#r1" ! [(set_attr "type" "branch")]) (define_insn "indirect_jump" --- 3064,3068 ---- "null_epilogue ()" "jmp%. %#r1" ! [(set_attr "type" "jump")]) (define_insn "indirect_jump" *************** *** 2923,2927 **** "" "jmp%. %0" ! [(set_attr "type" "branch")]) (define_insn "jump" --- 3070,3074 ---- "" "jmp%. %0" ! [(set_attr "type" "jump")]) (define_insn "jump" diff -rc2N gcc-2.1/config/m88kluna.h gcc-2.2.1/config/m88kluna.h *** gcc-2.1/config/m88kluna.h Thu Jan 23 09:10:45 1992 --- gcc-2.2.1/config/m88kluna.h Thu Apr 9 11:34:25 1992 *************** *** 26,29 **** --- 26,30 ---- #endif #define DBX_DEBUGGING_INFO + #define DEFAULT_GDB_EXTENSIONS 0 #include "aoutos.h" diff -rc2N gcc-2.1/config/m88kv3.h gcc-2.2.1/config/m88kv3.h *** gcc-2.1/config/m88kv3.h Thu Mar 19 15:40:28 1992 --- gcc-2.2.1/config/m88kv3.h Mon Apr 13 13:26:01 1992 *************** *** 70,80 **** #define HAVE_ATEXIT - #if (STACK_BOUNDARY / BITS_PER_UNIT) == 16 && REG_PARM_STACK_SPACE (0) == 32 #define CTOR_LIST_BEGIN \ asm (INIT_SECTION_ASM_OP); \ ! asm ("\tsubu\t r31,r31,16"); \ ! asm ("\tst\t r0,r31,32"); #define CTOR_LIST_END - #endif /* ASM_OUTPUT_CONSTRUCTOR outputs code into the .init section to push the --- 70,78 ---- #define HAVE_ATEXIT #define CTOR_LIST_BEGIN \ asm (INIT_SECTION_ASM_OP); \ ! asm ("\tsubu\t r31,r31,16"); /* (STACK_BOUNDARY / BITS_PER_UNIT) == 16 */ \ ! asm ("\tst\t r0,r31,32"); /* REG_PARM_STACK_SPACE (0) == 32 */ #define CTOR_LIST_END /* ASM_OUTPUT_CONSTRUCTOR outputs code into the .init section to push the diff -rc2N gcc-2.1/config/mips-bsd.h gcc-2.2.1/config/mips-bsd.h *** gcc-2.1/config/mips-bsd.h Sat Mar 21 11:32:39 1992 --- gcc-2.2.1/config/mips-bsd.h Sat Mar 28 17:40:26 1992 *************** *** 50,52 **** --- 50,56 ---- #define TARGET_MEM_FUNCTIONS + /* Override defaults for finding the MIPS tools. */ + #define MD_STARTFILE_PREFIX "/bsd43/usr/lib/cmplrs/cc/" + #define MD_EXEC_PREFIX "/bsd43/usr/lib/cmplrs/cc/" + #include "mips.h" diff -rc2N gcc-2.1/config/mips-g5.h gcc-2.2.1/config/mips-g5.h *** gcc-2.1/config/mips-g5.h --- gcc-2.2.1/config/mips-g5.h Mon Apr 27 15:27:54 1992 *************** *** 0 **** --- 1,22 ---- + /* Definitions of target machine for GNU compiler. Sony RISC NEWS (mips) + System V using encapsulated stabs. + Copyright (C) 1992 Free Software Foundation, Inc. + + This file is part of GNU CC. + + GNU CC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GNU CC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GNU CC; see the file COPYING. If not, write to + the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + #include "mips-news5.h" diff -rc2N gcc-2.1/config/mips-gbsd.h gcc-2.2.1/config/mips-gbsd.h *** gcc-2.1/config/mips-gbsd.h Sat Mar 21 14:30:37 1992 --- gcc-2.2.1/config/mips-gbsd.h Sat Mar 28 17:42:03 1992 *************** *** 20,22 **** #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG ! #include "mips-gbsd.h" --- 20,22 ---- #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG ! #include "mips-bsd.h" diff -rc2N gcc-2.1/config/mips-n5.h gcc-2.2.1/config/mips-n5.h *** gcc-2.1/config/mips-n5.h Sat Mar 21 11:56:51 1992 --- gcc-2.2.1/config/mips-n5.h Sat Jun 6 15:01:23 1992 *************** *** 52,54 **** --- 52,73 ---- #define NM_FLAGS "-Bp" + /* Generate calls to memcpy, etc., not bcopy, etc. */ + #define TARGET_MEM_FUNCTIONS + + /* Mips System V.4 doesn't have a getpagesize() function needed by the + trampoline code, so use the POSIX sysconf function to get it. + This is only done when compiling the trampoline code. */ + + #ifdef L_trampoline + #include + #include + + #ifdef _SC_PAGE_SIZE + #define getpagesize() sysconf(_SC_PAGE_SIZE) + + #else /* older rev of OS */ + #define getpagesize() (NBPC) + #endif /* !_SC_PAGE_SIZE */ + #endif /* L_trampoline */ + #include "mips.h" diff -rc2N gcc-2.1/config/mips-svr4.h gcc-2.2.1/config/mips-svr4.h *** gcc-2.1/config/mips-svr4.h Sat Mar 21 16:50:37 1992 --- gcc-2.2.1/config/mips-svr4.h Fri Apr 10 18:10:54 1992 *************** *** 47,49 **** --- 47,70 ---- #define MACHINE_TYPE "RISC-OS System V.4 Mips" + /* Override defaults for finding the MIPS tools. */ + #define MD_STARTFILE_PREFIX "/svr4/usr/lib/cmplrs/cc/" + #define MD_EXEC_PREFIX "/svr4/usr/lib/cmplrs/cc/" + + /* Mips System V.4 doesn't have a getpagesize() function needed by the + trampoline code, so use the POSIX sysconf function to get it. + This is only done when compiling the trampoline code. */ + + #ifdef L_trampoline + #include + + #define getpagesize() sysconf(_SC_PAGE_SIZE) + #endif /* L_trampoline */ + + /* Use atexit for static constructors/destructors, instead of defining + our own exit function. */ + #define HAVE_ATEXIT + + /* Generate calls to memcpy, etc., not bcopy, etc. */ + #define TARGET_MEM_FUNCTIONS + #include "mips.h" diff -rc2N gcc-2.1/config/mips-sysv.h gcc-2.2.1/config/mips-sysv.h *** gcc-2.1/config/mips-sysv.h Sat Mar 21 11:36:58 1992 --- gcc-2.2.1/config/mips-sysv.h Sat Jun 6 15:01:45 1992 *************** *** 47,49 **** --- 47,72 ---- #define MACHINE_TYPE "RISC-OS System V Mips" + /* Override defaults for finding the MIPS tools. */ + #define MD_STARTFILE_PREFIX "/sysv/usr/lib/cmplrs/cc/" + #define MD_EXEC_PREFIX "/sysv/usr/lib/cmplrs/cc/" + + /* Mips System V doesn't have a getpagesize() function needed by the + trampoline code, so use the POSIX sysconf function to get it. + This is only done when compiling the trampoline code. */ + + #ifdef L_trampoline + #include + #include + + #ifdef _SC_PAGE_SIZE + #define getpagesize() sysconf(_SC_PAGE_SIZE) + + #else /* older rev of OS */ + #define getpagesize() (NBPC) + #endif /* !_SC_PAGE_SIZE */ + #endif /* L_trampoline */ + + /* Generate calls to memcpy, etc., not bcopy, etc. */ + #define TARGET_MEM_FUNCTIONS + #include "mips.h" diff -rc2N gcc-2.1/config/mips.c gcc-2.2.1/config/mips.c *** gcc-2.1/config/mips.c Sat Mar 21 18:33:19 1992 --- gcc-2.2.1/config/mips.c Sat Jun 6 20:50:06 1992 *************** *** 51,55 **** #endif ! #ifdef USG #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */ #else --- 51,55 ---- #endif ! #if defined(USG) || defined(NO_STAB_H) #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */ #else *************** *** 78,81 **** --- 78,82 ---- extern rtx gen_movsi_ulw (); extern rtx gen_movsi_usw (); + extern rtx gen_movstrsi_internal (); extern rtx gen_addsi3 (); extern rtx gen_iorsi3 (); *************** *** 94,97 **** --- 95,116 ---- extern char *language_string; + /* Enumeration for all of the relational tests, so that we can build + arrays indexed by the test type, and not worry about the order + of EQ, NE, etc. */ + + enum internal_test { + ITEST_EQ, + ITEST_NE, + ITEST_GT, + ITEST_GE, + ITEST_LT, + ITEST_LE, + ITEST_GTU, + ITEST_GEU, + ITEST_LTU, + ITEST_LEU, + ITEST_MAX + }; + /* Global variables for machine-dependent things. */ *************** *** 136,142 **** } *extern_head = 0; - /* Name of the current function. */ - char *current_function_name; - /* Name of the file containing the current function. */ char *current_function_file = ""; --- 155,158 ---- *************** *** 462,465 **** --- 478,491 ---- } + /* Return truth value of whether OP is the FP status register. */ + + int + fpsw_register_operand (op, mode) + rtx op; + enum machine_mode mode; + { + return (GET_CODE (op) == REG && ST_REG_P (REGNO (op))); + } + /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */ *************** *** 590,621 **** } - /* Return true if the address is suitable for function call. */ - - int - call_memory_operand (op, mode) - rtx op; - enum machine_mode mode; - { - rtx addr; - enum rtx_code code; - - if (GET_CODE (op) != MEM) - return FALSE; - - addr = XEXP (op, 0); - code = GET_CODE (addr); - - if (GET_MODE (addr) != FUNCTION_MODE) - return FALSE; - - if (code == REG || code == SUBREG) - return TRUE; - - if (CONSTANT_ADDRESS_P (addr)) - return TRUE; - - return FALSE; - } - /* Return true if the code of this rtx pattern is EQ or NE. */ --- 616,619 ---- *************** *** 686,689 **** --- 684,704 ---- } + + /* Return true if the operand is either the PC or a label_ref. */ + + int + pc_or_label_operand (op, mode) + rtx op; + enum machine_mode mode; + { + if (op == pc_rtx) + return TRUE; + + if (GET_CODE (op) == LABEL_REF) + return TRUE; + + return FALSE; + } + /* Return an operand string if the given instruction's delay slot or *************** *** 711,715 **** register int num_nops; ! if (type == DELAY_LOAD) num_nops = 1; --- 726,730 ---- register int num_nops; ! if (type == DELAY_LOAD || type == DELAY_FCMP) num_nops = 1; *************** *** 1030,1034 **** { delay = DELAY_LOAD; ! return "mtc1\t%z1,%0"; } } --- 1045,1049 ---- { delay = DELAY_LOAD; ! ret = "mtc1\t%z1,%0"; } } *************** *** 1075,1079 **** { delay = DELAY_LOAD; ! ret = "la\t%0,%a1\t\t# pic reference"; } else --- 1090,1095 ---- { delay = DELAY_LOAD; ! ret = "lw\t%0,%2\t\t# pic reference"; ! operands[2] = HALF_PIC_PTR (op1); } else *************** *** 1463,1466 **** --- 1479,1691 ---- + /* Make normal rtx_code into something we can index from an array */ + + static enum internal_test + map_test_to_internal_test (test_code) + enum rtx_code test_code; + { + enum internal_test test = ITEST_MAX; + + switch (test_code) + { + case EQ: test = ITEST_EQ; break; + case NE: test = ITEST_NE; break; + case GT: test = ITEST_GT; break; + case GE: test = ITEST_GE; break; + case LT: test = ITEST_LT; break; + case LE: test = ITEST_LE; break; + case GTU: test = ITEST_GTU; break; + case GEU: test = ITEST_GEU; break; + case LTU: test = ITEST_LTU; break; + case LEU: test = ITEST_LEU; break; + } + + return test; + } + + + /* Generate the code to compare two integer values. The return value is: + (reg:SI xx) The pseudo register the comparison is in + (const_int 0) The comparison is always false + (const_int 1) The comparison is always true + (rtx)0 No register, generate a simple branch. */ + + rtx + gen_int_relational (test_code, result, cmp0, cmp1, p_invert) + enum rtx_code test_code; /* relational test (EQ, etc) */ + rtx result; /* result to store comp. or 0 if branch */ + rtx cmp0; /* first operand to compare */ + rtx cmp1; /* second operand to compare */ + int *p_invert; /* NULL or ptr to hold whether branch needs */ + /* to reserse it's test */ + { + struct cmp_info { + enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */ + int const_low; /* low bound of constant we can accept */ + int const_high; /* high bound of constant we can accept */ + int const_add; /* constant to add (convert LE -> LT) */ + int reverse_regs; /* reverse registers in test */ + int invert_const; /* != 0 if invert value if cmp1 is constant */ + int invert_reg; /* != 0 if invert value if cmp1 is register */ + }; + + static struct cmp_info info[ (int)ITEST_MAX ] = { + + { XOR, 0, 65535, 0, 0, 0, 0 }, /* EQ */ + { XOR, 0, 65535, 0, 0, 1, 1 }, /* NE */ + { LT, -32769, 32766, 1, 1, 1, 0 }, /* GT */ + { LT, -32768, 32767, 0, 0, 1, 1 }, /* GE */ + { LT, -32768, 32767, 0, 0, 0, 0 }, /* LT */ + { LT, -32769, 32766, 1, 1, 0, 1 }, /* LE */ + { LTU, -32769, 32766, 1, 1, 1, 0 }, /* GTU */ + { LTU, -32768, 32767, 0, 0, 1, 1 }, /* GEU */ + { LTU, -32768, 32767, 0, 0, 0, 0 }, /* LTU */ + { LTU, -32769, 32766, 1, 1, 0, 1 }, /* LEU */ + }; + + enum internal_test test; + struct cmp_info *p_info; + int branch_p; + int eqne_p; + int invert; + rtx reg; + rtx reg2; + + test = map_test_to_internal_test (test_code); + if (test == ITEST_MAX) + abort (); + + p_info = &info[ (int)test ]; + eqne_p = (p_info->test_code == XOR); + + /* See if the test is always true or false. */ + if ((GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG) + && GET_CODE (cmp1) == CONST_INT) + { + int value = INTVAL (cmp1); + rtx truth = (rtx)0; + + if (test == ITEST_GEU && value == 0) + truth = const1_rtx; + + else if (test == ITEST_LTU && value == 0) + truth = const0_rtx; + + else if (!TARGET_INT64) + { + if (test == ITEST_LTU && value == -1) + truth = const1_rtx; + + else if (test == ITEST_GTU && value == -1) + truth = const0_rtx; + + else if (test == ITEST_LEU && value == -1) + truth = const1_rtx; + + else if (test == ITEST_GT && value == 0x7fffffff) + truth = const0_rtx; + + else if (test == ITEST_LE && value == 0x7fffffff) + truth = const1_rtx; + + else if (test == ITEST_LT && value == 0x80000000) + truth = const0_rtx; + + else if (test == ITEST_GE && value == 0x80000000) + truth = const1_rtx; + } + + if (truth != (rtx)0) + { + if (result != (rtx)0) + emit_move_insn (result, truth); + + return truth; + } + } + + /* Eliminate simple branches */ + branch_p = (result == (rtx)0); + if (branch_p) + { + if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG) + { + /* Comparisons against zero are simple branches */ + if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0) + return (rtx)0; + + /* Test for beq/bne. */ + if (eqne_p) + return (rtx)0; + } + + /* allocate a psuedo to calculate the value in. */ + result = gen_reg_rtx (SImode); + } + + /* Make sure we can handle any constants given to us. */ + if (GET_CODE (cmp0) == CONST_INT) + cmp0 = force_reg (SImode, cmp0); + + if (GET_CODE (cmp1) == CONST_INT) + { + int value = INTVAL (cmp1); + if (value < p_info->const_low || value > p_info->const_high) + cmp1 = force_reg (SImode, cmp1); + } + + /* See if we need to invert the result. */ + invert = (GET_CODE (cmp1) == CONST_INT) + ? p_info->invert_const + : p_info->invert_reg; + + if (p_invert != (int *)0) + { + *p_invert = invert; + invert = FALSE; + } + + /* Comparison to constants, may involve adding 1 to change a LT into LE. + Comparison between two registers, may involve switching operands. */ + if (GET_CODE (cmp1) == CONST_INT) + { + if (p_info->const_add != 0) + cmp1 = gen_rtx (CONST_INT, VOIDmode, INTVAL (cmp1) + p_info->const_add); + } + else if (p_info->reverse_regs) + { + rtx temp = cmp0; + cmp0 = cmp1; + cmp1 = temp; + } + + if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0) + reg = cmp0; + else + { + reg = (invert || eqne_p) ? gen_reg_rtx (SImode) : result; + emit_move_insn (reg, gen_rtx (p_info->test_code, SImode, cmp0, cmp1)); + } + + if (test == ITEST_NE) + { + emit_move_insn (result, gen_rtx (GTU, SImode, reg, const0_rtx)); + invert = FALSE; + } + + else if (test == ITEST_EQ) + { + reg2 = (invert) ? gen_reg_rtx (SImode) : result; + emit_move_insn (reg2, gen_rtx (LTU, SImode, reg, const1_rtx)); + reg = reg2; + } + + if (invert) + emit_move_insn (result, gen_rtx (XOR, SImode, reg, const1_rtx)); + + return result; + } + + /* Emit the common code for doing conditional branches. operand[0] is the label to jump to. *************** *** 1472,1505 **** enum rtx_code test_code; { ! enum { ! I_EQ, ! I_NE, ! I_GT, ! I_GE, ! I_LT, ! I_LE, ! I_GTU, ! I_GEU, ! I_LTU, ! I_LEU, ! I_MAX ! } test = I_MAX; ! ! static enum machine_mode mode_map[(int)CMP_MAX][(int)I_MAX] = { { /* CMP_SI */ ! CC_EQmode, /* eq */ ! CC_EQmode, /* ne */ ! CCmode, /* gt */ ! CCmode, /* ge */ ! CCmode, /* lt */ ! CCmode, /* le */ ! CCmode, /* gtu */ ! CCmode, /* geu */ ! CCmode, /* ltu */ ! CCmode, /* leu */ }, { /* CMP_SF */ CC_FPmode, /* eq */ ! CC_FPmode, /* ne */ CC_FPmode, /* gt */ CC_FPmode, /* ge */ --- 1697,1716 ---- enum rtx_code test_code; { ! static enum machine_mode mode_map[(int)CMP_MAX][(int)ITEST_MAX] = { { /* CMP_SI */ ! SImode, /* eq */ ! SImode, /* ne */ ! SImode, /* gt */ ! SImode, /* ge */ ! SImode, /* lt */ ! SImode, /* le */ ! SImode, /* gtu */ ! SImode, /* geu */ ! SImode, /* ltu */ ! SImode, /* leu */ }, { /* CMP_SF */ CC_FPmode, /* eq */ ! CC_REV_FPmode, /* ne */ CC_FPmode, /* gt */ CC_FPmode, /* ge */ *************** *** 1513,1517 **** { /* CMP_DF */ CC_FPmode, /* eq */ ! CC_FPmode, /* ne */ CC_FPmode, /* gt */ CC_FPmode, /* ge */ --- 1724,1728 ---- { /* CMP_DF */ CC_FPmode, /* eq */ ! CC_REV_FPmode, /* ne */ CC_FPmode, /* gt */ CC_FPmode, /* ge */ *************** *** 1526,1556 **** enum machine_mode mode; ! enum cmp_type type = branch_type; ! rtx cmp0 = branch_cmp[0]; ! rtx cmp1 = branch_cmp[1]; ! rtx label = gen_rtx (LABEL_REF, VOIDmode, operands[0]); ! ! /* Make normal rtx_code into something we can index from an array */ ! switch (test_code) ! { ! case EQ: test = I_EQ; break; ! case NE: test = I_NE; break; ! case GT: test = I_GT; break; ! case GE: test = I_GE; break; ! case LT: test = I_LT; break; ! case LE: test = I_LE; break; ! case GTU: test = I_GTU; break; ! case GEU: test = I_GEU; break; ! case LTU: test = I_LTU; break; ! case LEU: test = I_LEU; break; ! } ! if (test == I_MAX) { ! mode = CCmode; goto fail; } ! /* Get the machine mode to use (CCmode, CC_EQmode, or CC_FPmode). */ mode = mode_map[(int)type][(int)test]; if (mode == VOIDmode) --- 1737,1756 ---- enum machine_mode mode; ! enum cmp_type type = branch_type; ! rtx cmp0 = branch_cmp[0]; ! rtx cmp1 = branch_cmp[1]; ! rtx label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]); ! rtx label2 = pc_rtx; ! rtx reg = (rtx)0; ! int invert = 0; ! enum internal_test test = map_test_to_internal_test (test_code); ! if (test == ITEST_MAX) { ! mode = SImode; goto fail; } ! /* Get the machine mode to use (CCmode, CC_EQmode, CC_FPmode, or CC_REV_FPmode). */ mode = mode_map[(int)type][(int)test]; if (mode == VOIDmode) *************** *** 1563,1600 **** case CMP_SI: ! /* Change >, >=, <, <= tests against 0 to use CC_0mode, since we have ! special instructions to do these tests directly. */ ! ! if (mode == CCmode && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0) { ! emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, cmp0)); ! mode = CC_0mode; } ! else if (mode == CCmode && GET_CODE (cmp0) == CONST_INT && INTVAL (cmp0) == 0) ! { ! emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, cmp1)); ! test_code = reverse_condition (test_code); ! mode = CC_0mode; ! } - else - { - /* force args to register for equality comparisons. */ - if (mode == CC_EQmode && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0) - cmp1 = force_reg (SImode, cmp1); - - emit_insn (gen_rtx (SET, VOIDmode, - cc0_rtx, - gen_rtx (COMPARE, mode, cmp0, cmp1))); - } break; case CMP_DF: - emit_insn (gen_cmpdf_internal (cmp0, cmp1)); - break; - case CMP_SF: ! emit_insn (gen_cmpsf_internal (cmp0, cmp1)); break; } --- 1763,1789 ---- case CMP_SI: ! reg = gen_int_relational (test_code, (rtx)0, cmp0, cmp1, &invert); ! if (reg != (rtx)0) { ! cmp0 = reg; ! cmp1 = const0_rtx; ! test_code = NE; } ! /* Make sure not non-zero constant if ==/!= */ ! else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0) ! cmp1 = force_reg (SImode, cmp1); break; case CMP_DF: case CMP_SF: ! { ! rtx reg = gen_rtx (REG, mode, FPSW_REGNUM); ! emit_insn (gen_rtx (SET, VOIDmode, reg, gen_rtx (test_code, mode, cmp0, cmp1))); ! cmp0 = reg; ! cmp1 = const0_rtx; ! test_code = NE; ! } break; } *************** *** 1601,1610 **** /* Generate the jump */ emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, ! gen_rtx (test_code, mode, cc0_rtx, const0_rtx), ! label, ! pc_rtx))); return; --- 1790,1806 ---- /* Generate the jump */ + if (invert) + { + label2 = label1; + label1 = pc_rtx; + } + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, ! gen_rtx (test_code, mode, cmp0, cmp1), ! label1, ! label2))); ! return; *************** *** 1620,1624 **** static rtx ! block_move_load_store (dest_reg, src_reg, p_bytes, p_offset, align) rtx src_reg; /* register holding source memory addresss */ rtx dest_reg; /* register holding dest. memory addresss */ --- 1816,1820 ---- static rtx ! block_move_load_store (dest_reg, src_reg, p_bytes, p_offset, align, orig_src) rtx src_reg; /* register holding source memory addresss */ rtx dest_reg; /* register holding dest. memory addresss */ *************** *** 1626,1629 **** --- 1822,1826 ---- int *p_offset; /* pointer to current offset */ int align; /* alignment */ + rtx orig_src; /* original source for making a reg note */ { int bytes; /* # bytes remaining */ *************** *** 1634,1637 **** --- 1831,1836 ---- rtx src_addr; /* source address */ rtx dest_addr; /* destination address */ + rtx insn; /* insn of the load */ + rtx orig_src_addr; /* original source address */ rtx (*load_func)(); /* function to generate load insn */ rtx (*store_func)(); /* function to generate destination insn */ *************** *** 1649,1652 **** --- 1848,1854 ---- } + #if 0 + /* Don't generate unligned moves here, rather defer those to the + general movestrsi_internal pattern. */ else if (bytes >= UNITS_PER_WORD) { *************** *** 1656,1659 **** --- 1858,1862 ---- store_func = gen_movsi_usw; } + #endif else if (bytes >= UNITS_PER_SHORT && align >= UNITS_PER_SHORT) *************** *** 1689,1693 **** reg = gen_reg_rtx (mode); ! emit_insn ((*load_func) (reg, gen_rtx (MEM, mode, src_addr))); return (*store_func) (gen_rtx (MEM, mode, dest_addr), reg); } --- 1892,1902 ---- reg = gen_reg_rtx (mode); ! insn = emit_insn ((*load_func) (reg, gen_rtx (MEM, mode, src_addr))); ! orig_src_addr = XEXP (orig_src, 0); ! if (CONSTANT_P (orig_src_addr)) ! REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUIV, ! plus_constant (orig_src_addr, offset), ! REG_NOTES (insn)); ! return (*store_func) (gen_rtx (MEM, mode, dest_addr), reg); } *************** *** 1711,1715 **** static void ! block_move_sequence (dest_reg, src_reg, bytes, align) rtx dest_reg; /* register holding destination address */ rtx src_reg; /* register holding source address */ --- 1920,1924 ---- static void ! block_move_sequence (dest_reg, src_reg, bytes, align, orig_src) rtx dest_reg; /* register holding destination address */ rtx src_reg; /* register holding source address */ *************** *** 1716,1719 **** --- 1925,1929 ---- int bytes; /* # bytes to move */ int align; /* max alignment to assume */ + rtx orig_src; /* original source for making a reg note */ { int offset = 0; *************** *** 1730,1734 **** prev2_store = prev_store; prev_store = cur_store; ! cur_store = block_move_load_store (dest_reg, src_reg, &bytes, &offset, align); } --- 1940,1946 ---- prev2_store = prev_store; prev_store = cur_store; ! cur_store = block_move_load_store (dest_reg, src_reg, ! &bytes, &offset, ! align, orig_src); } *************** *** 1752,1756 **** ... temp = src[MAX_MOVE_REGS-1]; - src += MAX_MOVE_REGS; dest[0] = temp1; dest[1] = temp2; --- 1964,1967 ---- *************** *** 1757,1760 **** --- 1968,1972 ---- ... dest[MAX_MOVE_REGS-1] = temp; + src += MAX_MOVE_REGS; dest += MAX_MOVE_REGS; } while (src != final); *************** *** 1771,1775 **** static void ! block_move_loop (dest_reg, src_reg, bytes, align) rtx dest_reg; /* register holding destination address */ rtx src_reg; /* register holding source address */ --- 1983,1987 ---- static void ! block_move_loop (dest_reg, src_reg, bytes, align, orig_src) rtx dest_reg; /* register holding destination address */ rtx src_reg; /* register holding source address */ *************** *** 1776,1781 **** int bytes; /* # bytes to move */ int align; /* alignment */ { ! rtx stores[MAX_MOVE_REGS]; rtx label; rtx final_src; --- 1988,1996 ---- int bytes; /* # bytes to move */ int align; /* alignment */ + rtx orig_src; /* original source for making a reg note */ { ! rtx dest_mem = gen_rtx (MEM, BLKmode, dest_reg); ! rtx src_mem = gen_rtx (MEM, BLKmode, src_reg); ! rtx align_rtx = gen_rtx (CONST_INT, VOIDmode, align); rtx label; rtx final_src; *************** *** 1783,1787 **** int i; int leftover; - int offset; if (bytes < 2*MAX_MOVE_BYTES) --- 1998,2001 ---- *************** *** 1805,1817 **** emit_label (label); ! offset = 0; ! for (i = 0; i < MAX_MOVE_REGS; i++) ! stores[i] = block_move_load_store (dest_reg, src_reg, &bytes, &offset, align); ! ! emit_insn (gen_addsi3 (src_reg, src_reg, gen_rtx (CONST_INT, VOIDmode, MAX_MOVE_BYTES))); ! for (i = 0; i < MAX_MOVE_REGS; i++) ! emit_insn (stores[i]); ! ! emit_insn (gen_addsi3 (dest_reg, dest_reg, gen_rtx (CONST_INT, VOIDmode, MAX_MOVE_BYTES))); emit_insn (gen_cmpsi (src_reg, final_src)); emit_jump_insn (gen_bne (label)); --- 2019,2026 ---- emit_label (label); ! bytes_rtx = gen_rtx (CONST_INT, VOIDmode, MAX_MOVE_BYTES); ! emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx)); ! emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx)); ! emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx)); emit_insn (gen_cmpsi (src_reg, final_src)); emit_jump_insn (gen_bne (label)); *************** *** 1818,1822 **** if (leftover) ! block_move_sequence (dest_reg, src_reg, leftover, align); } --- 2027,2033 ---- if (leftover) ! emit_insn (gen_movstrsi_internal (dest_mem, src_mem, ! gen_rtx (CONST_INT, VOIDmode, leftover), ! align_rtx)); } *************** *** 1858,1864 **** { rtx bytes_rtx = operands[2]; int constp = (GET_CODE (bytes_rtx) == CONST_INT); int bytes = (constp ? INTVAL (bytes_rtx) : 0); ! int align = INTVAL (operands[3]); rtx src_reg; rtx dest_reg; --- 2069,2077 ---- { rtx bytes_rtx = operands[2]; + rtx align_rtx = operands[3]; int constp = (GET_CODE (bytes_rtx) == CONST_INT); int bytes = (constp ? INTVAL (bytes_rtx) : 0); ! int align = INTVAL (align_rtx); ! rtx orig_src = operands[1]; rtx src_reg; rtx dest_reg; *************** *** 1867,1873 **** return; /* Move the address into scratch registers. */ dest_reg = copy_addr_to_reg (XEXP (operands[0], 0)); ! src_reg = copy_addr_to_reg (XEXP (operands[1], 0)); if (TARGET_MEMCPY) --- 2080,2089 ---- return; + if (align > UNITS_PER_WORD) + align = UNITS_PER_WORD; + /* Move the address into scratch registers. */ dest_reg = copy_addr_to_reg (XEXP (operands[0], 0)); ! src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); if (TARGET_MEMCPY) *************** *** 1874,1882 **** block_move_call (dest_reg, src_reg, bytes_rtx); else if (constp && bytes <= 2*MAX_MOVE_BYTES) ! block_move_sequence (dest_reg, src_reg, bytes, align); else if (constp && align >= UNITS_PER_WORD && optimize) ! block_move_loop (dest_reg, src_reg, bytes, align); else if (constp && optimize) --- 2090,2105 ---- block_move_call (dest_reg, src_reg, bytes_rtx); + #if 0 + else if (constp && bytes <= 3*align) + block_move_sequence (dest_reg, src_reg, bytes, align, orig_src); + #endif + else if (constp && bytes <= 2*MAX_MOVE_BYTES) ! emit_insn (gen_movstrsi_internal (gen_rtx (MEM, BLKmode, dest_reg), ! gen_rtx (MEM, BLKmode, src_reg), ! bytes_rtx, align_rtx)); else if (constp && align >= UNITS_PER_WORD && optimize) ! block_move_loop (dest_reg, src_reg, bytes, align, orig_src); else if (constp && optimize) *************** *** 1899,1903 **** /* Unaligned loop. */ ! block_move_loop (dest_reg, src_reg, bytes, 1); emit_jump_insn (gen_jump (join_label)); emit_barrier (); --- 2122,2126 ---- /* Unaligned loop. */ ! block_move_loop (dest_reg, src_reg, bytes, 1, orig_src); emit_jump_insn (gen_jump (join_label)); emit_barrier (); *************** *** 1905,1909 **** /* Aligned loop. */ emit_label (aligned_label); ! block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD); emit_label (join_label); --- 2128,2132 ---- /* Aligned loop. */ emit_label (aligned_label); ! block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_src); emit_label (join_label); *************** *** 1910,1914 **** /* Bytes at the end of the loop. */ if (leftover) ! block_move_sequence (dest_reg, src_reg, leftover, align); } --- 2133,2148 ---- /* Bytes at the end of the loop. */ if (leftover) ! { ! #if 0 ! if (leftover <= 3*align) ! block_move_sequence (dest_reg, src_reg, leftover, align, orig_src); ! ! else ! #endif ! emit_insn (gen_movstrsi_internal (gen_rtx (MEM, BLKmode, dest_reg), ! gen_rtx (MEM, BLKmode, src_reg), ! gen_rtx (CONST_INT, VOIDmode, leftover), ! gen_rtx (CONST_INT, VOIDmode, align))); ! } } *************** *** 1918,1921 **** --- 2152,2407 ---- + /* Emit load/stores for a small constant block_move. + + operands[0] is the memory address of the destination. + operands[1] is the memory address of the source. + operands[2] is the number of bytes to move. + operands[3] is the alignment. + operands[4] is a temp register. + operands[5] is a temp register. + ... + operands[3+num_regs] is the last temp register. + + The block move type can be one of the following: + BLOCK_MOVE_NORMAL Do all of the block move. + BLOCK_MOVE_NOT_LAST Do all but the last store. + BLOCK_MOVE_LAST Do just the last store. */ + + char * + output_block_move (insn, operands, num_regs, move_type) + rtx insn; + rtx operands[]; + int num_regs; + enum block_move_type move_type; + { + rtx dest_reg = XEXP (operands[0], 0); + rtx src_reg = XEXP (operands[1], 0); + int bytes = INTVAL (operands[2]); + int align = INTVAL (operands[3]); + int num = 0; + int offset = 0; + int use_lwl_lwr = FALSE; + int last_operand = num_regs+4; + int i; + rtx xoperands[10]; + + struct { + char *load; /* load insn without nop */ + char *load_nop; /* load insn with trailing nop */ + char *store; /* store insn */ + char *final; /* if last_store used: NULL or swr */ + char *last_store; /* last store instruction */ + int offset; /* current offset */ + enum machine_mode mode; /* mode to use on (MEM) */ + } load_store[4]; + + /* Detect a bug in GCC, where it can give us a register + the same as one of the addressing registers. */ + for (i = 4; i < last_operand; i++) + { + if (reg_mentioned_p (operands[i], operands[0]) + || reg_mentioned_p (operands[i], operands[1])) + { + abort_with_insn (insn, "register passed as address and temp register to block move"); + } + } + + /* If we are given global or static addresses, and we would be + emitting a few instructions, try to save time by using a + temporary register for the pointer. */ + if (bytes > 2*align || move_type != BLOCK_MOVE_NORMAL) + { + if (CONSTANT_P (src_reg)) + { + if (TARGET_STATS) + mips_count_memory_refs (operands[1], 1); + + src_reg = operands[ 3 + num_regs-- ]; + if (move_type != BLOCK_MOVE_LAST) + { + xoperands[1] = operands[1]; + xoperands[0] = src_reg; + output_asm_insn ("la\t%0,%1", xoperands); + } + } + + if (CONSTANT_P (dest_reg)) + { + if (TARGET_STATS) + mips_count_memory_refs (operands[0], 1); + + dest_reg = operands[ 3 + num_regs-- ]; + if (move_type != BLOCK_MOVE_LAST) + { + xoperands[1] = operands[0]; + xoperands[0] = dest_reg; + output_asm_insn ("la\t%0,%1", xoperands); + } + } + } + + if (num_regs > (sizeof (load_store) / sizeof (load_store[0]))) + num_regs = (sizeof (load_store) / sizeof (load_store[0])); + + else if (num_regs < 1) + abort (); + + if (TARGET_GAS && move_type != BLOCK_MOVE_LAST && set_noreorder++ == 0) + output_asm_insn (".set\tnoreorder", operands); + + while (bytes > 0) + { + load_store[num].offset = offset; + + if (bytes >= UNITS_PER_WORD && align >= UNITS_PER_WORD) + { + load_store[num].load = "lw\t%0,%1"; + load_store[num].load_nop = "lw\t%0,%1%#"; + load_store[num].store = "sw\t%0,%1"; + load_store[num].last_store = "sw\t%0,%1"; + load_store[num].final = (char *)0; + load_store[num].mode = SImode; + offset += UNITS_PER_WORD; + bytes -= UNITS_PER_WORD; + } + + else if (bytes >= UNITS_PER_WORD) + { + #if BYTES_BIG_ENDIAN + load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2"; + load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#"; + load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2"; + load_store[num].last_store = "swr\t%0,%2"; + load_store[num].final = "swl\t%0,%1"; + #else + load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1"; + load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#"; + load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1"; + load_store[num].last_store = "swr\t%0,%1"; + load_store[num].final = "swl\t%0,%2"; + #endif + load_store[num].mode = SImode; + offset += UNITS_PER_WORD; + bytes -= UNITS_PER_WORD; + use_lwl_lwr = TRUE; + } + + else if (bytes >= UNITS_PER_SHORT && align >= UNITS_PER_SHORT) + { + load_store[num].load = "lh\t%0,%1"; + load_store[num].load_nop = "lh\t%0,%1%#"; + load_store[num].store = "sh\t%0,%1"; + load_store[num].last_store = "sh\t%0,%1"; + load_store[num].final = (char *)0; + load_store[num].offset = offset; + load_store[num].mode = HImode; + offset += UNITS_PER_SHORT; + bytes -= UNITS_PER_SHORT; + } + + else + { + load_store[num].load = "lb\t%0,%1"; + load_store[num].load_nop = "lb\t%0,%1%#"; + load_store[num].store = "sb\t%0,%1"; + load_store[num].last_store = "sb\t%0,%1"; + load_store[num].final = (char *)0; + load_store[num].mode = QImode; + offset++; + bytes--; + } + + if (TARGET_STATS && move_type != BLOCK_MOVE_LAST) + { + dslots_load_total++; + dslots_load_filled++; + + if (CONSTANT_P (src_reg)) + mips_count_memory_refs (src_reg, 1); + + if (CONSTANT_P (dest_reg)) + mips_count_memory_refs (dest_reg, 1); + } + + /* Emit load/stores now if we have run out of registers or are + at the end of the move. */ + + if (++num == num_regs || bytes == 0) + { + /* If only load/store, we need a NOP after the load. */ + if (num == 1) + { + load_store[0].load = load_store[0].load_nop; + if (TARGET_STATS && move_type != BLOCK_MOVE_LAST) + dslots_load_filled--; + } + + if (move_type != BLOCK_MOVE_LAST) + { + for (i = 0; i < num; i++) + { + int offset; + + if (!operands[i+4]) + abort (); + + if (GET_MODE (operands[i+4]) != load_store[i].mode) + operands[i+4] = gen_rtx (REG, load_store[i].mode, REGNO (operands[i+4])); + + offset = load_store[i].offset; + xoperands[0] = operands[i+4]; + xoperands[1] = gen_rtx (MEM, load_store[i].mode, + plus_constant (src_reg, offset)); + + if (use_lwl_lwr) + xoperands[2] = gen_rtx (MEM, load_store[i].mode, + plus_constant (src_reg, UNITS_PER_WORD-1+offset)); + + output_asm_insn (load_store[i].load, xoperands); + } + } + + for (i = 0; i < num; i++) + { + int last_p = (i == num-1 && bytes == 0); + int offset = load_store[i].offset; + + xoperands[0] = operands[i+4]; + xoperands[1] = gen_rtx (MEM, load_store[i].mode, + plus_constant (dest_reg, offset)); + + + if (use_lwl_lwr) + xoperands[2] = gen_rtx (MEM, load_store[i].mode, + plus_constant (dest_reg, UNITS_PER_WORD-1+offset)); + + if (move_type == BLOCK_MOVE_NORMAL) + output_asm_insn (load_store[i].store, xoperands); + + else if (move_type == BLOCK_MOVE_NOT_LAST) + { + if (!last_p) + output_asm_insn (load_store[i].store, xoperands); + + else if (load_store[i].final != (char *)0) + output_asm_insn (load_store[i].final, xoperands); + } + + else if (last_p) + output_asm_insn (load_store[i].last_store, xoperands); + } + + num = 0; /* reset load_store */ + use_lwl_lwr = FALSE; /* reset whether or not we used lwl/lwr */ + } + } + + if (TARGET_GAS && move_type != BLOCK_MOVE_LAST && --set_noreorder == 0) + output_asm_insn (".set\treorder", operands); + + return ""; + } + + /* Argument support functions. */ *************** *** 2235,2241 **** int signo; { ! char print_pid[50]; char *argv[4]; pid_t pid; int status; --- 2721,2728 ---- int signo; { ! char select_pgrp[15]; char *argv[4]; pid_t pid; + pid_t pgrp; int status; *************** *** 2244,2252 **** (current_function_file != (char *)0) ? current_function_file : ""); /* Spawn a ps to tell about current memory usage, etc. */ - sprintf (print_pid, "-p%d,%d", getpid (), getppid ()); argv[0] = "ps"; ! argv[1] = print_pid; ! argv[2] = "-ouser,state,pid,pri,nice,wchan,tt,start,usertime,systime,pcpu,cp,inblock,oublock,vsize,rss,pmem,ucomm"; argv[3] = (char *)0; --- 2731,2744 ---- (current_function_file != (char *)0) ? current_function_file : ""); + pgrp = getpgrp (); + if (pgrp != -1) + sprintf (select_pgrp, "-g%d", pgrp); + else + strcpy (select_pgrp, "-a"); + /* Spawn a ps to tell about current memory usage, etc. */ argv[0] = "ps"; ! argv[1] = "-ouser,pid,pri,nice,usertime,systime,pcpu,cp,inblock,oublock,vsize,rss,pmem,ucomm"; ! argv[2] = select_pgrp; argv[3] = (char *)0; *************** *** 2271,2278 **** (void) signal (SIGQUIT, sigquit); } - - signal (SIGINFO, siginfo); } - #endif /* SIGINFO */ --- 2763,2767 ---- *************** *** 2418,2421 **** --- 2907,2922 ---- #endif + #ifdef _IOLBF + /* If -mstats and -quiet, make stderr line buffered. */ + if (quiet_flag && TARGET_STATS) + { + #ifdef MIPS_BSD43 + setlinebuf (stderr); + #else + setvbuf (stderr, (char *)0, _IOLBF, BUFSIZ); + #endif + #endif + } + /* Set up the classification arrays now. */ mips_rtx_classify[(int)PLUS] = CLASS_ADD_OP; *************** *** 2456,2462 **** mips_char_to_class['h'] = HI_REG; mips_char_to_class['l'] = LO_REG; - mips_char_to_class['s'] = ST_REGS; mips_char_to_class['x'] = MD_REGS; mips_char_to_class['y'] = GR_REGS; /* Set up array to map GCC register number to debug register number. --- 2957,2963 ---- mips_char_to_class['h'] = HI_REG; mips_char_to_class['l'] = LO_REG; mips_char_to_class['x'] = MD_REGS; mips_char_to_class['y'] = GR_REGS; + mips_char_to_class['z'] = ST_REGS; /* Set up array to map GCC register number to debug register number. *************** *** 2490,2496 **** for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) { ! register int temp = FALSE; ! if (GP_REG_P (regno)) temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD)); --- 2991,3000 ---- for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) { ! register int temp; ! ! if (mode == CC_FPmode || mode == CC_REV_FPmode) ! temp = (regno == FPSW_REGNUM); ! else if (GP_REG_P (regno)) temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD)); *************** *** 2497,2503 **** else if (FP_REG_P (regno)) temp = ((TARGET_FLOAT64 || ((regno & 1) == 0)) ! && (TARGET_DEBUG_H_MODE ! || class == MODE_FLOAT ! || class == MODE_COMPLEX_FLOAT)); else if (MD_REG_P (regno)) --- 3001,3007 ---- else if (FP_REG_P (regno)) temp = ((TARGET_FLOAT64 || ((regno & 1) == 0)) ! && (class == MODE_FLOAT ! || class == MODE_COMPLEX_FLOAT ! || (TARGET_DEBUG_H_MODE && class == MODE_INT))); else if (MD_REG_P (regno)) *************** *** 2504,2509 **** temp = (mode == SImode || (regno == MD_REG_FIRST && mode == DImode)); ! else if (ST_REG_P (regno)) ! temp = ((mode == SImode) || (class == MODE_CC)); mips_hard_regno_mode_ok[(int)mode][regno] = temp; --- 3008,3013 ---- temp = (mode == SImode || (regno == MD_REG_FIRST && mode == DImode)); ! else ! temp = FALSE; mips_hard_regno_mode_ok[(int)mode][regno] = temp; *************** *** 2550,2553 **** --- 3054,3058 ---- return offset; } + /* A C compound statement to output to stdio stream STREAM the *************** *** 3073,3079 **** fprintf (stream, "\t.abicalls\n"); - /* put gcc_compiled. in data, not text */ - data_section (); - if (TARGET_GP_OPT) { --- 3578,3581 ---- *************** *** 3106,3109 **** --- 3608,3614 ---- int len; + if (HALF_PIC_P ()) + HALF_PIC_FINISH (file); + if (TARGET_GP_OPT) { *************** *** 3167,3170 **** --- 3672,3714 ---- + /* Output a double precision value to the assembler. If both the + host and target are IEEE, emit the values in hex. */ + + void + mips_output_double (stream, value) + FILE *stream; + REAL_VALUE_TYPE value; + { + #ifdef REAL_VALUE_TO_TARGET_DOUBLE + long value_long[2]; + REAL_VALUE_TO_TARGET_DOUBLE (value, value_long); + + fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n", + value_long[0], value, value_long[1]); + #else + fprintf (stream, "\t.double\t%.20g\n", value); + #endif + } + + + /* Output a single precision value to the assembler. If both the + host and target are IEEE, emit the values in hex. */ + + void + mips_output_float (stream, value) + FILE *stream; + REAL_VALUE_TYPE value; + { + #ifdef REAL_VALUE_TO_TARGET_SINGLE + long value_long; + REAL_VALUE_TO_TARGET_SINGLE (value, value_long); + + fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value); + #else + fprintf (stream, "\t.float\t%.12g\n", value); + #endif + } + + /* Return the bytes needed to compute the frame pointer from the current stack pointer. *************** *** 3748,3752 **** fprintf (stderr, ! "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d\n", current_function_name, (frame_pointer_needed) ? 'y' : 'n', --- 4292,4296 ---- fprintf (stderr, ! "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d", current_function_name, (frame_pointer_needed) ? 'y' : 'n', *************** *** 3760,3763 **** --- 4304,4315 ---- dslots_jump_total, dslots_jump_filled, num_refs[0], num_refs[1], num_refs[2]); + + if (HALF_PIC_NUMBER_PTRS) + fprintf (stderr, " half-pic=%3d", HALF_PIC_NUMBER_PTRS); + + if (HALF_PIC_NUMBER_REFS) + fprintf (stderr, " pic-ref=%3d", HALF_PIC_NUMBER_REFS); + + fputc ('\n', stderr); } *************** *** 3822,3823 **** --- 4374,4376 ---- return (compute_frame_size (get_frame_size ())) == 0; } + diff -rc2N gcc-2.1/config/mips.h gcc-2.2.1/config/mips.h *** gcc-2.1/config/mips.h Sat Mar 21 18:38:23 1992 --- gcc-2.2.1/config/mips.h Fri Jun 5 18:54:24 1992 *************** *** 50,54 **** DELAY_NONE, /* no delay slot */ DELAY_LOAD, /* load from memory delay */ ! DELAY_HILO /* move from/to hi/lo registers */ }; --- 50,55 ---- DELAY_NONE, /* no delay slot */ DELAY_LOAD, /* load from memory delay */ ! DELAY_HILO, /* move from/to hi/lo registers */ ! DELAY_FCMP /* delay after doing c..{d,s} */ }; *************** *** 55,59 **** /* Which processor to schedule for. Since there is no difference between a R2000 and R3000 in terms of the scheduler, we collapse them into ! just an R3000. */ enum processor_type { --- 56,61 ---- /* Which processor to schedule for. Since there is no difference between a R2000 and R3000 in terms of the scheduler, we collapse them into ! just an R3000. The elements of the enumeration must match exactly ! the cpu attribute in the mips.md machine description. */ enum processor_type { *************** *** 64,67 **** --- 66,81 ---- }; + /* Recast the cpu class to be the cpu attribute. */ + #define mips_cpu_attr ((enum attr_cpu)mips_cpu) + + /* Which type of block move to do (whether or not the last store is + split out so it can fill a branch delay slot). */ + + enum block_move_type { + BLOCK_MOVE_NORMAL, /* generate complete block move */ + BLOCK_MOVE_NOT_LAST, /* generate all but last store */ + BLOCK_MOVE_LAST /* generate just the last store */ + }; + extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */ extern char mips_print_operand_punct[]; /* print_operand punctuation chars */ *************** *** 106,110 **** extern int arith32_operand (); extern int arith_operand (); - extern int call_memory_operand (); extern int cmp_op (); extern int cmp2_op (); --- 120,123 ---- *************** *** 113,116 **** --- 126,130 ---- extern int equality_op (); extern int fcmp_op (); + extern int fpsw_register_operand (); extern struct rtx_def * function_arg (); extern void function_arg_advance (); *************** *** 119,122 **** --- 133,137 ---- extern void function_prologue (); extern void gen_conditional_branch (); + extern struct rtx_def * gen_int_relational (); extern void init_cumulative_args (); extern int large_int (); *************** *** 133,140 **** --- 148,159 ---- extern char *mips_move_1word (); extern char *mips_move_2words (); + extern void mips_output_double (); extern int mips_output_external (); + extern void mips_output_float (); extern void mips_output_filename (); extern void mips_output_lineno (); + extern char *output_block_move (); extern void override_options (); + extern int pc_or_label_operand (); extern void print_operand_address (); extern void print_operand (); *************** *** 158,164 **** --- 177,188 ---- #ifndef HALF_PIC_P #define HALF_PIC_P() 0 + #define HALF_PIC_NUMBER_PTRS 0 + #define HALF_PIC_NUMBER_REFS 0 #define HALF_PIC_ENCODE(DECL) + #define HALF_PIC_DECLARE(NAME) #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.") #define HALF_PIC_ADDRESS_P(X) 0 + #define HALF_PIC_PTR(X) X + #define HALF_PIC_FINISH(STREAM) #endif *************** *** 236,239 **** --- 260,266 ---- #define OPTIMIZATION_OPTIONS(LEVEL) \ { \ + flag_no_function_cse = TRUE; \ + flag_gnu_linker = FALSE; \ + \ if (LEVEL) \ { \ *************** *** 376,383 **** #endif - #ifndef CC1PLUS_SPEC - #define CC1PLUS_SPEC "%{!fgnu-binutils: -fno-gnu-binutils}" - #endif - /* Preprocessor specs */ --- 403,406 ---- *************** *** 406,410 **** /* Print subsidiary information on the compiler version in use. */ ! #define MIPS_VERSION "[AL 1.1, MM 14]" #ifndef MACHINE_TYPE --- 429,433 ---- /* Print subsidiary information on the compiler version in use. */ ! #define MIPS_VERSION "[AL 1.1, MM 19]" #ifndef MACHINE_TYPE *************** *** 597,600 **** --- 620,630 ---- #endif + /* Don't use the default definitions, because we don't have gld. + Also, we don't want stabs when generating ECOFF output. + Instead we depend on collect to handle these. */ + + #define ASM_OUTPUT_CONSTRUCTOR(file, name) + #define ASM_OUTPUT_DESTRUCTOR(file, name) + /* Run-time compilation parameters selecting different hardware subsets. */ *************** *** 636,641 **** #define MASK_DEBUG_A 0x20000000 /* don't allow