PARTNO		U304 ;
	NAME		U304 ;
	DATE		May 30, 1990 ;
	REV		3 ;
	DESIGNER	Dave Haynie ;
	COMPANY		Commodore-Amiga ;
	ASSEMBLY	BIGRAM ;
	LOCATION	U304 ;

/************************************************************************/
/*									*/
/* Zorro III BIGRAM DRAM CAS Select					*/
/*									*/
/*	This device controls the CAS strobes, which control DRAM byte	*/
/*	enables and most significant bank. 				*/
/*									*/
/************************************************************************/
/*									*/
/* DEVICE DATA:								*/
/*									*/
/*	Device:		20L8-15						*/
/*	Clock:		NONE						*/
/*	Unused:		NONE						*/
/*									*/
/************************************************************************/
/*									*/
/* REVISION HISTORY:							*/
/*									*/
/*	DBH 05-02:	Original version.				*/
/*	DBH 05-30:	Guarantee column address setup to CAS!		*/
/*									*/
/************************************************************************/

/* INPUTS: */

PIN 1	=	!CASEN	;	/* Normal CAS enable */
PIN 2	=	!DTACK	;	/* Zorro III cycle termination */
PIN 3	=	!REFCAS	;	/* CAS for refresh cycle */
PIN 4	=	!REFACK	;	/* We're in refresh */
PIN 5	=	!DS3	;	/* Zorro III data strobes */
PIN 6	=	!DS2	;
PIN 7	=	!DS1	;
PIN 8	=	!DS0	;
PIN 9	=	 SCRAM	;	/* Using static column memories */
PIN 10	=	 READ	;	/* Zorro III Read enable */
PIN 11	=	 MEG4	;	/* Are we using 4 Meg parts? */
PIN 13	=	!CADDR	;	/* Column Address Valid */
PIN 14	=	 A24	;	/* Address lines */
PIN 23	=	 A22	;

/* OUTPUTS: */

PIN 15	=	!CASL0	;	/* Lower bank CAS */
PIN 16	=	!CASL1	;
PIN 17	=	!CASL2	;
PIN 18	=	!CASL3	;
PIN 19	=	!CASH0	;	/* Upper bank CAS */
PIN 20	=	!CASH1	;
PIN 21	=	!CASH2	;
PIN 22	=	!CASH3	;

/** INTERNAL TERMS: **/

/* The CAS lines are the highest order banking control.  If we're using 
   1 Meg parts, lower is $0000000-$03fffff, upper is $0400000-$07fffff,
   so A22 controls the banking.  If we're using 4 Meg parts, lower is
   $0000000-$0ffffff, upper is $1000000-$1ffffff, so A24 controls the
   banking.  */

lower		= !A24 &  MEG4 & CASEN & CADDR
		# !A22 & !MEG4 & CASEN & CADDR;
upper		=  A24 &  MEG4 & CASEN & CADDR
		#  A22 & !MEG4 & CASEN & CADDR;

/** OUTPUT TERMS: **/

/* The CAS terms are simple.  There are two banks of memory, and the banking
   is controlled as above.  On writes, the data strobes control the particular
   CAS line, and we wait for WRDEL so that data is guaranteed valid on the 
   DRAM bus.  On reads, all CAS lines in a bank are asserted ASAP.  On 
   refresh, all CAS lines are asserted. */

CASL0		= lower & !READ & DS0 
		# lower &  READ
		# REFCAS;

CASL1		= lower & !READ & DS1
		# lower &  READ
		# REFCAS;

CASL2		= lower & !READ & DS2
		# lower &  READ
		# REFCAS;

CASL3		= lower & !READ & DS3
		# lower &  READ
		# REFCAS;

CASH0		= upper & !READ & DS0
		# upper &  READ
		# REFCAS;

CASH1		= upper & !READ & DS1
		# upper &  READ
		# REFCAS;

CASH2		= upper & !READ & DS2
		# upper &  READ
		# REFCAS;

CASH3		= upper & !READ & DS3
		# upper &  READ
		# REFCAS;