PARTNO		U300 ;
	NAME		U300 ;
	DATE		May 24, 1990 ;
	REV		4 ;
	DESIGNER	Dave Haynie ;
	COMPANY		Commodore-Amiga ;
	ASSEMBLY	BIGRAM ;
	LOCATION	U300 ;

/************************************************************************/
/*									*/
/* Zorro III BIGRAM DRAM Timing						*/
/*									*/
/*	This device controls the standard and refresh timing of the	*/
/*	dynamic RAM. Big-Time asynchronicity ahead!  This also controls	*/
/*	banking within a CAS controlled memory bank.			*/
/*									*/
/************************************************************************/
/*									*/
/* DEVICE DATA:								*/
/*									*/
/*	Device:		20L8-10						*/
/*	Clock:		NONE						*/
/*	Unused:		
/*									*/
/************************************************************************/
/*									*/
/* REVISION HISTORY:							*/
/*									*/
/*	DBH 05-02:	Original version.				*/
/*	DBH 05-24:	Hacked refresh logic to remove CAS bounce.	*/
/*	DBH 05-24:	More refresh logic adjustments.			*/
/*	DBH 05-24:	Fixed refresh end-of-cycle.			*/
/*									*/
/************************************************************************/

/* INPUTS: */

PIN 1	=	!RASDEL	;	/* RAS strobe delay */
PIN 2	=	!MUX	;	/* DRAM Address multiplexer */
PIN 3	=	!MTCR	;	/* Multiple cycle request. */
PIN 4	=	!BURST	;	/* We're in burst mode. */
PIN 5	=	 DOE	;	/* Data time */
PIN 6	=	!SLAVE	;	/* The board is responding */
PIN 7	=	!REFACK	;	/* We're servicing a refresh request */
PIN 8	=	 SCRAM	;	/* We're using static column RAM. */
PIN 9	=	 A23	;	/* System addresses */
PIN 10	=	 A22	;
PIN 11	=	 A21	;
PIN 13	=	 A20	;
PIN 14	=	 MEG4	;	/* 4 Meg parts? */
PIN 23	=	!CASDEL	;	/* CAS strobe delay */

/* BIDIRECTIONALS: */

PIN 16	=	!CASEN	;	/* CAS strobe enable */
PIN 17	=	!CASOUT	;	/* CAS delay input */
PIN 18	=	!REFCAS	;	/* CAS for refresh */
PIN 19	=	!REFCYC ;	/* We're in a refresh cycle. */
PIN 20	=	!DTACK	;	/* Data is valid on bus */
PIN 21	=	!RASEN	;	/* RAS strobe enable */

/* OUTPUTS: */

PIN 22	=	BK0	;	/* Small Bank bit 0 */
PIN 15	=	BK1	;	/* Small Bank bit 1 */

/** OUTPUT TERMS: **/

/* The data valid signal.  Data is valid on the bus if we're not in
   a refresh cycle, the board is selected, and something's happened.
   The non-burst cycle is driven by RAS delay only, the burst
   cycle by CAS delay only. */

DTACK		= SLAVE & !BURST & !REFACK & !REFCYC & DOE & RASDEL & CASDEL
		# SLAVE & !BURST &  DTACK
		# SLAVE &  BURST & !REFACK & !REFCYC & DOE & CASOUT & CASDEL & MTCR
		# SLAVE &  BURST &  DTACK & MTCR;

DTACK.OE	= SLAVE;

/* The RAS enable strobe.  If we're not in refresh, it goes as soon
   as we're sure the board is selected.  If refresh is called for, 
   start a RAS cycle after the CAS delay. */

RASEN		= !REFACK & !REFCYC & SLAVE & !RASDEL
		# !REFACK & !REFCYC & SLAVE &  RASEN
		#  REFCYC &  CASDEL & !RASDEL
		#  REFCYC &   RASEN & !RASDEL;

/* The CAS enable works differently for burst vs. non-burst.  For non-burst,
   it follows RASEN after DOE and MUX are asserted.  In a burst cycle, it
   follows MTCR.  For refresh, CAS can't be enabled until we're sure that
   RASDEL is negated, thus ensuring RAS precharge when a refresh cycle
   immediately follows a standard memory cycle.  */

CASOUT		= !REFACK & !REFCYC & !BURST &  RASDEL & DOE
		# !REFACK & !REFCYC &  BURST & !CASDEL & MTCR
		# !REFACK & !REFCYC & !BURST &  CASOUT & DTACK & SLAVE
		# !REFACK & !REFCYC &  BURST &  CASOUT & MTCR
		#  REFACK &  REFCYC & !RASEN & !RASDEL
		#  CASOUT &  REFCYC & !RASEN;
 
/* The actual CAS that goes out is modified by our use of SCRAMs.  If 
   SCRAMs are in use, CASEN goes low and stays low, while CASOUT works
   the DTACK line.  Otherwise, CASEN and CASOUT are the same. */

CASEN		= !REFACK & !REFCYC & !SCRAM & CASOUT
		# !REFACK & !REFCYC &  SCRAM & CASOUT
		# !REFACK & !REFCYC &  SCRAM &  CASEN & SLAVE;

/* This is the rest of the refresh machine.  A refresh cycle starts with a
   valid refresh acknowledge and the assertion of the standard and refresh 
   CAS.  RAS for refresh is asserted one CASDEL later, and standard CAS is
   negated at the same point.  The refresh counter will clear REFREQ when 
   REFCYC is asserted, and clear REFACK when REFREQ is negated. */

REFCAS		= REFACK & REFCYC & !CASDEL & !RASDEL
		# REFCAS & REFCYC & !MUX
		# REFCAS & REFCYC &  RASEN & !RASDEL;
 
REFCYC		= REFACK & !CASDEL & !RASDEL 
		# REFCYC &  CASOUT & !RASDEL
		# REFCYC &   RASEN
		# REFCYC &  RASDEL;

/* Bank control. The bank is controlled by A23 and A22 for 4 Meg memory,
   A21 and A20 for 1 Meg memory. */

BK0		= A22 &  MEG4
		# A20 & !MEG4;

BK1		= A23 &  MEG4
		# A21 & !MEG4;