PARTNO		U201 ;
	NAME		U201 ;
	DATE		May 24, 1990 ;
	REV		3 ;
	DESIGNER	Dave Haynie ;
	COMPANY		Commodore-Amiga ;
	ASSEMBLY	BIGRAM ;
	LOCATION	U201 ;

/************************************************************************/
/*									*/
/* Zorro III BIGRAM Board Control					*/
/*									*/
/*	This device controls the main features of the BIGRAM board.	*/
/*									*/
/************************************************************************/
/*									*/
/* DEVICE DATA:								*/
/*									*/
/*	Device:		20L8-10						*/
/*	Clock:		NONE						*/
/*	Unused:		22(O)						*/
/*									*/
/************************************************************************/
/*									*/
/* REVISION HISTORY:							*/
/*									*/
/*	DBH 05-02:	Original version.				*/
/*	DBH 05-24:	Fixed "select" term for configured state.	*/
/*	DBH 05-24:	Fixed various refresh bits.			*/
/*									*/
/************************************************************************/

/* INPUTS: */

PIN 1   =	!MATCH	;	/* Address match from comparator. */
PIN 2	=	 CFGLT	;	/* Configuration latch. */
PIN 3	=	!PRECON	;	/* Board was configed or shutup. */
PIN 4	=	!FCS	;	/* Full Cycle Strobe. */
PIN 5	=	!CFGIN	;	/* Configuration chain in. */
PIN 6	=	 FC0	;	/* Function codes, don't ignore these! */
PIN 7	=	 FC1	;
PIN 8	=	!REFREQ	;	/* Refresh request from refresh counter */
PIN 9	=	!Z2SHUNT;	/* Zorro II backplane bypass. */
PIN 10	=	 DOE	;	/* Data enable. */
PIN 11	=	!BERR	;	/* Bus error, all off. */
PIN 13	=	!REFCYC ;	/* We're in a refresh cycle. */
PIN 14	=	!BRENB	;	/* Burst/Multiple transfer enable. */
PIN 20	=	!MTCR	;	/* We're in a multiple cycle. */
PIN 23	=	 A24	;	/* Latched bus address 24. */

/* OUTPUTS: */

PIN 15	=	!DBOE	;	/* Data buffer output enable. */

/* BIDIRECTIONALS: */

PIN 16	=	!CFGOUT	;	/* Board is configured. */
PIN 17	=	!REFACK	;	/* Refresh acknowledge. */
PIN 18	=	!MTACK	;	/* Multiple transfer acknowledge. */
PIN 19	=	!SLAVE	;	/* Board select. */
PIN 21	=	!BURST	;	/* This is a burst cycle. */

/** INTERNAL TERMS: **/

/* The valid board address consists of a comparator match and a valid
   memory space.  The valid spaces are as follows:

	SPACE			FC2 FC1 FC0
	Reserved		 0   0   0
	User Data		 0   0   1
	User Program		 0   1   0
	Reserved		 0   1   1
	Reserved		 1   0   0
	Supervisor Data		 1   0   1
	Supervisor Program	 1   1   0
	CPU			 1   1   1

  This reduces to the equation used: FC0 XOR FC1. The external comparator
  only looks at A31..A25, which is OK for normal operation (we're a 32
  meg board), but bad for configuration.  So if we're not yet configured,
  A24 must be high for a select match.
*/

select		= MATCH & (FC0 $ FC1) & (CFGOUT # A24);

/* This indicates a normal board select; SLAVE starts the cycle, FCS
   cuts it off quickly at the end. */

hit		= SLAVE & FCS;

/* OUTPUT TERMS: */

/* This output controls the data buffer enable pins.  Data buffers
   turn on when DOE is asserted and the board is selected, they
   turn off as quickly after a cycle ends as possible. */

DBOE		= hit & DOE & !BERR;

/* This signal indicates that the board is configured. The board is
   considered configured if actually configured, shut up, or placed
   in a Zorro II backplane.  It only responds if actually configured,
   of course. This signal must only change at the end of a cycle, if
   actually operating. */

CFGOUT		= PRECON & CFGIN & !FCS
		# PRECON & CFGOUT
		# Z2SHUNT;

/* This is the refresh acknowledge cycle.  When the a refresh request
   comes in, and the coast is clear, this line is asserted to start
   the refresh machine.  Determining when the coast is clear, eg,
   arbitrating refresh, is the trick to all hand-made DRAM controllers.
   This one works pretty simply.  The coast is clear when there's no
   bus cycle happening, or when a bus cycle is happening but another
   slave is responding.  The trick is avoid races; FCS could be 
   changing just as REFREQ comes in.  Therefore, the second half of
   this arbiter is in the RAS cycle generation, which doesn't start
   until REFACK is negated and SLAVE is asserted.  */

REFACK		= REFREQ & !FCS & !MATCH
		# REFREQ &  FCS & !SLAVE & DOE
		# REFACK &  REFREQ;

/* The multiple cycle transfer acknowledge.  If the jumper enables
   them, and a refresh isn't already requested, we'll acknowledge
   them.  If a refresh request comes in, we'll negate MTACK after
   the current cycle finishes, which will result in one more 
   burst cycle before the full cycle terminates and the refresh
   can be acknowledged.  I do it this way because I use the 
   refresh timer to handle the TRASMAX limitation of the DRAM as
   wall as handling refresh. */

MTACK		= hit & BRENB & !REFREQ
		# hit & MTACK & !DOE
		# hit & MTACK &  MTCR;

MTACK.OE	= hit;

/* This is SLAVE, the board select line.  Most board activity centers
   around this line.  If the board is selected and unconfigured, 
   always respond.  Once configured, only respond if it's not shutup
   or shunted.  This line is held through the cycle's end. */

SLAVE		= select & FCS & CFGIN & !CFGOUT
		# select & FCS & CFGLT &  CFGOUT;

/* This indicates if the cycle is a burst cycle.  The first cycle is
   always a non-burst cycle.  If, at the end of the first cycle,
   MTCR and MTACK are asserted, all subsequent cycles are burst
   until FCS is negated. */

BURST		= SLAVE & DOE & MTCR & MTACK
		# BURST & FCS;