PARTNO		U200 ;
	NAME		U200 ;
	DATE		May 2, 1990 ;
	REV		1 ;
	DESIGNER	Dave Haynie ;
	COMPANY		Commodore-Amiga ;
	ASSEMBLY	BIGRAM ;
	LOCATION	U200 ;

/************************************************************************/
/*									*/
/* Zorro III BIGRAM Configuration Control 				*/
/*									*/
/*	This device acts as configuration ROM and configuration 	*/
/*	register controller.						*/
/*									*/
/************************************************************************/
/*									*/
/* DEVICE DATA:								*/
/*									*/
/*	Device:		16L8-15						*/
/*	Clock:		NONE						*/
/*	Unused:		NONE						*/
/*									*/
/************************************************************************/
/*									*/
/* REVISION HISTORY:							*/
/*									*/
/*	DBH 05-02:	Original version.				*/
/*									*/
/************************************************************************/

/* INPUTS: */

PIN 1	=	!SLAVE	;	/* Board selected? */
PIN 2	=	!RST	;	/* Board reset */
PIN 3	=	!DS3	;	/* High order data strobe. */
PIN 4	=	 READ	;	/* Read cycle strobe */
PIN 5	=	 A2	;	/* Bus Addresses. */
PIN 6	=	 A3	;
PIN 7	=	 A4	;
PIN 8	=	 A5	;
PIN 9	=	 A6	;
PIN 11	=	 A1	;	/* This is really A8. */
PIN 16	=	!CFGOUT	;	/* Board configured? */

/* OUTPUTS: */

PIN 19	=	 D28	;	/* Configuration data ROM nybble. */
PIN 12	=	 D31	;
PIN 13	=	 D30	;
PIN 14	=	 D29	;
PIN 15	=	 DBDIR	;	/* Data buffer direction. */

/* BIDIRECTIONALS: */

PIN 17	=	!PRECON	;	/* Preconfiguation strobe. */
PIN 18	=	 CFGLT	;	/* Configuration address latch. */


/** INTERNAL TERMS: **/

/* Mapping A8 as A1 here makes the register pairs line up just
   as they would under Zorro II configuration. */

field addr	= [A6..1];


/** OUTPUT TERMS: **/

/* The configuration ROM is created here.  The logical ordering
   of it is as follows:

	REG	76543210

	00	10100001	Zorro III, autolink, 32 megabytes
	04	10010010	Product $53
	08	10100001	Extended Memory board, supports
				Shutup, autosized in software.
	0C	00000000	Reserved
	10	00000010	Manufacturer's code (C-A)
	14	00000010
	18-3C	00000000	Zeroed options/reserved.

   The autoconfiguration specs call for every readable register 
   except for 0 to be inverted in the physical implementation.
   So the resulting map is:


	ADDR	D31 D30 D29 D28
	 00	 1   0   1   0
	 02	 0   0   0   1
	 04	 0   1   1   0
	 06	 1   1   0   1
	 08	 0   1   0   1
	 0A	 1   1   1   0
	 0C	 1   1   1   1
	 0E	 1   1   1   1
	 10	 1   1   1   1
	 12	 1   1   0   1
	 14	 1   1   1   1
	 16	 1   1   0   1
	OTHERS	 1   1   1   1

  Only the Zero terms are explicitly entered here; anything not specifically
  driven low will be driven high.
*/

!D31		= addr:02
		# addr:04
		# addr:08;

!D30		= addr:00
		# addr:02;

!D29		= addr:02
		# addr:06
		# addr:08
		# addr:12
		# addr:14;

!D28		= addr:00
		# addr:04
		# addr:0A;

[D31..28].OE	= SLAVE & !CFGOUT & READ;

/* This signal is driven to indicate an address latch request.
   Note that the board uses 16 bit configuration write feature
   to configure all at once; this isn't available in the Zorro II
   configuration space. */

CFGLT		= PRECON & !A3
		# CFGLT & !RST;

/* If the board is told to shut up or configure, this line is 
   asserted and held through reset.  The logical SHUTUP line
   is PRECON & !CFGLT, once FCS is negated. */

PRECON		= SLAVE & DS3 & addr:4C
		# SLAVE & DS3 & addr:44
		# PRECON & !RST;

/* This controls the data buffer direction between the PIC's 
   local bus and the expansion bus. */

DBDIR		= SLAVE & READ;