PARTNO		U303 ;
	NAME		U303 ;
	DATE		July 9, 1992 ;
	REV		0 ;
	DESIGNER	Dave Haynie ;
	COMPANY		Commodore ;
	ASSEMBLY	A3090 ;
	LOCATION	West Chester ;
	DEVICE		g22v10 ;

/************************************************************************/
/*									*/
/*	A3090	Zorro III/SCSI Arbiter					*/
/*									*/
/*	This device manages arbitration of the A3090 and Zorro III 	*/
/*	buses.								*/
/*									*/
/************************************************************************/
/*									*/
/* DEVICE DATA:								*/
/*									*/
/*	Device:		22V10-15					*/
/*	Clock:		C7M (33MHz)					*/
/*	Unused:		11(I),13(I),14(I/O),15(I/O),16(I/O),19(I/O)	*/
/*									*/
/************************************************************************/
/*									*/
/* REVISION HISTORY:							*/
/*									*/
/*	DBH Jul  9:	Original version.				*/
/*									*/
/************************************************************************/

/** INPUTS: **/

PIN 1		=  C7M		;	/* Zorro III arbiter clock. */
PIN 2		= !MASTER	;	/* SCSI owns the A3090 bus. */
PIN 3		= !SBR		;	/* SCSI bus request. */
PIN 4		= !EBG		;	/* Expansion bus grant. */
PIN 5		=  FCS		;	/* Zorro III cycle strobe. */
PIN 6		= !SLAVE	;	/* Zorro III slave response. */
PIN 7		= !DTACK	;	/* Zorro III bus termination. */
PIN 8		= !BERR		;	/* Zorro III bus error. */
PIN 9		= !RST		;	/* Zorro III reset. */
PIN 10		=  CLK		;	/* NCR 53C710 bus clock. */

/** OUTPUTS: **/

PIN 14		= SMASTER	;	/* synched master for fall edge */
PIN 15		= BLOCKBG	;	/* after 1st sbg block till end */
PIN 16		= DMASTER	;	/* MASTER DELAYED. */
PIN 17		= !MYBUS	;	/* A3090 owns the Zorro III bus. */
PIN 18		= !SBG		;	/* SCSI bus grant. */
PIN 19		= SSBR		;	/* SYNCHED SCSI bus req. */
PIN 20		= !REGED	;	/* A3090 is registered as a Zorro III master. */
PIN 21		= !EBR		;	/* Zorro III bus request. */
PIN 23		=  BMASTER	;	/* Buffered/inverted version of MASTER. */

/** USED INTERNALLY: **/

PIN 22		= !RCHNG	;	/* Registration is changing. */

/** OUTPUT TERMS: **/

/* The SCSI chip can be given the A3090 bus as soon as there's no activity on it. 
   Hold onto it until the SCSI becomes master. */
/* Not really if granted early the chip will have as asserted then fcs will 
   assert and when the z bus is granted fcs and addr will assert a the same time */

SBG		= !FCS & !DTACK & !RST & SBR & EBG & !BLOCKBG
		#  SBG &  SBR & !RST & !BLOCKBG
		#  SBG & !MASTER & !RST & !BLOCKBG;

/* after 1st sbg must block any further till unregistered and ebg deasserts;
*/
BLOCKBG		= MASTER
		# BLOCKBG & REGED # BLOCKBG & EBG;
/* The Zorro III bus request is driven out on C7M high, for one C7M cycle, to
   register for bus mastership.  When done, the same sequence relinquishes
   registration.  The RCHNG signal indicated when a change is necessary. */

EBR.D		= RCHNG & !EBR & !RST;
EBR.AR		= RST;

/* A change of registration is necessary whenever a SCSI request comes in 
   and we're unregistered, or when the MASTER line is dropped and we are
   registered. DMASTER is used to block regd & !master period at beginning*/

RCHNG.D		= !REGED & SSBR & !EBR
		#  REGED & !SMASTER & !EBR & DMASTER;
DMASTER.D	= SMASTER;
SMASTER.D	= MASTER;
/* Here's the actual registration indicator.  We're registered when EBR toggles,
   unregistered the next time it toggles.  This can only change while EBR is low,
   or in response to an error or reset condition. */

REGED.D		= !REGED & EBR
		#  REGED & !EBR & !RST;
REGED.AR	= RST;

/* The A3090 has the Zorro III bus only if its registered and it receives a grant.
   It holds the bus until the grant is removed and the cycle ends. */

MYBUS		= REGED & EBG
		# MYBUS & FCS & !RST;

/* SBR is synch to 33M clock we must synch to 7m to avoid metastability. SBG
   is not resynched to 33m since we use asynch fast arbitration mode */

SSBR.D		= SBR;


BMASTER = MASTER;