PARTNO		U207 ;
	NAME		U207 ;
	DATE		July 1, 1992 ;
	REV		0 ;
	DESIGNER	Dave Haynie ;
	COMPANY		Commodore ;
	ASSEMBLY	A3090 ;
	LOCATION	West Chester ;
	DEVICE		g22v10 ;

/************************************************************************/
/*									*/
/*	A3090	Network chip control and interrupt mixer.		*/
/*									*/
/*	This device manages assorted COM20020 functions and combines 	*/
/*	interrupt signals from both this network device and the NCR	*/
/* 	SCSI chip.							*/
/*									*/
/************************************************************************/
/*									*/
/* DEVICE DATA:								*/
/*									*/
/*	Device:		22V10-15					*/
/*	Clock:		CLK (33MHz)					*/
/*	Unused:		21(I/O)						*/
/*									*/
/************************************************************************/
/*									*/
/* REVISION HISTORY:							*/
/*									*/
/*	DBH Jul  1:	Original version.				*/
/*									*/
/************************************************************************/

/** INPUTS: **/

PIN 1		=  CLK		;	/* 33MHz system clock. */
PIN 5		= !DS0		;	/* Low byte data strobe. */
PIN 6		=  READ		;	/* Z3 READ signal. */
PIN 7		= !RST		;	/* System reset signal. */
PIN 8		= !SINT		;	/* SCSI interrupt. */
PIN 9		= !INTVEC	;	/* Interrupt vector generation. */
PIN 10		=  FCS		;	/* Z3 full cycle strobe. */
PIN 11		= !SLAVE	;	/* Board select. */
PIN 13		= !CFGOUT	;	/* Configuration chain output. */
PIN 16		= !ROM		;	/* ROM select decode. */

/** OUTPUTS: **/

PIN 20		= !NACK		;	/* Network data acknowledge. */
PIN 22		= !INT		;	/* Interrupt output. */

/** USED INTERNALLY: **/

PIN 17		= !NS2		;	/* Network chip cycle counter. */
PIN 18		= !NS1		;
PIN 19		= !NS0		;

/** INTERNAL TERMS: **/

/* The state vector */

field state	= [NS2..0];

/** OUTPUT TERMS: **/


/* The combined interrupt line is generated based on either of the
   device-specific interrupt lines.  It can only change between
   Zorro III cycles. */

INT		= !FCS & SINT
		#  INT & SINT;

/* This is a simple counter for network access states.  The state
   count starts based on network chip or ROM access. */

NS0.D		= !RST & FCS & ROM & !NS0;

NS1.D		= !RST & FCS & (NS0 $ NS1);

NS2.D		= !RST & FCS & ((NS0 & NS1) $ NS2);

[NS2..0].AR	= RST;


/* The termination signal is at least 200ns from the chip select 
   (again, verify the timing on this).  Since the clock is 33MHz,
   the states are roughly 30ns each, so we'll need to wait seven
   states between NCS and the termination signal.  Since the only
   other timed access on the board is the ROM response, that's
   done here too.  A 150ns ROM needs five clocks. */

NACK		=  ROM & state:5
		# NACK & FCS & !RST;