PARTNO		U203 ;
	NAME		U203 ;
	DATE		June 30, 1992 ;
	REV		0 ;
	DESIGNER	Dave Haynie ;
	COMPANY		Commodore ;
	ASSEMBLY	A3090 ;
	LOCATION	West Chester ;
	DEVICE		g22v10 ;

/************************************************************************/
/*									*/
/*	A3090	Device Mapper, Interrupt manager			*/
/*									*/
/*	This device manages chip select decodes for various devices on	*/
/*	board.  Additionally, it helps supports the interrupt vector	*/
/*	response handshaking.						*/
/*									*/
/************************************************************************/
/*									*/
/* DEVICE DATA:								*/
/*									*/
/*	Device:		22V10-10					*/
/*	Clock:		NONE						*/
/*	Unused:		NONE						*/
/*									*/
/************************************************************************/
/*									*/
/* REVISION HISTORY:							*/
/*									*/
/*	DBH Jun 20:	Original version.				*/
/*									*/
/************************************************************************/

/** INPUTS: **/

PIN 1		=  A23		;	/* Addresses */
PIN [2..4]	= [A19..17]	;
PIN 5		=  A1		;	/* Real A1/Lock signal */
PIN 6		= !INT		;	/* Merged SCSI/Net interrupt. */
PIN 7		=  READ		;	/* Z3 read strobe. */
PIN 8		= !DS0		;	/* Z3 low order data strobe. */
PIN 9		=  FC2		;	/* Function code. */
PIN 10		=  FCS		;	/* Z3 full cycle strobe. */
PIN 11		= !MTCR		;	/* Z3 multiple transfer cycle strobe. */
PIN 13		= !INTSPC	;	/* Partially qualified interrupt space. */
PIN 23		= !RST		;	/* Reset. */

/** OUTPUTS: **/

PIN 14		= !SID		;	/* SCSI ID jumper access. */
PIN 15		= !INT2		;	/* Interrupt out to Z3 bus. */
PIN 19		= !INTVEC	;	/* An interrupt vector phase is signalled. */
PIN 20		=  INTREG	;	/* Interrupt register access. */
PIN 21		= !ROM		;	/* System ROM access. */
PIN 22		= !SCSI		;	/* SCSI Chip register access. */

/** BIDIRECTIONALS: **/

PIN 17		= !SLAVE	;	/* Slave for interrupt cycles. */

/** USED INTERNALLY: **/

PIN 16		= !INTSERV	;	/* We're servicing this interrupt phase. */
PIN 18		= !INTPOLL	;	/* An interrupt polling phase is signalled. */

/** INTERNAL TERMS: **/

/* The addresses for decodes. */

field addr	= [A23,A19..A17];

/* The qualifier for CPU space access, basically, anything that isn't a possible
   interrupt cycle. */

cpucyc		= !(INTSPC & FC2);

/* This interrupt cycle qualifier takes into account the partial qualifier and
   the full interrupt address.  In reality, this should also look for A16 high,
   but I didn't have enough pins after adding the ID register.  In practice, the
   only CPU space type are breakpoint (0), coprocessor (2), and interrupt
   acknowledge (f), so this is safe. */

intcyc		= INTSPC & FC2 & A19 & A18 & A17 & !A1 & READ;

/** OUTPUT TERMS: **/

/* The basic configuration unit takes 16MB of space.  I slice it up based on A23,
   A19..A17.  That's because, while the slicing is rather arbitrary, the interrupt
   cycle decode needs A19..A17, so I use these for partitioning too.


   8C0000	IDREG
   880000	INTREG
   840000	SCSI write
   800000	SCSI read
   000000	ROM   

*/

/* The ROM is selected for all reads before we're configured, for low reads after
   configuration.  Since only lower memory is read during configuration, this
   doesn't have to be any kind of special case. */

ROM		= cpucyc & SLAVE & READ & addr:[7fffff..000000]
		# ROM & SLAVE;

/* SCSI and NET selects are very straight-forward. */

SCSI		= cpucyc & SLAVE & addr:[83ffff..800000] & READ
		# cpucyc & SLAVE & addr:[87ffff..840000] & !READ;

/* The interrupt register select is actually a latching signal.  It should be 
   asserted in interrupt register space only after data is valid, and only on
   writes. */

INTREG		= cpucyc & SLAVE & addr:[8bffff..880000] & DS0 & !READ;

/* The SCSI ID register is a read-only register. */

SID		= cpucyc & SLAVE & addr:[8fffff..8c0000] & READ;

/* Whenever an interrupt comes in, I pass it out via a simulated open-collector
   signal to the bus. */

INT2		= 'b'1;
INT2.OE		= INT;


/* Should we be responding to an interrupt poll?  Only if the interrupt has been
   locally generated.  This strobe indicates the start of a service condition.
   It is negated once the POLL phase is complete.  Note that the INT signal is
   designed to change only between Z3 cycles, which prevents an INTSERV condition
   from being triggered should an interrupt just happen to come in while a poll
   is being conducted. */

INTSERV		= intcyc & INT & !FCS
		# INTSERV & !INTPOLL & !RST
		# INTSERV &  MTCR;

/* A poll phase starts when we've established a service condition and MTCR falls.
   This is held through the end of the cycle. */

INTPOLL		= INTSERV & MTCR
		# INTPOLL & FCS;

/* A slave output is generated if we're established that the polling phase is 
   being answered. */

SLAVE		= 'b'1;
SLAVE.OE	= INTPOLL & INTSERV;

/* The vector phase is started in response to an answered polling condition. */

INTVEC		= INTPOLL & MTCR & SLAVE & DS0;