PARTNO		U306 ;
	NAME		U306 ;
	DATE		July 9, 1992 ;
	REV		0 ;
	DESIGNER	Dave Haynie ;
	COMPANY		Commodore ;
	ASSEMBLY	A3090 ;
	LOCATION	West Chester ;
	DEVICE		p22v10 ;

/************************************************************************/
/*									*/
/*	A3090	SCSI Burst Control					*/
/*									*/
/*	This device manages burst and some other bits of NCR 53C710 to	*/
/*	Zorro III bus translation.					*/
/*									*/
/************************************************************************/
/*									*/
/* DEVICE DATA:								*/
/*									*/
/*	Device:		22V10-10					*/
/*	Clock:		!CLK (33MHz)					*/
/*	Unused:		11(I),13(I),18(I/O)				*/
/*									*/
/************************************************************************/
/*									*/
/* REVISION HISTORY:							*/
/*									*/
/*	DBH Jul  9:	Original version.				*/
/*									*/
/************************************************************************/

/** INPUTS: **/

PIN 1		= !CLK		;	/* 33MHz system clock. */
PIN 2		= !MYBUS	;	/* SCSI owns the Zorro III bus. */
PIN 3		=  FCS		;	/* Zorro III cycle strobe. */
PIN 4		= !MTACK	;	/* Zorro III slave burst strobe. */
PIN 5		= !CBREQ	;	/* SCSI burst request. */
PIN 6		= !SCSI		;	/* SCSI slave chip select. */
PIN 7		= !EDTACK	;	/* Zorro III data acknowledge, on bus. */
PIN 8		= !ABOEH	;	/* High order address buffer enable. */
PIN 9		= !BERR		;	/* Zorro III bus error. */
PIN 10		= !RST		;	/* Zorro III reset. */

/** OUTPUTS: **/

PIN 14		= !BDTACK	;	/* Zorro III data acknowledge, buffered. */
PIN 16		= !STERM	;	/* SCSI termination. */
PIN 17		= !BURST	;	/* This cycle will be a burst cycle. */
PIN 19		=  DOE		;	/* Zorro III data ouput enable. */
PIN 21		= !MTCR		;	/* Zorro III multiple transfer strobe. */
PIN 22		= !LASTBURST	;	/* Zorro III end-of-burst indicator. */
PIN 23		= !CBACK	;	/* SCSI burst acknowledge. */

/** USED INTERNALLY: **/

PIN 15		= !DTSYNC	;	/* Synchronizer for DTACK->STERM. */
PIN 20		= !DCNT		;	/* State bit for Zorro III stuff. */


/** OUTPUT TERMS: **/

/* The data output enable has to wait until a safe "data phase".  This is 
   guaranteed to be two clocks after FCS falls.  DCNT is used to time
   this from cycle's start. */

DOE.D		= FCS & !DOE & MYBUS & DCNT
		# FCS &  DOE;
DOE.OE		= MYBUS;
DOE.AR		= RST;

/* This form FCS, to ensure proper DOE assertion. */

DCNT.D		= FCS & !DOE & !DCNT & MYBUS
		# FCS & DCNT;
DCNT.AR		= RST;

/* This signal samples an incoming DTACK, to help out with STERM
   generation. */

DTSYNC.D	= FCS &  DOE &  !BURST & EDTACK
		# FCS &  DOE &   BURST & EDTACK & MTCR;
DTSYNC.AR	= RST;

/* The SCSI termination is based on a synchronized DTACK.  I actually 
   synchronize DTACK for either slave or master cycle, since the 
   NCR 53C710 wants the effect of SLACK (which makes a DTACK on slave
   to SCSI cycles) reflected on STERM to actually end the cycle. */

STERM.D		= DTSYNC & EDTACK & FCS & !BURST
		# DTSYNC & !STERM & FCS &  BURST & MTCR;
STERM.AR	= RST;

/* The SCSI chips gets a CBACK any time we have an MTACK. */

CBACK		= MYBUS & FCS & MTACK;
CBACK.OE	= MYBUS;

/* The burst cycle is based on the burst handshaking between Zorro III and
   the SCSI chip.  This has to be done by DOE time. */

BURST		= MYBUS & MTACK & FCS & CBACK & !DOE
		# MYBUS & BURST & FCS;

LASTBURST	= MYBUS &     BURST & !MTACK & MTCR
		# MYBUS & LASTBURST & FCS;
		
/* The burst strobe is generated for any burst cycle

MTCR.D		= MYBUS & FCS & BURST & DOE & !STERM & !LASTBURST
		# MYBUS & FCS & BURST & DOE & !STERM &  MTCR;
MTCR.AR		= RST;

/* The DTACK line is buffered into the rest of the board. */

BDTACK		= EDTACK;