LISTING FOR LOGIC DESCRIPTION FILE: u306.pld                         Page 1

CUPL: Universal Compiler for Programmable Logic
Version 4.0a Serial# MD-40A-8380
Copyright (C)  1983,1990 Logical Devices, Inc.
Created Fri Jan 04 02:56:32 1980

  1:        PARTNO          U306 ;
  2:        NAME            U306 ;
  3:        DATE            July 9, 1992 ;
  4:        REV             0 ;
  5:        DESIGNER        Dave Haynie ;
  6:        COMPANY         Commodore ;
  7:        ASSEMBLY        A3090 ;
  8:        LOCATION        West Chester ;
  9:        DEVICE          p22v10 ;
 10:
 11:/************************************************************************/
 12:/*                                                                      */
 13:/*      A3090   SCSI Burst Control                                      */
 14:/*                                                                      */
 15:/*      This device manages burst and some other bits of NCR 53C710 to  */
 16:/*      Zorro III bus translation.                                      */
 17:/*                                                                      */
 18:/************************************************************************/
 19:/*                                                                      */
 20:/* DEVICE DATA:                                                         */
 21:/*                                                                      */
 22:/*      Device:         22V10-10                                        */
 23:/*      Clock:          !CLK (33MHz)                                    */
 24:/*      Unused:         11(I),13(I),18(I/O)                             */
 25:/*                                                                      */
 26:/************************************************************************/
 27:/*                                                                      */
 28:/* REVISION HISTORY:                                                    */
 29:/*                                                                      */
 30:/*      DBH Jul  9:     Original version.                               */
 31:/*                                                                      */
 32:/************************************************************************/
 33:
 34:/** INPUTS: **/
 35:
 36:PIN 1           = !CLK          ;       /* 33MHz system clock. */
 37:PIN 2           = !MYBUS        ;       /* SCSI owns the Zorro III bus. */
 38:PIN 3           =  FCS          ;       /* Zorro III cycle strobe. */
 39:PIN 4           = !MTACK        ;       /* Zorro III slave burst strobe. */
 40:PIN 5           = !CBREQ        ;       /* SCSI burst request. */
 41:PIN 6           = !SCSI         ;       /* SCSI slave chip select. */
 42:PIN 7           = !EDTACK       ;       /* Zorro III data acknowledge, on bus. */
 43:PIN 8           = !ABOEH        ;       /* High order address buffer enable. */
 44:PIN 9           = !BERR         ;       /* Zorro III bus error. */
 45:PIN 10          = !RST          ;       /* Zorro III reset. */
 46:
 47:/** OUTPUTS: **/
 48:
 49:PIN 14          = !BDTACK       ;       /* Zorro III data acknowledge, buffered. */
 50:PIN 16          = !STERM        ;       /* SCSI termination. */
 51:PIN 17          = !BURST        ;       /* This cycle will be a burst cycle. */
 52:PIN 19          =  DOE          ;       /* Zorro III data ouput enable. */
 53:PIN 21          = !MTCR         ;       /* Zorro III multiple transfer strobe. */

LISTING FOR LOGIC DESCRIPTION FILE: u306.pld                         Page 2

CUPL: Universal Compiler for Programmable Logic
Version 4.0a Serial# MD-40A-8380
Copyright (C)  1983,1990 Logical Devices, Inc.
Created Fri Jan 04 02:56:32 1980

 54:PIN 22          = !LASTBURST    ;       /* Zorro III end-of-burst indicator. */
 55:PIN 23          = !CBACK        ;       /* SCSI burst acknowledge. */
 56:
 57:/** USED INTERNALLY: **/
 58:
 59:PIN 15          = !DTSYNC       ;       /* Synchronizer for DTACK->STERM. */
 60:PIN 20          = !DCNT         ;       /* State bit for Zorro III stuff. */
 61:
 62:
 63:/** OUTPUT TERMS: **/
 64:
 65:/* The data output enable has to wait until a safe "data phase".  This is 
 66:   guaranteed to be two clocks after FCS falls.  DCNT is used to time
 67:   this from cycle's start. */
 68:
 69:DOE.D           = FCS & !DOE & MYBUS & DCNT
 70:                # FCS &  DOE;
 71:DOE.OE          = MYBUS;
 72:DOE.AR          = RST;
 73:
 74:/* This form FCS, to ensure proper DOE assertion. */
 75:
 76:DCNT.D          = FCS & !DOE & !DCNT & MYBUS
 77:                # FCS & DCNT;
 78:DCNT.AR         = RST;
 79:
 80:/* This signal samples an incoming DTACK, to help out with STERM
 81:   generation. */
 82:
 83:DTSYNC.D        = FCS &  DOE &  !BURST & EDTACK
 84:                # FCS &  DOE &   BURST & EDTACK & MTCR;
 85:DTSYNC.AR       = RST;
 86:
 87:/* The SCSI termination is based on a synchronized DTACK.  I actually 
 88:   synchronize DTACK for either slave or master cycle, since the 
 89:   NCR 53C710 wants the effect of SLACK (which makes a DTACK on slave
 90:   to SCSI cycles) reflected on STERM to actually end the cycle. */
 91:
 92:STERM.D         = DTSYNC & EDTACK & FCS & !BURST
 93:                # DTSYNC & !STERM & FCS &  BURST & MTCR;
 94:STERM.AR        = RST;
 95:
 96:/* The SCSI chips gets a CBACK any time we have an MTACK. */
 97:
 98:CBACK           = MYBUS & FCS & MTACK;
 99:CBACK.OE        = MYBUS;
100:
101:/* The burst cycle is based on the burst handshaking between Zorro III and
102:   the SCSI chip.  This has to be done by DOE time. */
103:
104:BURST           = MYBUS & MTACK & FCS & CBACK & !DOE
105:                # MYBUS & BURST & FCS;
106:
107:LASTBURST       = MYBUS &     BURST & !MTACK & MTCR

LISTING FOR LOGIC DESCRIPTION FILE: u306.pld                         Page 3

CUPL: Universal Compiler for Programmable Logic
Version 4.0a Serial# MD-40A-8380
Copyright (C)  1983,1990 Logical Devices, Inc.
Created Fri Jan 04 02:56:32 1980

108:                # MYBUS & LASTBURST & FCS;
109:                
110:/* The burst strobe is generated for any burst cycle
111:
112:MTCR.D          = MYBUS & FCS & BURST & DOE & !STERM & !LASTBURST
113:                # MYBUS & FCS & BURST & DOE & !STERM &  MTCR;
114:MTCR.AR         = RST;
115:
116:/* The DTACK line is buffered into the rest of the board. */
117:
118:BDTACK          = EDTACK;
119:
120:

[0016cb] Please note: no expression assigned to:  DCNT.sp
[0016cb] Please note: no expression assigned to:  DOE.sp
[0016cb] Please note: no expression assigned to:  DTSYNC.sp
[0016cb] Please note: no expression assigned to:  STERM.sp


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