LISTING FOR LOGIC DESCRIPTION FILE: u207.pld                         Page 1

CUPL: Universal Compiler for Programmable Logic
Version 4.0a Serial# MD-40A-8380
Copyright (C)  1983,1990 Logical Devices, Inc.
Created Fri Jan 04 02:47:20 1980

  1:        PARTNO          U207 ;
  2:        NAME            U207 ;
  3:        DATE            July 1, 1992 ;
  4:        REV             0 ;
  5:        DESIGNER        Dave Haynie ;
  6:        COMPANY         Commodore ;
  7:        ASSEMBLY        A3090 ;
  8:        LOCATION        West Chester ;
  9:        DEVICE          p22v10 ;
 10:
 11:/************************************************************************/
 12:/*                                                                      */
 13:/*      A3090   Network chip control and interrupt mixer.               */
 14:/*                                                                      */
 15:/*      This device manages assorted COM20020 functions and combines    */
 16:/*      interrupt signals from both this network device and the NCR     */
 17:/*      SCSI chip.                                                      */
 18:/*                                                                      */
 19:/************************************************************************/
 20:/*                                                                      */
 21:/* DEVICE DATA:                                                         */
 22:/*                                                                      */
 23:/*      Device:         22V10-15                                        */
 24:/*      Clock:          CLK (33MHz)                                     */
 25:/*      Unused:         21(I/O)                                         */
 26:/*                                                                      */
 27:/************************************************************************/
 28:/*                                                                      */
 29:/* REVISION HISTORY:                                                    */
 30:/*                                                                      */
 31:/*      DBH Jul  1:     Original version.                               */
 32:/*                                                                      */
 33:/************************************************************************/
 34:
 35:/** INPUTS: **/
 36:
 37:PIN 1           =  CLK          ;       /* 33MHz system clock. */
 38:PIN 2           = !NTXEN        ;       /* Transmit enable from COM20020. */
 39:PIN 3           = !NINT         ;       /* Network interrupt. */
 40:PIN 4           = !NET          ;       /* Basic network chip select decode. */
 41:PIN 5           = !DS0          ;       /* Low byte data strobe. */
 42:PIN 6           =  READ         ;       /* Z3 READ signal. */
 43:PIN 7           = !RST          ;       /* System reset signal. */
 44:PIN 8           = !SINT         ;       /* SCSI interrupt. */
 45:PIN 9           = !INTVEC       ;       /* Interrupt vector generation. */
 46:PIN 10          =  FCS          ;       /* Z3 full cycle strobe. */
 47:PIN 11          = !SLAVE        ;       /* Board select. */
 48:PIN 13          = !CFGOUT       ;       /* Configuration chain output. */
 49:PIN 16          = !ROM          ;       /* ROM select decode. */
 50:
 51:/** OUTPUTS: **/
 52:
 53:PIN 14          = !NDS          ;       /* Network data strobe. */

LISTING FOR LOGIC DESCRIPTION FILE: u207.pld                         Page 2

CUPL: Universal Compiler for Programmable Logic
Version 4.0a Serial# MD-40A-8380
Copyright (C)  1983,1990 Logical Devices, Inc.
Created Fri Jan 04 02:47:20 1980

 54:PIN 15          = !NCS          ;       /* Network chip select. */
 55:PIN 20          = !NACK         ;       /* Network data acknowledge. */
 56:PIN 22          = !INT          ;       /* Interrupt output. */
 57:PIN 23          =  PTXEN        ;       /* Transmit enable to RS-488 driver */
 58:
 59:/** USED INTERNALLY: **/
 60:
 61:PIN 17          = !NS2          ;       /* Network chip cycle counter. */
 62:PIN 18          = !NS1          ;
 63:PIN 19          = !NS0          ;
 64:
 65:/** INTERNAL TERMS: **/
 66:
 67:/* The state vector */
 68:
 69:field state     = [NS2..0];
 70:
 71:/** OUTPUT TERMS: **/
 72:
 73:/* The transmit enable is just an inversion. */
 74:
 75:PTXEN           = NTXEN;
 76:
 77:/* The combined interrupt line is generated based on either of the
 78:   device-specific interrupt lines.  It can only change between
 79:   Zorro III cycles. */
 80:
 81:INT             = !FCS & NINT
 82:                # !FCS & SINT
 83:                #  INT & NINT
 84:                #  INT & SINT;
 85:
 86:/* This is a simple counter for network access states.  The state
 87:   count starts based on network chip or ROM access. */
 88:
 89:NS0.D           = !RST & FCS & NCS & !NS0
 90:                # !RST & FCS & ROM & !NS0;
 91:
 92:NS1.D           = !RST & FCS & (NS0 $ NS1);
 93:
 94:NS2.D           = !RST & FCS & ((NS0 & NS1) $ NS2);
 95:
 96:[NS2..0].AR     = RST;
 97:
 98:/* The actual network signals are very easy from here. The chip
 99:   select for the network chip is simply the first state after
100:   the asynchronous NET select has been received. */
101:
102:NCS.D           = !RST & FCS & NET
103:                # !RST & FCS & NCS;
104:NCS.AR          =  RST;
105:
106:/* The network data strobe is driven based on the READ condition.
107:   Check the required timing of this again in the COM20020 spec. 

LISTING FOR LOGIC DESCRIPTION FILE: u207.pld                         Page 3

CUPL: Universal Compiler for Programmable Logic
Version 4.0a Serial# MD-40A-8380
Copyright (C)  1983,1990 Logical Devices, Inc.
Created Fri Jan 04 02:47:20 1980

108:   I also toggle this puppy prior to configuration so that the
109:   COM20020 has plenty of time to sense the kind of bus (Motorola
110:   in this case, NDS and R/W get diddled at the same time). */
111:
112:NDS             =  READ & NCS
113:                # !READ & state:1
114:                #   NDS & FCS & !RST
115:                # !CFGOUT & SLAVE;
116:
117:/* The termination signal is at least 200ns from the chip select 
118:   (again, verify the timing on this).  Since the clock is 33MHz,
119:   the states are roughly 30ns each, so we'll need to wait seven
120:   states between NCS and the termination signal.  Since the only
121:   other timed access on the board is the ROM response, that's
122:   done here too.  A 150ns ROM needs five clocks. */
123:
124:NACK            =  NET & state:7
125:                #  ROM & state:5
126:                # NACK & FCS & !RST;
127:
128:
129:

[0016cb] Please note: no expression assigned to:  NCS.sp
[0016cb] Please note: no expression assigned to:  NS0.sp
[0016cb] Please note: no expression assigned to:  NS1.sp
[0016cb] Please note: no expression assigned to:  NS2.sp


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