LISTING FOR LOGIC DESCRIPTION FILE: u202.pld                         Page 1

CUPL: Universal Compiler for Programmable Logic
Version 4.0a Serial# MD-40A-8380
Copyright (C)  1983,1990 Logical Devices, Inc.
Created Fri Jan 04 02:40:02 1980

  1:        PARTNO          U202 ;
  2:        NAME            U202 ;
  3:        DATE            June 30, 1992 ;
  4:        REV             0 ;
  5:        DESIGNER        Dave Haynie ;
  6:        COMPANY         Commodore ;
  7:        ASSEMBLY        A3090 ;
  8:        LOCATION        West Chester ;
  9:        DEVICE          p22V10 ;
 10:
 11:/************************************************************************/
 12:/*                                                                      */
 13:/*      A3090   AutoConfig                                              */
 14:/*                                                                      */
 15:/*      This device manages various aspects of autoconfiguration, along */
 16:/*      with some address decoding and Zorro III signal generation.     */
 17:/*                                                                      */
 18:/************************************************************************/
 19:/*                                                                      */
 20:/* DEVICE DATA:                                                         */
 21:/*                                                                      */
 22:/*      Device:         22V10-15                                        */
 23:/*      Clock:          NONE                                            */
 24:/*      Unused:         NONE                                            */
 25:/*                                                                      */
 26:/************************************************************************/
 27:/*                                                                      */
 28:/* REVISION HISTORY:                                                    */
 29:/*                                                                      */
 30:/*      DBH Jun 20:     Original version.                               */
 31:/*                                                                      */
 32:/************************************************************************/
 33:
 34:/** INPUTS: **/
 35:
 36:PIN 1           = !MATCH        ;       /* Address comparator match. */
 37:PIN [2..7]      =  [A6..1]      ;       /* Low order address, A1 is really A8 */
 38:PIN 8           =  READ         ;       /* Z3 read strobe. */
 39:PIN 9           = !DS3          ;       /* Z3 high order data strobe. */
 40:PIN 10          =  FCS          ;       /* Z3 full cycle strobe. */
 41:PIN 11          =  FC1          ;       /* Function codes */
 42:PIN 13          =  FC0          ;
 43:PIN 14          = !BERR         ;       /* Bus error */
 44:PIN 15          = !CFGIN        ;       /* Configuration chain input */
 45:PIN 16          =  RST          ;       /* Z3 reset strobe. */
 46:PIN 17          = !SHUNT        ;       /* Z2 configuration shunt. */
 47:
 48:/** OUTPUTS: **/
 49:
 50:PIN 18          = !CFGOUT       ;       /* Configuration chain output */
 51:PIN 19          =  CFGLT        ;       /* Configuration address latch */
 52:PIN 20          = !CINH         ;       /* Z3 cache inhibit */
 53:PIN 22          = !SLAVE        ;       /* Normal slave response to Z3 bus. */

LISTING FOR LOGIC DESCRIPTION FILE: u202.pld                         Page 2

CUPL: Universal Compiler for Programmable Logic
Version 4.0a Serial# MD-40A-8380
Copyright (C)  1983,1990 Logical Devices, Inc.
Created Fri Jan 04 02:40:02 1980

 54:
 55:/** USED INTERNALLY: **/
 56:
 57:PIN 21          = !SLAVEOE      ;       /* Slave output enable. */
 58:PIN 23          = !INTSPC       ;       /* Partially qualified interrupt decode. */
 59:
 60:/** INTERNAL TERMS: **/
 61:
 62:/* Valid processor access space? */
 63:
 64:cpuspace        = FC0 & FC1;
 65:
 66:/* The low-order addresses. */
 67:
 68:field addr      = [A6..A1];
 69:
 70:/** OUTPUT TERMS: **/
 71:
 72:/* The board configuration is really quite simple.  If there's a
 73:   write to the configuration register space, the configuration address
 74:   is latched and we pass configuration out.  If the system is shunted
 75:   (eg, in a Zorro II backplane), configuration out goes immediately. 
 76:   Note that the configuration read registers are actually supplied by 
 77:   the first part of the boot ROM. */
 78:
 79:CFGLT           = addr:44 & cpuspace & FCS & !READ & CFGIN & DS3 & !BERR & !RST
 80:                # CFGLT & !RST;
 81:
 82:CFGOUT          = CFGLT & !RST & !FCS
 83:                # CFGOUT & !RST
 84:                # SHUNT;
 85:
 86:/* The slave signal is drive from here for any normal access.  When it isn't
 87:   being driven, it is tri-stated, since the interrupt response logic may 
 88:   also drive SLAVE.  */
 89:
 90:SLAVEOE         = CFGIN & MATCH & cpuspace & FCS & !RST;
 91:
 92:SLAVE           = 'b'1;
 93:SLAVE.OE        = SLAVEOE;
 94:
 95:/* The cache should be inhibited for any access to the board.  Actually, it
 96:   doesn't matter if we cache ROM, but there's no reason to since its not
 97:   execute-in-place ROM so no performance is lost making it uncached too. */
 98:
 99:CINH            = SLAVE;
100:CINH.OE         = SLAVE;
101:
102:/* This signal partially qualifies the decode for interrupt response cycles.
103:   We want to respond to INT2, of course in CPU space only.  The rest of
104:   the decode takes place in U203, including the real A1. */
105:
106:INTSPC          = CFGIN & CFGOUT & FC0 & FC1 & !RST & !A3 & A2;
107:

LISTING FOR LOGIC DESCRIPTION FILE: u202.pld                         Page 3

CUPL: Universal Compiler for Programmable Logic
Version 4.0a Serial# MD-40A-8380
Copyright (C)  1983,1990 Logical Devices, Inc.
Created Fri Jan 04 02:40:02 1980

108:



Jedec Fuse Checksum       (4dfe)
Jedec Transmit Checksum   (3abc)