PARTNO		391587-02;
	NAME		U306 ;
	DATE		March 29, 1993 ;
	REV		5 ;
	DESIGNER	Dave Haynie ;
	COMPANY		Commodore ;
	ASSEMBLY	A3090 ;
	LOCATION	West Chester ;
	DEVICE		g22v10 ;

/************************************************************************/
/*									*/
/*	A3090	SCSI Burst Control					*/
/*									*/
/*	This device manages burst and some other bits of NCR 53C710 to	*/
/*	Zorro III bus translation.					*/
/*									*/
/************************************************************************/
/*									*/
/* DEVICE DATA:								*/
/*									*/
/*	Device:		22V10-10					*/
/*	Clock:		!CLK (33MHz)					*/
/*	Unused:		13(I)						*/
/*									*/
/************************************************************************/
/*									*/
/* REVISION HISTORY:							*/
/*									*/
/*	DBH Jul  9:	Original version.				*/
/*	DBH Oct 26:	The expansion FCS is now generated here.	*/
/*	DBH Oct 26:	Reworked DTSYNC and STERM to free up AR for 	*/
/*			use EFCS.					*/
/*	DBH Oct 26:	Find the missing DTACK.  Fix to correct this.	*/
/*	DBH Oct 28:	Changes here for a different FCS/DTACK strategy	*/
/*			that makes the FCS shutoff delay independent of */
/*			A3090 DTACK sampling.				*/
/*	DBH Oct 29:	Changed above to also insure STERM is generated	*/
/*			in slave mode, even at 25MHz.			*/
/*	DBH Mar 29:	Stolen the unused BURST pin for NOZ3.  This	*/
/*			is asserted to get the A4091 off the Zorro III	*/
/*			bus quickly, even when its local FCS may still	*/
/*			be active.  This is designed to fix the 	*/
/*			multiple A4091 problem.				*/
/************************************************************************/

/** INPUTS: **/

PIN 1		= !CLK		;	/* 33MHz system clock. */
PIN 2		= !MYBUS	;	/* SCSI owns the Zorro III bus. */
PIN 3		=  BFCS		;	/* A3090 local Zorro III cycle strobe. */
PIN 4		= !MTACK	;	/* Zorro III slave burst strobe. */
PIN 5		= !CBREQ	;	/* SCSI burst request. */
PIN 6		= !SCSI		;	/* SCSI slave chip select. */
PIN 7		= !EDTACK	;	/* Zorro III data acknowledge, on bus. */
PIN 8		= !ABOEH	;	/* High order address buffer enable. */
PIN 9		= !BERR		;	/* Zorro III bus error. */
PIN 10		= !RST		;	/* Zorro III reset. */
PIN 11		= !ASQ		;	/* Clocked and qualified SCSI strobe. */

/** OUTPUTS: **/

PIN 14		= !BDTACK	;	/* Zorro III data acknowledge, buffered. */
PIN 16		= !STERM	;	/* SCSI termination. */
PIN 17		= !NOZ3		;	/* Stop driving Zorro III! */
PIN 18		= !EFCS		;	/* Zorro III cycle strobe for DMA. */
PIN 19		=  DOE		;	/* Zorro III data ouput enable. */
PIN 21		= !MTCR		;	/* Zorro III multiple transfer strobe. */
PIN 23		= !CBACK	;	/* SCSI burst acknowledge. */

/** USED INTERNALLY: **/

PIN 15		= !DCNT		;	/* State bit for Zorro III stuff. */
PIN 20		= !DTSYNC	;	/* Synchronizer for DTACK->STERM. */
PIN 22		= !CYCZ3	;	/* On-bus Zorro III cycle. */

/** OUTPUT TERMS: **/

/* The Zorro III cycle starts on-bus as soon as it's certain to be a real
   cycle that's starting.  If just starting, the buffered FCS isn't 
   asserted but ASQ is. Once on, it stays on until a DTACK is properly
   noticed. */

CYCZ3		= !RST & MYBUS & !BFCS & ASQ & !BDTACK & !CLK
		# !RST & MYBUS & CYCZ3 & ASQ & !BDTACK;

/* The master-mode FCS is asserted onto the bus once we have determined
   a real out-to-bus Zorro III cycle should take place.  This wasn't
   originally clocked out, but I got nervous about ABOEH setup. */

EFCS		=   CLK & MYBUS & CYCZ3 & !RST
		#  EFCS & MYBUS & CYCZ3 & !RST;
EFCS.OE		= MYBUS & CYCZ3;

/* Get off the Zorro III bus right after the EFCS cycle ends, hold it
   until the local cycle ends. */

NOZ3		= MYBUS & BFCS & !CYCZ3
		# RST;

/* The data output enable has to wait until a safe "data phase".  This is 
   guaranteed to be two clocks after FCS falls.  DCNT is used to time
   this from cycle's start. */

DOE.D		= BFCS & !RST & !DOE & MYBUS & DCNT
		# BFCS & !RST &  DOE;
DOE.OE		= MYBUS;

/* This is a count phase from FCS, to ensure proper DOE assertion. */

DCNT.D		= BFCS & !DOE & !DCNT & MYBUS
		# BFCS & DCNT;

/* This signal samples a termination signal.  It used to sample EDTACK, but
   the quick turnoff of EFCS means that EDTACK may be gone before our sampling
   edge comes around.  Instead, the state where EFCS is negated but BFCS is
   asserted indicates that the EFCS logic has detected EDTACK. */

DTSYNC.D	= BFCS & !RST & DOE & BDTACK
		# BFCS & !RST & DOE & DTSYNC;
DTSYNC.AR	= !BFCS;

/* The SCSI termination is based on a synchronized DTACK.  I 
   synchronize DTACK for either slave or master cycle, since the 
   NCR 53C710 wants the effect of SLACK (which makes a DTACK on slave
   to SCSI cycles) reflected on STERM to actually end the cycle. */

STERM.D		= !RST &  MYBUS & BFCS & DTSYNC & !STERM & BDTACK
		# !RST & !MYBUS & BFCS & BDTACK & !STERM;
STERM.AR	= !BFCS;

/* We _never_ issue a CBACK, since BURST isn't supported. */

CBACK		= 'b'0;
CBACK.OE	= 'b'0;
		
/* We _never_ issue an MTCR, since BURST isn't supported. */

MTCR		= 'b'0;
MTCR.OE		= 'b'0;

/* The DTACK line is buffered into the rest of the board.  It actually
   latches the EDTACK line in various ways, since EDTACK isn't necessarily
   going to hang around long enough to be sampled. */

BDTACK		= !RST & BFCS & EDTACK
		# !RST & BFCS & BDTACK & !STERM;