PARTNO		U205 ;
	NAME		U205 ;
	DATE		April 1, 1993 ;
	REV		5 ;
	DESIGNER	Dave Haynie ;
	COMPANY		Commodore ;
	ASSEMBLY	A4091 ;
	LOCATION	West Chester ;
	DEVICE		g22v10 ;

/************************************************************************/
/*									*/
/*	A4091	Buffer and termination control.				*/
/*									*/
/*	This device manages data buffer direction, enable, and latch	*/
/*	functions, address buffer enable, and slave cycle termination.	*/
/*									*/
/************************************************************************/
/*									*/
/* DEVICE DATA:								*/
/*									*/
/*	Device:		22V10-15					*/
/*	Clock:		CLK (25MHz)					*/
/*	Unused:		16(I/O)						*/
/*									*/
/************************************************************************/
/*									*/
/* REVISION HISTORY:							*/
/*									*/
/*	DBH Jul  8:	Original version.				*/
/*	DBH Oct 26:	Extended data latching function.		*/
/*	DBH Nov  2:	Modified DTACK again for fast SCSI slave cycle	*/
/*			termination.					*/
/*	DBH Nov 19:	Changed DBOE for self-reference support.	*/
/*	DBH Mar 30:	Added NOZ3 term for quick Zorro III disconnect,	*/
/*			to eliminate the multiple A4091 problem.	*/
/*	DBH Apr  1:	Some more NOZ3-related tweaks.			*/
/************************************************************************/

/** INPUTS: **/

PIN 1		=  CLK		;	/* 25MHz system clock. */
PIN 2		= !SLAVE	;	/* Board select. */
PIN 3		= !MYBUS	;	/* The A4091 has the bus. */
PIN 4		=  DOE		;	/* Data phase on Zorro III. */
PIN 5		=  FCS		;	/* Z3 full cycle strobe. */
PIN 6		=  READ		;	/* The Zorro III read cycle. */
PIN 7		= !SLACK	;	/* The NCR 53C710 slave acknowledge. */
PIN 8		= !NOZ3		;	/* Get off the Z3 bus? */
PIN 9		=  INTREG	;	/* Interrupt register access. */
PIN 10		= !INTVEC	;	/* Interrupt vector access. */
PIN 11		= !CFGOUT	;	/* Configuration chain output. */
PIN 13		= !NACK		;	/* Network chip acknowledge. */
PIN 14		= !MTCR		;	/* Zorro III burst strobe. */
PIN 15		= !MASTER	;	/* SCSI chip owns the A3090 bus. */
PIN 16		= !SID    	;	/* SCSI ID. */

/** OUTPUTS: **/

PIN 18		= !D2Z		;	/* Data is transferred to Zorro III bus. */
PIN 19		= !Z2D		;	/* Data is transferred from Zorro III bus. */
PIN 20		=  DBLT		;	/* Data is latched. */
PIN 21		= !DBOE		;	/* Data transfer enable. */
PIN 22		= !ABOEL	;	/* Low order address transfer enable. */
PIN 23		= !ABOEH	;	/* High order address transfer enable. */

/** BIDIRECTIONALS: **/

PIN 17		= !DTACK	;	/* Zorro III termination. */

/** LOGICAL TERMS: **/

/* It takes both MYBUS and MASTER to fully qualify a cycle.  If MYBUS is 
   asserted but master not, we're in the process of bus arbitration.  If
   MASTER is asserted but not MYBUS, the SCSI chip is master of the A4091
   bus and waiting for a grant to the Zorro bus.  In both of these cases,
   as little as possible should be done. */

mastercyc	=  MYBUS &  MASTER;

slavecyc	= !MYBUS & !MASTER;

/** OUTPUT TERMS: **/

/* This is the data output enable control.  When data buffers are
   pointed toward the board, they can turn on early in the cycle.
   This is a write for slave access, a read for DMA access.  When
   the data buffers are pointed out toward the bus, the have to 
   wait until DOE to turn on; this is a slave read or DMA write. 
   When the board responds to itself, the buffers are left off.   If
   the NOZ3 signal is asserted on a write (eg, master driving the 
   Zorro III bus), DBOE must be negated immediately. */

DBOE		=  slavecyc &  SLAVE & !READ & FCS 
		#  slavecyc &  SLAVE &  READ & FCS & DOE
		# mastercyc & !SLAVE & !READ & FCS & DOE & !ABOEH & !NOZ3
		# mastercyc & !SLAVE &  READ & FCS;

/* The data buffer direction calculations are very simple.  The data to
   Zorro III connection is made for slave reads or DMA writes.  The Zorro III
   to data bus connection is made for slave writes or DMA reads. */

D2Z		=  slavecyc &  READ & FCS &  SLAVE
		# mastercyc & !READ & FCS & !SLAVE;

Z2D		=   slavecyc & !READ & FCS &  SLAVE
		#  mastercyc &  READ & FCS & !SLAVE;

/* For either kind of access, data is latched when DTACK is asserted and 
   we're in data time.  Data is held through the end of the cycle.  */

DBLT		=  slavecyc & FCS & DTACK & DOE &  SLAVE
		# mastercyc & FCS & DTACK & DOE & !SLAVE 
		#      DBLT & FCS;

/* The address buffer controls.  I want addresses going in unless the SCSI
   device has been granted the A3090 bus.  If so, addresses only go out when
   the A3090 has been granted the Zorro III bus.  High order addresses also
   go off quickly after FCS is asserted. */

ABOEL.D		=  slavecyc
		# mastercyc & !FCS
		# mastercyc &  FCS & ABOEL;
ABOEL.AR	= NOZ3;

ABOEH.D		=  slavecyc
		# mastercyc & !FCS;
ABOEH.AR	= NOZ3;

/* The board needs to generate a DTACK here for slave accesses.  Most
   of the slave terminations are very simple, since they're either 
   based on a termination signal (SLACK for SCSI, NACK for net or ROM)
   or they're instant (interrupt vector R/W).  During configuration,
   any write should also be instantly terminated, that would be a 
   configuration register write (reads are governed by ROM access). */

DTACK		= SLAVE & FCS & DOE & SLACK 
		# SLAVE & FCS & DOE & INTREG
		# SLAVE & FCS & DOE & INTVEC
		# SLAVE & FCS & DOE & SID
		# SLAVE & FCS & DOE & NACK
		# SLAVE & FCS & DOE & !CFGOUT & !READ
		# SLAVE & FCS & DOE & DTACK;

DTACK.OE	= SLAVE & FCS & !NOZ3;