PARTNO	  XXXXX ;
		NAME	  U701;
		DATE	  April 6, 1989;
		REV	  1 ;
		DESIGNER  Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  A30000 ;
		LOCATION  U701 ;

/************************************************************************/
/*									*/
/*  A3000	Interrupt mixing and latch logic			*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 16R4A	 			*/
/************************************************************************/
/*  Clock:		7Mhz						*/
/************************************************************************/
/*  Free Pins:		9(I),13(I/O)					*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Apr  5:	Completely new.					*/
/************************************************************************/

/**  Inputs  **/

PIN 2		= !CIPL0	;	/* Chip conditioned interrupts */
PIN 3		= !CIPL1	;
PIN 4		= !CIPL2	;
PIN 5		= !PINT1	;	/* Bus interrupts */
PIN 6		= !PINT4	;
PIN 7		= !PINT5	;
PIN 8		= !PINT7	;
PIN 9		= !INTENB	;	/* Interrupt enable */

/**  Outputs  **/

PIN 17		= !IPL0		;	/* CPU interrupts */
PIN 16		= !IPL1		;
PIN 15		= !IPL2		;

/** Declarations and Intermediate Variable Definitions **/

level0	= !CIPL2 & !CIPL1 & !CIPL0 & !(PINT1 # PINT4 # PINT5 # PINT7);

level1	= !CIPL2 & !CIPL1 &  CIPL0 & !(PINT4 # PINT5 # PINT7)
	#  PINT1 & !(PINT4 # PINT5 # PINT7);

level2	= !CIPL2 &  CIPL1 & !CIPL0 & !(PINT4 # PINT5 # PINT7);

level3	= !CIPL2 &  CIPL1 &  CIPL0 & !(PINT4 # PINT5 # PINT7);

level4	=  CIPL2 & !CIPL1 & !CIPL0 & !(PINT5 # PINT7)
	#  PINT4 & !(PINT5 # PINT7);

level5	=  CIPL2 & !CIPL1 &  CIPL0 & !PINT7
	#  PINT5 & !PINT7;

level6	=  CIPL2 &  CIPL1 & !CIPL0 & !PINT7;

level7	=  CIPL2 &  CIPL1 &  CIPL0 
	#  PINT7 ;

/**  Logic Equations  **/

IPL2.D	= level7 & INTENB
	# level6 & INTENB
	# level5 & INTENB
	# level4 & INTENB ;

IPL1.D	= level7 & INTENB
	# level6 & INTENB
	# level3 & INTENB
	# level2 & INTENB ;

IPL0.D	= level7 & INTENB
	# level5 & INTENB
	# level3 & INTENB
	# level1 & INTENB ;