PARTNO	  XXXXX ;
		NAME	  KLUDGE1;
		DATE	  October 9, 1989;
		REV	  3 ;
		DESIGNER  Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  A30000 ;
		LOCATION  U714 ;

/************************************************************************/
/*									*/
/*  A3000	System Kludge Chip : Fixes Buster problems		*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 20L8-15	 			*/
/************************************************************************/
/*  Free Pins: NONE							*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Sep 18:	Completely new.					*/
/*	DBH Oct  4:	Axed BG0 in order to fix holding problem.	*/
/*	DBH Oct  9:	Added ABOE2* to fix contention problem.		*/
/************************************************************************/

/**  Inputs  **/

PIN 1		= !SLV3		;	 /* Expansion Bus slave strobes */
PIN 2		= !SLV2		;
PIN 3		= !SLV1		;
PIN 4		= !SLV0		;
PIN 5		= !DBOE1	;	/* Data enable 1 */
PIN 6		= !DBOE0	;	/* Data enable 0 */
PIN 7		= !DBR16	;	/* Data bridge for 16 bit DMA */
PIN 8		= !BG3		;	/* Expansion Bus grant strobes */
PIN 9		= !BG2		;
PIN 10		= !BG1		;
PIN 11		= !ABOE2	;	/* High order address enable */
PIN 13		= !AS		;	/* Local bus address strobe */
PIN 14		= !DSACK1	;	/* Cycle termination strobes */
PIN 23		= !DSACK0	;
PIN 21		= !OWN		;	/* Expansion owns local bus */

/**  Outputs  **/

PIN 20		= !DBR16x	;	/* Modified DBR16 */ 
PIN 19		= !DBOE0x	;	/* Modified DBOE0 */
PIN 18		= !DBOE1x	;	/* Modified DBOE1 */
PIN 16		= !BG1x		;	/* Modified bus grants */
PIN 15		= !BG2x		;
PIN 22		= !BG3x		;

/**  Used internally  **/

PIN 17		= !BGENB	;	/* Enable bus grants? */

/** Declarations and Intermediate Variable Definitions **/

/* When any slave is happening */

anyslv		= SLV0 
		# SLV1
		# SLV2
		# SLV3;

/* When the bus is clear of activity.  This should be more robust, but 
   there's a pin limitation here, so we can't look at BGACKs or STERM. */

busfree		= !OWN & !AS & !DSACK0 & !DSACK1;

/**  Logic Equations  **/

BGENB		= BG3 & busfree
		# BG3 & BGENB
		# BG2 & busfree
		# BG3 & BGENB
		# BG1 & busfree
		# BG1 & BGENB;

/* Here's the new bus grant logic.  The problem with bus grants in the
   current Buster chip is the issue of hidden cycles.  The expansion bus
   can't be taken over by a DMA device until that device has asserted
   its BR*, received BG*, and then asserted OWN* and BGACK* once the bus
   is clear of activity.  The problem is, Zorro II expansion devices now 
   can't see local-only activity -- chip cycles and anything outside of
   MEMZ2 and IOZ2 never show up on the expansion bus.  So the bus arbiter,
   Buster in this case, must spy the hidden cycles and pass on BG* only
   when the bus is clear.  The A2630 actually does this same thing.  If we
   don't do this, there's an excellent chance that DMA from the expansion
   bus will start in the midst of a local bus cycle, corrupting at least
   the action of that cycle, if not subsequent cycles.  The real Buster
   fix should also assure that the BGn outputs are asserted on the 7M edge,
   which this doesn't guarantee.  It's generally not a problem, but it is
   the spec.
*/

BG1x		= BG1 & BGENB;
BG2x		= BG2 & BGENB;
BG3x		= BG3 & BGENB;

/* The next problem is the action of the local<->expansion data buffers.
   When an expansion slave responds to an expansion master, the bus buffers
   are supposed to turn off all data buffers.  Unfortunately, somehow this
   snuck by again; the buffers remain on in the current Buster chip.  The
   below equations solve this problem properly.  I don't think it's 
   necessary to modify DBOE0 here, since it's not driven during 16 bit
   DMA in any case. */

DBR16x		= DBR16 & !(OWN & anyslv);

DBOE0x		= DBOE0 & !(OWN & anyslv);

DBOE1x		= DBOE1 & !(OWN & anyslv);