Partno		390527-02;
Name            (CHIPCASC.PLD) 32 bit chip RAM logic.;
Date            02/12/90;
Rev             2;
Designer        Greg Berlin;
Company         CBM;
Assembly        ;
Location        U203;

/* Target PAL Device : 16L8-10 */

/**************************************************************************/
/*                           R E V I S I O N S                            */
/**************************************************************************/
/*                                                                        */
/*    -02 - Added term in LA19 to allow for static column DRAM            */
/*          (This was actually in the -01 spec, but the original parts in */
/*          production were burned wrong.  -02 is used to avoid confusion */
/*                                                                        */
/**************************************************************************/

/* INPUTS */

pin 11 	= !CASL;	/* CAS'es out of AGNUS */
pin 9	= !CASU;

pin 3	= MA9; 		/* Mux'ed address bit 9. Has A20 value at CAS time */
pin 7	= MA0I;		/* Mux'ed address bit 0. Has A1 value at CAS time */
pin 6	= !BLIT;	/* If low, then BLITTER is doing the accessing */
pin 1   = !CDAC;
pin 8	= !WE;
pin 2	= !UUDS;
pin 5	= LA19;		/* Latched address bit A19 */
pin 4	= !LMDS;
pin 17	= C3;

/* OUTPUTS */

pin 14 	= !CAS5;
pin 13	= !CAS7;
pin 18	= !BRIDGE;	/* Bridge D0-D15 to D16-D31 during CHIP access */
pin 15	= BRIDGEDIR;	/* Direction to bridge data buses */
pin 16	= !RAMOE;	/* Output enable for RAMs */
pin 19	= MA0O;		/* Mux'ed Adr bit 0 output */


A1	= MA0I;
A20	= MA9;


CAS5	= !BLIT & (CASL # CASU) & LMDS & CDAC & C3 & !A20 /* start it for 68030 access */
	#  BLIT & CASU & CDAC & C3 & !A20 & A1 	 	  /* start it for CHIP access */
	# CAS5 & (CASL # CASU);				  /* Finish it up for both */

CAS7	= !BLIT & (CASL # CASU) & LMDS & CDAC & C3 & A20  /* start it for 68030 access */
	#  BLIT & CASU & CDAC & C3 & A20 & A1	 	  /* start it for CHIP access */
	# CAS7 & (CASL # CASU);				  /* Finish it up for both */

!MA0O	= !CDAC & !MA0I & !CASU & !CASL	/* Pass A9 thru at RAS time */
	# CDAC & !LA19			/* Substitute A19 for A1 at CAS time */
	# !LA19 & (CASU # CASL);	/* Hold for static column DRAM (-02) */

BRIDGE	/*= BLIT 
	# BRIDGE & (CASU # CASL);*/

	= BLIT & C3 & CDAC & WE		/* ALWAYS Bridge on a write... */
	# BLIT & C3 & CDAC & A1		/* ... or if A1 is high.       */
	# BRIDGE & (CASU # CASL);	/* Hold it on ... */


!BRIDGEDIR	/*= BLIT & A1 & !WE & (CASU # CASL) & CDAC & C3*/  /* (BUS B to BUS A) */
		/*# !BRIDGEDIR & (CASU # CASL);*/
	= !WE
	# !BRIDGEDIR & (CASU # CASL);

RAMOE	/*= (CASU # CASL) & !CDAC & C3 & !WE*/  /* Delay by 35 ns to allow the data drivers to */
	/*# RAMOE & (CASU # CASL);*/
	= !WE
	# RAMOE & (CASU # CASL);