.so /usr/lib/tmac/tmac.e .po 1i .ll 6.5i .he ''%'' .fo '''' .tp .sp 1.5i .(l C 100 Pin Expansion Signals on Amiga Computers .sp 4 by Dave Haynie .sp 1 July 20, 1987 .sp 4 .)l .(z L F .(c .ce 1 .uh "ABSTRACT" .sp This document details the signals found on the 100 pin standard Amiga expansion connector. The main point of this document is to discuss the signals found on the B2000 computer and how these differ from the similar signals found on A2000 computers and those of the original Zorro specification and A1000 computers. .)c .)z .bp 1 .sh 1 "Introduction" .pp This document details the signals found on the 100 pin standard Amiga expansion connector. The main point of this document is to discuss the signals found on the B2000 computer and how these differ from the similar signals found on A2000 computers and those of the original Zorro specification and A1000 computers. Anytime something is specified for the A2000, it is also true for the B2000 unless otherwise stated. .sh 2 "Changes From Previous Documents" .pp We've attempted to keep the Expansion Bus pin specification as much the same as possible from machine to machine. However, especially concerning the changes from the original specification to the A2000 specifications, there were indeed some major changes made. Although these changes will affect relatively few boards, they're non-trivial for the boards that they do affect. In this case, we basically chose to sacrifice a small fraction of our compatibility for a reasonably large increase in the power of the Expansion Bus. Just about all of the currently existing A1000 expansion boards will work, unmodified, on the B2000 Expansion Bus (the physical shape of the boards, of course, has changed). If at all possible, add-in boards should be designed for the Expansion Bus. There are multiple slots so that up to five Expansion devices can work together, and in addition only Expansion Bus devices can fully support the autoconfiguration standard. The 86 pin Coprocessor Slot is designed to house a single board that's acting as a Coprocessor or replacement processor in the system. This slot looks very much like the A1000 edge connector, though on the B2000 is supports a few new signals. As an example, a 68020 board would logically be placed here, though such boards may also be designed as Expansion devices\**. .(f \**Please refer to the paper "Coprocessor Expansion and 86 Pin Signals on Amiga Computers" by Dave Haynie, for a complete treatment of this capability. .)f .pp Most of the Expansion Bus signals are buffered. This is an important point to consider, for buffered signals may become critical in any timing analysis, while unbuffered signals may become critical in any loading analysis. Buffered signals are typically either inputs or some synchronous bidirectionals; outputs and asynchronous bidirectionals can't easily be buffered. .sh 2 "Definition of Terms" .pp Several terms are used in the following text, and an understanding of them is required to speak proper Amiga-ese. A device known as a .u PIC , or Plug In Card, is a device that plugs into an expansion slot and follows the auto-configuration protocol. Nothing should plug into a 100 pin slot that doesn't follow this protocol. The term .u "slot" refers to a physical plug in location, either the Coprocessor Slot or one of the five available Expansion Slots. The terms .u 100 .u Pin .u Slot and .u Expansion .u Slot are considered synonyms, and describe one of the five 100 pin Expansion Slots. The .u Expansion .u Bus is the processor bus that is in common between all Expansion Slots. The terms .u 86 .u Pin .u Slot, .u Coprocessor .u Slot, and .u Local .u Slot are considered synonyms, and pertain to the 86 pin Coprocessor Slot in the A2000 and B2000. The terms .u 86 .u Pin .u Edge and .u Expansion .u Edge are considered synonyms, and pertain to the 86 pin Expansion Edge in the A1000 and A500. The .u Local .u Bus is the processor bus directly connected to the 68000 processor and the Coprocessor Slot or Expansion Edge; both the Coprocessor Slot and Expansion Edge are considered Local Bus Ports. Each different implementation of a hardware design is termed an .u Instance of that design; thus, the A2000's Expansion Bus, the B2000's Expansion Bus, and all third party ZORRO backplanes for the A1000 or A500 are instances of the Expansion Bus. .pp Along with an understanding of Amiga bus terms, a familiarity with Motorola's 68000 processor and its characteristic names for things will also be very useful in understanding this document. .sh 1 "Power Connections" .pp The Expansion Bus provides several different voltages designed to supply expansion devices. The A2000 power supply is currently rated at 200 Watts, which supplies the main board and all other expansion ports as well as the Expansion Bus. .sh 2 "Digital Ground (Ground)" .pp Digital supply ground used by all expansion cards as the return path for all expansion supplies. This are found on all instances of the Expansion Bus. See Appendix for pin assignments. .sh 2 "Main Supply (+5V)" .pp Main power supply for all expansion cards, and is capable of sourcing large currents; each Expansion Slot can draw up to 2.0 Amps of +5, and a single Slot can draw as much as 4 Amps if necessary, for devices such as 8 megabyte RAM cards. The maximum supply currert for the entire A2000 system is 20 Amps on the +5 supply. All ports open to the outside of the box have their own, separate +5 supply that's short protected, thus no loads external to the A2000 box need be considered. This supply is found on all instances of the Expansion Bus, though the available currents may vary. Pins: 5, 6. .sh 2 "Negative Supply (-5V)" .pp Negative version of the main supply, for small current loads only; there's a total of 0.3 Amp for the entire A2000 system. Found on all instances of the Expansion Bus, though the available currents may vary. Pin: 8. .sh 2 "High Voltage Supply (+12V)" .pp Higher voltage supply, useful for communications cards an other devices requiring greater that digital voltage levels. This is intended for small loading only; there's a total of 8 Amps for the entire A2000 system, much of which is normally devoted to floppy and hard disk drive motors. Found on all instances of the Expansion Bus, though the available currents may vary. Pin: 10. .sh 2 "Negative High Supply (-12V)" .pp Negative version of the high voltage supply, also commonly used in communications applications, and similarly intended for small loads only; there is a total of 0.3 Amp for the entire A2000 system. This pin is an extension of the original Zorro specification, and is found in all A2000 machines. Pin: 20. .sh 1 "Clock Signals" .pp The Expansion Bus provides clock signals for expansion boards. They are generally used to allow clocked logic to be used in designs instead of delay lines. .sh 2 "/C1 Clock" .pp This is a 3.58 MHz clock (3.55 MHz on PAL systems) that's synched to the falling edge of the 7M system clock. Also known as /CCK in some places. Pin 16. .sh 2 "/C3 Clock" .pp This is a 3.58 MHz clock (3.55 MHz on PAL systems) that's synched to the ising edge of the 7M system clock. Also known as /CCKQ in some places. Pin 14. .sh 2 "CDAC Clock" .pp This is a 7.16 MHz clock (7.09 MHz on PAL systems) that leads the 7M system clock by 70ns (90 degrees). Pin 15. .sh 2 "E Clock" .pp This is the 68000 generated "E" clock, used for 6800 family peripherals driven by "E" and 6502 peripherals driven by PHI2. This clock is six 7M clocks high, four clocks low, as per the 68000 spec. Pin 50. .sh 2 "7M Clock" .pp This is the 7.16 MHz system clock (7.09 MHz on PAL systems). The A2000/B2000 design has true 7M which is actually in common with the 68000's clock input. On the original ZORRO bus specification this was the EQU7MHz signal, a 7M equivalent made using the relationship EQU7MHz = /C1 XNOR /C3. Because of this, there may be some timing differences in this signal among different vendors of ZORRO expansion boards and between these ZORRO boards and the A2000/B2000 system. It is possible to create an EQU7MHz clock on a ZORRO board that is nearly identical to the internal version, as on an A2000 the signal is created using exactly this aforementioned relationship. Pin 92. .sh 1 "Addressing and Control Signals" .pp These signals are various items used for the addressing of devices on the bus by the 68000 and any DMA devices. Most of these signals are buffered versions of similar 68000 signals, and are bidirectionally buffered to allow any DMA device on the bus to drive the 68000 local bus when such a device is a bus master. .sh 2 "Read Enable (READ)" .pp Read enable for the bus, which is a buffered version of the 68000's R/W output. Read asserted indicates a read or internal cycle, read negated indicates a write cycle. Pin 68. .sh 2 "Address Bus (A1-A23)" .pp This is a buffered version of the 68000's address bus, providing 16 megabytes of address space, though only 8 megabytes of this address space is available to expansion bus devices. Expansion boards should only respond to address ranges assigned them during configuration, otherwise addressing conflicts between multiple boards will arise. See Appendix for pin list. .sh 2 "Address Strobe (/AS)" .pp The falling edge of this strobe indicates that addresses are valid, the rising edge signals the end of an Expansion Bus memory cycle. This is a buffered version of the 68000 /AS signal. Found on pin 74. .sh 2 "Data Bus (D0-D15)" .pp This is a buffered version of the 68000's data bus, providing 16 bits of data accessible by word or either byte. Note that the data bus is enabled by /AS asserted, so the data bus is not expected to have any significant hold time beyond /AS negated. During write cycles in most design applications /AS should not be used to latch data. During read cycles, the enabling of the data bus is delayed to give the collision detection circuitry time to detect any collisions before data is enabled, thus avoiding any fights among the data drivers of multiple PICs. See Appendix for pin list. .sh 2 "Data Strobes (/LDS, /UDS)" .pp This these are buffered versions of the 68000's upper and lower data strobes. The strobes fall on data valid during transfer; the lower strobe being used for the lower byte (even byte address), the upper strobe being used for the upper byte (odd byte address). These are considered by the data bus buffers during read cycles, in case the cycle actually turns out to be a read-modify-write cycle. They're ignored during write cycles, since they can become valid quite late in the cycle, and a late enable would require unnecessarily fast data handling in certain PIC applications. Pins: 70, 72. .sh 2 "Valid Memory Address (/VMA)" .pp Unbuffered output from the 68000 indicating a valid address for 6800 style peripheral devices, in response to a /VPA input. Pin 51. .sh 2 "Valid Peripheral Address (/VPA)" .pp Unbuffered input to the 68000 indicating the address has selected a 6800 or 6502 style peripheral, so the 6800 style peripheral access should take place. Pin 48. .sh 2 "Data Transfer Acknowledge (/DTACK)" .pp This signal is logically associated with the 68000's Data Transfer Acknowledge input. Normally in the Amiga system, Amiga system logic creates /DTACK for a simple, no-wait state cycle (this may be varied by the custom chips). Therefore, this signal is treated as an output to the Expansion and Coprocessor Slots, for most situations. Any slow device on the bus that needs to control /DTACK may do so by negating XRDY to hold off /DTACK or asserting /OVR very quickly to tri-state /DTACK. Note that depending upon when /AS is asserted by a bus master when accessing the CHIP memory, one of two possible cycles may result. If /AS is asserted during C1 low, C3 low, the bus cycle is considered "in-sync", and will proceed, with /DTACK driven as for a normal, 4 tick clock cycle. If instead, /AS is asserted during C1 high , C3 high, the bus cycle is considered "out of sync" and the internally generated /DTACK will be held off, causing a wait state that's designed to "sync-up" the DMA cycle with the custom chip's memory cycle. This signal is on pin 66. .sh 2 "Processor Status (FC0-FC2)" .pp These signals are the buffered versions of the 68000 Processor Status outputs, which can be used by bus devices to determine the internal state of the 68000 any time /AS is asserted. Pins 31, 33, 35. .sh 2 "Bus Error (/BERR)" .pp This is an input that goes directly to the 68000. It's used to indicate some kind of bus error occurring. Any expansion card capable of detecting a bus error relating directly to that card can assert /BERR when that bus error condition is detected. At other times, the card must monitor /BERR and be prepared to tri-state all of its on-bus output buffers whenever this signal is asserted. Since any number of devices may assert /BERR, and all bus cards must monitor it, any device that drives /BERR must drive with an open collector or similar device capable of sinking at least 12ma, and any device that monitors /BERR should place as little load on it as possible (1 "F" type load or less, per board, is suggested). This signal is connected to a low valued motherboard pullup resistor, and shouldn't need any more pulling up. Pin 46. .sh 2 "System Reset (/RST, /BUSRST)" .pp Pin 53 of the bus contains the /RST signal, pin 94 contains the /BUSRST signal. Both of these reflect system reset, however, the /RST signal is bidirectional, unbuffered, and in common with the original 68000 reset signal. It should only be used on boards that are capable of resetting the system. The /BUSRST signal is a buffered output-only version of the reset signal that should be used as the normal reset input to boards not concerned with resetting the system on their own. The /RST signal is connected to a medium valued motherboard pullup resistor and shouldn't need any more pulling up. .sh 2 "System Halt (/HLT)" .pp This is the 68000's processor halt signal, tied directly to the 68000. It is connected to a medium valued on-board pullup resistor and shouldn't need any more pulling up. This signal, when driven by a PIC, will halt and tristate the 68000 at the end of the current bus cycle. If driven by the 68000, it indicates detection of a double bus fault. Pin 55. .sh 2 "System Interrupts" .pp Six of the 68000 interrupts are available on the Expansion Bus, and these are labelled as /INT2, /INT6, /EINT1, /EINT4, /EINT5, /EINT7. The interrupt structure of the original ZORRO specification has been slightly changed for the A2000/B2000. This change affects the availability of decoded interrupt inputs and multiplexed interrupt inputs. Specifically, the 68000 accepts 7 levels of interrupt that are presented to it as 8 possible values priority encoded into 3 multiplexed inputs. The original ZORRO specification called for decoded interrupt inputs on pin 19 for interrupt level 2 (/INT2), and on pin 22 for interrupt level 6 (/INT6). These are the same interrupts used by the Amiga internal system chips and encoded by the Paula chip. The interrupts could be used by external devices by wired ORing interrupt requests into one of these available interrupts. The original ZORRO bus also provides the encoded interrupt lines /IPL0, /IPL1, and /IPL2 on bus pins 40, 42, and 44 respectively. These are useless as inputs, but as outputs are required by any Coprocessor or alternate processor that needs to monitor system interrupts. In the A2000/B2000 scheme, coprocessors sit in the Coprocessor Slot which allows them full control of the system. The encoded interrupt lines have been replaced with decoded interrupt lines that may be freely used as inputs; interrupt levels 7 (/EINT7), 5 (/EINT5), and 4 (/EINT4) are available now on bus pins 40, 42, and 44 respectively, and the level 1 interrupt (/EINT1) is available on bus pin 96 which is left open in the ZORRO specification. See Appendix for pin list. .sh 2 "Override (/OVR)" .pp The /OVR, or Override, signal is a special Amiga expansion signal that can serve two purposes. The signal can basically turn off the on-board decoding of system memory ranges, including those used by the Amiga custom chips. As a result of this, it can also turn off internally generated things, like /DTACK. The timing in the A500 and B2000, based on the Gary chip (not the PALs of the older machines), effectively prohibits the use of /OVR for the area of address space outside of the $200000-$9FFFFF (Expansion Bus) range. .pp The supported use of this signal is to allow PICs to create their own /DTACK. Asserting /OVR will tri-state the motherboard generated /DTACK signal, allowing a Coprocessor or Expansion device to create its own /DTACK. The same effect can be achieved for most applications by using XRDY to delay the motherboard's generation of /DTACK. Pin 17. .sh 2 "External Ready (XRDY)" .pp This input provides a way for an external device to delay the motherboard generated /DTACK, for things like slow memory and I/O boards that need to add wait states. This signal should be negated very quickly, no later than 60ns from address valid (/AS asserted), in order for the motherboard circuitry to have enough time to prevent the normal assertion of /DTACK. XDRY should stay negated for as many wait states are required. Once XRDY is asserted, /DTACK completes the rest of the normal cycle. XRDY is a wired-OR input; it is pulled up by a resistor on the motherboard, and should be driven with an open collector or equivalent output. Pin 18. .sh 1 "Slot Control Signals" .pp This group of signals is responsible for the control of things that happen between Expansion Slots. .sh 2 "Slave (/SLAVEn)" .pp Pin 9 is the SLAVEn signal, where "n" refers to the Expansion Slot number. Each Slot has its own SLAVE output, all of which go into the collision detect circuitry. Whenever a PIC is responding to a decoded address range, it must assert its SLAVE output within 35ns of /AS asserted. The SLAVE output must be negated at the end of a cycle within 50ns of /AS negated. If more than one SLAVE output occurs for the same address, or if a PIC asserts its SLAVE output for an address reserved by the local bus, a collision is registered and results in /BERR being asserted. .sh 2 "Configuration Chain (/CFGINn, /CFGOUTn)" .pp Pins 11 and 12 are, respectively, the /CFGOUTn and /CFGINn signals, where "n" refers to the Expansion Slot number. Each Slot has its own version of each, which make up the configuration chain between Slots. Each subsequent /CFGIN is a result of all previous /CFGOUTs, going from slot 1 to slot 5 on the Expansion Bus. On the B2000, the 86 pin coprocessor has CONFIG priority 0, which chains directly into Expansion Slot 1. This enforces the order of autoconfiguration between slots. During the autoconfiguration process, an unconfigured PIC responds to the 64K address space starting at $E80000 if its CFGIN signal is asserted. All unconfigured PICs come up with CFGOUT negated. When configured, or told to "shut up", a PIC will assert is CFGOUT, which results in the CFGIN of the next slot to be asserted. On-board logic automatically passes on the state of the previous CFGOUT to the next CFGIN for any slot not occupied by a PIC, so there's no need to sequentially populate the Expansion Bus Slots. .sh 2 "Data Output Enable (DOE)" .pp This signal is used by an expansion card to enable the buffers on the data bus. The signal's timing changes from read cycle to write cycle. Pin 93. .sh 1 "DMA Control Signals" .pp There are various signals on the Expansion Bus that coordinate the arbitration of DMAs that may be requested by devices on the Expansion Bus. .sh 2 "PIC is DMA Owner (/OWN)" .pp Asserted by Expansion Bus DMA device when it becomes bus master. This output is to be treated as a wired-OR output between all Expansion Slots, any of which may have a PIC signalling bus mastership. Thus, this should be driven with an open-collector or similar output by any PIC using it. Found on pin 7. .sh 2 "Slot Specific Bus Arbitration (/BRn, /BGn)" .pp Pins 60 and 64 are, respectively, the /BRn and /BGn signals, where "n" refers to the Expansion Slot number. Each Slot has its own version of each signal. The Bus Request and Bus Grant from each board go to some prioritization circuitry, and then to the 68000. Slot 1 has the highest priority, Slot 5 the lowest, out of the Expansion Slots. On a B2000, the Coprocessor Slot is included in this priority chain when it's not acting as a coprocessor, and it acts as priority level 0, right before that of slot 1. Note that along with the request prioritization logic, the bus requests are clocked by the rising edge of the 7M clock, and it's a very good idea for any PIC requesting the bus to similarly clock its Bus Request output. This design prohibits any astable or race conditions that can occur when two PICs desire to own the bus asynchronously. Found on pins 60, 64, respectively. .sh 2 "Bus Grant Acknowledge (/BGACK)" .pp This is the unbuffered 68000 /BGACK signal. Any PIC that receives a bus grant from the 68000 should assert this signal as long as the DMA continues, releasing it once the DMA request is finished. This signal should never be asserted until the Bus Grant has been received, AS is negated, DTACK is negated, and BGACK itself is negated, indicating that all other potential bus masters have relinquished the bus. This output is driven as a wired-OR output, so all devices driving it must drive it with an open collector or equivalent device. Pin 62. .sh 2 "Processor Bus Grant (/BG, /GBG)" .pp The A1000 and A2000 systems receive the the /BG (bus grant) signal from the 68000 directly, unchanged, in addition to the slot specific /BGn signals. This was actually a late change to the original ZORRO specification, so it may not be on every A1000 ZORRO expansion box. This has changed slightly on the B2000 system as part of the coprocessor interface. The B2000's bus pin 95 is /GBG, Generic Bus Grant. When the 68000 is in charge, /GBG will be essentially a buffered /BG. When the coprocessor is in charge, /GBG will be a buffered /CBG. This allows all card in the expansion bus to function without concern as to which processor is actually controlling the bus. .sh 1 "Reserved Pins" .pp Pins 96, 97, and 98 have been left open for future expansion. .sh 1 "Appendix" .pp There are three instances of the Expansion Bus, the original A1000/ZORRO specification, and the A2000 enhancement to this original spec, and the B2000 specification. The ZORRO specification is treated as a single instance for the purposes of this chart, even though there are several different ZORRO bus implementations from several different hardware manufacturers. .TS expand; c c c c c c n c c c c l. PIN ZORRO A2000 B2000 Buffered? Function 1 X X X N/A Ground 2 X X X N/A Ground 3 X X X N/A Ground 4 X X X N/A Ground 5 X X X N/A +5VDC 6 X X X N/A +5VDC 7 X X X N/A /OWN 8 X X X N/A -5VDC 9 X X X N/A /SLAVEn 10 X X X N/A +12VDC 11 X X X N/A /CFGOUTn 12 X X X N/A /CFGINn 13 X X X N/A Ground 14 X X X Yes /C3 Clock 15 X X X Yes CDAC Clock 16 X X X Yes /C1 Clock 17 X X X No /OVR 18 X X X No XRDY 19 X X X No /INT2 20 X N/A No Connect X X N/A -12VDC 21 X X X Yes A5 22 X X X No /INT6 23 X X X Yes A6 24 X X X Yes A4 25 X X X N/A Ground 26 X X X Yes A3 27 X X X Yes A2 28 X X X Yes A7 29 X X X Yes A1 30 X X X Yes A8 31 X X X Yes FC0 32 X X X Yes A9 33 X X X Yes FC1 34 X X X Yes A10 35 X X X Yes FC2 36 X X X Yes A11 37 X X X N/A Ground 38 X X X Yes A12 39 X X X Yes A13 40 X No /IPL0 X X No /EINT7 41 X X X Yes A14 42 X Yes /IPL1 X X Yes /EINT5 43 X X X Yes A15 44 X No /IPL2 X X No /EINT4 45 X X X Yes A16 46 X X X No /BERR 47 X X X Yes A17 48 X X X No /VPA 49 X X X N/A Ground 50 X X X No E Clock 51 X X X N/A /VMA 52 X X X Yes A18 53 X X X No /RST 54 X X X Yes A19 55 X X X No /HLT 56 X X X Yes A20 57 X X X Yes A22 58 X X X Yes A21 59 X X X Yes A23 60 X X X N/A /BRn 61 X X X N/A Ground 62 X X X No /BGACK 63 X X X Yes D15 64 X X X N/A /BGn 65 X X X Yes D14 66 X X X No /DTACK 67 X X X Yes D13 68 X X X Yes READ 69 X X X Yes D12 70 X X X Yes /LDS 71 X X X Yes D11 72 X X X Yes /UDS 73 X X X N/A Ground 74 X X X Yes /AS 75 X X X Yes D0 76 X X X Yes D10 77 X X X Yes D1 78 X X X Yes D9 79 X X X Yes D2 80 X X X Yes D8 81 X X X Yes D3 82 X X X Yes D7 83 X X X Yes D4 84 X X X Yes D6 85 X X X N/A Ground 86 X X X Yes D5 87 X X X N/A Ground 88 X X X N/A Ground 89 X X X N/A Ground 90 X X X N/A Ground 91 X X X N/A Ground 92 X N/A EQU7MHz X X No 7M 93 X X X N/A DOE 94 X X X Yes /BUSRST 95 X X No /BG X Yes /GBG 96 N/A No Connect X X No /EINT1 97 X X X N/A No Connect 98 X X X N/A No Connect 99 X X X N/A Ground 100 X X X N/A Ground .TE