PARTNO Combo ; NAME Combo ; DATE August 10, 1993 ; REV 0 ; DESIGNER Dave Haynie ; COMPANY Commodore ; ASSEMBLY Nyx ; LOCATION West Chester ; DEVICE g16V8 ; /************************************************************************/ /* */ /* Combo RAM Control PAL for the "combo" RAM board. */ /* */ /* This device manages configuration, buffer enables, and VRAM */ /* write strobe for the Nyx VRAM/DRAM module. */ /* */ /************************************************************************/ /* */ /* DEVICE DATA: */ /* */ /* Device: 16V8-15 */ /* Clock: NONE */ /* Unused: 13(IO) */ /* */ /************************************************************************/ /* */ /* REVISION HISTORY: */ /* */ /* DBH Aug 10: Original version. */ /* */ /************************************************************************/ /** INPUTS: **/ PIN 2 = !ALE ; /* Chip bus address latch enable */ PIN 3 = VRAM ; /* VRAM is on board */ PIN 4 = !CFGRD ; /* Chip bus autoconfig cycle */ PIN 5 = !WE ; /* Chip bus write cycle */ PIN [6..9] = [SZ0..3] ; /* Local size bits */ PIN 11 = SLOTID ; /* Which slot for this module? */ PIN 18 = !DRAS0 ; /* DRAM RAS bank 0. */ PIN 19 = !DRAS1 ; /* DRAM RAS bank 1. */ /** OUTPUTS: **/ PIN 12 = !VWE ; /* Gated VRAM write enable */ PIN 14 = !DOE ; /* Data bridge output enable */ PIN 15 = DIR ; /* Data bridge direction */ PIN 16 = !CLOE ; /* Config low output enable */ PIN 17 = !CHOE ; /* Config high output enable */ /** INTERNAL TERMS: **/ /* Configuration is done on-module if it's shut off for the motherboard. */ modcon = SZ0 & SZ1; /* Names for supported motherboard modes. Only DRAM can use the 2MB mode. */ loc1MD = !SZ0 & SZ1 & !VRAM; loc1MV = !SZ0 & SZ1 & VRAM; loc2M = SZ0 & !SZ1 & !VRAM; /* Names for the on-module modes (see below). */ mod4M = modcon & !SZ2 & !SZ3; mod8M = modcon & SZ2 & !SZ3; modmix = modcon & !SZ2 & SZ3; /* The VRAM is on when using motherboard configuration and VRAM is set, or when using the module's configuration in mode 2. */ anyVRAM = loc1MV # modmix; /** OUTPUT TERMS: **/ /* The current Andrea contains a bug, it doesn't handle the write-per-bit mask function in VRAM. To eliminate this problem, WE* is gated out to the VRAM after RAS falls. Since ALE* falls after RAS*, this is a simple equation. No point wiggling it if no VRAM is present. */ VWE = WE & ALE & anyVRAM; /* The data bridge is a bridge that sits between the A/D bus and the graphics bus, to allow the data on a DRAM system to make it out to the graphics bus. When DRAM is in the system and being read, there should be a connection from the A/D bus to the graphics bus. There is no need to go the other way. */ DOE = !WE & ALE & DRAS0 & !VRAM # !WE & ALE & DRAS1 & loc2M # !WE & ALE & DRAS2 & mod8M; /* This just sets the buffer to drive from the A/D bus to the graphics bus. */ DIR = 'b'1; /* This combo module will support a couple of configurations in which it drives configuration data, rather than the motherboard. All of these require that SZ0 = SZ1 = 1, which turns off motherboard-based decoding. The main idea here is to support 4MB modules, which we can do using 1MBx32 DRAM SIMMs, rather than 256Kx32. The jumper block JB2 does this, but there weren't enough inputs here to take in all the config code. So I have SZ2 and SZ3 to encode a couple of useful setups, others can be supported by changing this PAL. Anyway, the supported options: JB1 JB2 J1AB RAM Mode Name VRD SZ0 SZ1 SZ2 SZ3 1ME B0P B1E B1P Bank (size x 32) loc1MD 0 0 1 x x x x x x 1-2 256K DRAM loc2M 0 1 0 x x x x x x 1-2 512K DRAM loc2MV 1 0 1 x x x x x x x 256K VRAM mod4M x 1 1 0 0 0 0 1 x 1-2 1M DRAM mod8M x 1 1 1 0 0 0 0 0 1-2 2M DRAM modmix x 1 1 0 1 1 1 0 0 2-3 256K VRAM & 256K DRAM Any other set of jumpers will lead to an unsupported setup, which may conflict with another module in the system. Note that only one module can be used in mod8M mode, and, when only one module is in "module" mode, it must be the second one. */ CLOE = CFGRD & mod4M # CFGRD & mod8M # CFGRD & modmix; CHOE = CFGRD & mod8M # CFGRD & modmix;