PARTNO 31XXXX ; NAME CLOCKSWITCH ; DATE April 23, 1992 ; REV 1 ; DESIGNER Dave Haynie ; COMPANY Commodore ; ASSEMBLY AAAVideo ; LOCATION ; DEVICE p22v10 ; /************************************************************************/ /* */ /* AAAVideo Clock Switch PAL */ /* */ /* This PAL is designed to switch between four asynchronous clocks */ /* without slivers, in a relatively cheap-ass fashion (eg, we */ /* don't have time to make Jim Redfield's "CMOS PCLK" gate array */ /* and there's no room for a zillion components to do this). */ /* */ /************************************************************************/ /* Allowable Target Device Types: 22V10-10 */ /************************************************************************/ /* Clock: FCLK */ /************************************************************************/ /* Free Pins: NONE */ /************************************************************************/ /* HISTORY */ /* DBH Apr 23: Completely new. */ /************************************************************************/ /** Inputs **/ PIN 1 = FCLKIN ; /* Flip-flop clock */ PIN 2 = FS0 ; /* Frequency selects */ PIN 3 = FS1 ; PIN 4 = FS2 ; PIN 5 = !RST ; /* System reset */ PIN 6 = FREQ0 ; /* The clocks themselves */ PIN 7 = FREQ1 ; PIN 8 = FREQ3 ; PIN 9 = FREQ4 ; /** Outputs **/ PIN 23 = PCLK ; /* Pixel clock */ PIN 22 = SCLK ; /* Raw clock, slivers and all */ PIN 21 = FCLKOUT ; /* Flip-flop clock output */ /** Used Internally **/ PIN 19 = !CHANGE ; /* Ready for a change? */ PIN 18 = !CHANGING ; /* In the changing process? */ PIN 17 = !NEWCLK ; /* Ready for the next clock */ PIN 16 = LS0 ; /* Latched clock selects */ PIN 15 = LS1 ; PIN 14 = LS2 ; /** Declarations and Intermediate Variable Definitions **/ /** Logic Equations **/ /* This is the flip-flop clock output. Normally, we want this to reflect the state of the pixel clock, but we don't always know what the pixel clock is. FCLKOUT = !CHANGING & PCLK # CHANGING & !NEWCLK # NEWCLK & SCLK; /* This is the pixel clock output. The pixel clock will reflect the selected input clock during normal operation. When the clock is changing, the pixel clock will stay high. The change signals take into account the state of the input clock, so we avoid slivers. */ PCLK = FREQ0 & !LS2 & !LS1 & !LS0 # FREQ1 & !LS2 & !LS1 & LS0 # FREQ1 & !LS2 & LS1 & !LS0 # FREQ3 & !LS2 & LS1 & LS0 # FREQ4 & LS2 & !LS1 & !LS0 # CHANGING; /* This is the slivery clock. It's the same as the pixel clock, but it isn't inhibited during clock changeover. This basically keeps things moving while we're selecting the new clock. */ SCLK = FREQ0 & !FS2 & !FS1 & !FS0 # FREQ1 & !FS2 & !FS1 & FS0 # FREQ1 & !FS2 & FS1 & !FS0 # FREQ3 & !FS2 & FS1 & FS0 # FREQ4 & FS2 & !FS1 & !FS0; /* When the input clock address doesn't match the current clock address, it's time for a change. Change must occur when PCLK = FCLK is high, so we have enough time to wrap around and assert the CHANGING output. */ CHANGE = (LS2 $ FS2) & FCLKOUT & !RST # (LS1 $ FS1) & FCLKOUT & !RST # (LS0 $ FS0) & FCLKOUT & !RST # CHANGE & !CHANGING & !RST; /* The new clock can be enabled once we're in changing mode and on the right half of SCLK. */ NEWCLK = CHANGING & SCLK & !RST # CHANGING & NEWCLK & !RST; /* Once a change is called for, we need to set the CHANGING indicator. This goes valid on the rising edge of the FCLK, which at this time is synched to the PCLK. Once CHANGING is indicated, PCLK is forced high. Since CHANGING only takes place on PCLK going high, no slivers happen upon entering the change cycle. CHANGING.D = CHANGE # CHANGING & !NEWCLK; /* These are the latched clock selects. They remain constant until we're in changing mode, at which point the new clock address can come through. */ LS0.D = CHANGING & FS0 # !CHANGING & LS0; LS1.D = CHANGING & FS1 # !CHANGING & LS1; LS2.D = CHANGING & FS2 # !CHANGING & LS0;