PARTNO		31XXXX ;
		NAME            U202 ;
		DATE            April 25, 1991 ;
		REV             1 ;
		DESIGNER        Dave Haynie ;
		COMPANY         Commodore ;
		ASSEMBLY        Gemini ;
		Location        U202 ;

/************************************************************************/
/*									*/
/*	Gemini:	Satellite Mapper, U202 and U402				*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-15 				*/
/************************************************************************/
/*  Clock:		AS						*/
/************************************************************************/
/*  Free Pins:		NONE						*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Apr 25:	Completely new.					*/
/************************************************************************/

/** Inputs **/

PIN 1		= !AS		;	/* Local address strobe */
PIN 2		= !ABOE2	;	/* RAM Hi address */
PIN 3		= !EML		;	/* Expansion accesses local RAM */
PIN 4		=  RW		;	/* Local processor R/W */
PIN 5		= !REGQ		;	/* Register space qualifier */
PIN 6		= !COPQ		;	/* Coprocessor space qualifier */
PIN 7		= !IACK		;	/* Interrupt vector acknowledge */
PIN 8		= !TIMER	;	/* Output from timer circuit */
PIN 9		=  A21		;	/* Local addresses */
PIN 10		=  A20		;
PIN 11		=  A17		;
PIN 13		=  A16		;

/**  Outputs  **/

PIN 16		= !RE		;	/* DRAM read enable */
PIN 17		= !TINT		;	/* Timer interrupt output */
PIN 20		= !IREQ		;	/* Interrupt request */
PIN 21		=  VREG		;	/* Vector register access */
PIN 22		= !AVEC		;	/* 68030 autovector */
PIN 23		= !FPU		;	/* 68030 FPU chip select */

/**  Bidirectionals  **/

PIN 14		=  EAD24	;	/* Expansion address 24 */
PIN 15		=  A24		;	/* Local address 24 */
PIN 18		=  D24		;	/* Local data bit 24 */

/**  Used internally **/

PIN 19		= !TSET		;	/* Bit indicating timer mode */

/**  Declarations and Intermediate Variable Definitions  **/

/* Several access types. */

copcyc		=  COPQ & !REGQ & !EML;
regcyc		= !COPQ &  REGQ & !EML;
flipaddr	=  COPQ &  REGQ & !EML;

/* Types of coprocessor cycles. */

interruptack	= A17 &  A16;		    /* Interrupt acknowledge */
coppercom	= A17 & !A16		    /* Coprocessor */

/* Types of register cycles */

timercyc	= regcyc & !A21 & !A20 & AS;
vectorcyc	= regcyc &  A21 & !A20 & AS;

/**  Logic Equations  **/

/* This is the FPU chip select, which is only a partial decode of the full CPU 
   space address.
   
FPU		= copcyc & coppercom;

/* This is the interrupt autovector line. */

AVEC		= copcyc & interruptack;

/* This does the A24 nonsense.  Basically, during normal operation, these are
   both tristate.  When the satellite accesses expansion bus memory, it swaps
   $01000000 with $00000000.  This condition is indicated by both REGQ and
   COPQ asserted together, normally an impossible condition.  During an EML,
   local A24 is always low. */

A24		= 'b'0;
A24.OE		= EML;

EAD24		=  A24 & !flipaddr
		# !A24 &  flipaddr;
EAD24.OE	= ABOE2 & !EML;

/* The vector register is located at $00a0xxxx, which is in the REGQ space. */

VREG		= vectorcyc & !RW;

/* A write to the vector register also causes an interrupt request to go out.
   This request is cleared by an acknowledge, which takes place as the 
   vector is supplied to the Zorro III bus. */

IREQ		= VREG & !AS
		# IREQ & !IACK;

/* The timer register is located at $0080xxxx, which is in the REGQ space 
   also.  The timer control bit is a read/write bit. */

TSET		=  timercyc & D24 & !RW
		# !timercyc & TSET;

TINT		= TSET & TIMER
		# TINT & !IACK;

D24		=  timercyc & TSET & RW;
D24.OE		=  timercyc & TSET & RW;

/* The DRAM read enable is simply an inverted R/W signal. */

RE		= RW;