PARTNO		31XXXX ;
		NAME            U113 ;
		DATE            April 25, 1991 ;
		REV             1 ;
		DESIGNER        Dave Haynie ;
		COMPANY         Commodore ;
		ASSEMBLY        Gemini ;
		Location        U113 ;

/************************************************************************/
/*									*/
/*	Gemini:	Bus Arbiter						*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-15 				*/
/************************************************************************/
/*  Clock:		7MHz						*/
/************************************************************************/
/*  Free Pins:		NONE						*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Apr 25:	Completely new.					*/
/************************************************************************/

/** Inputs **/

PIN 1		=  C7M		;	/* 7MHz bus clock */
PIN 2		= !BG		;	/* Grant from Zorro III bus */
PIN 3		= !RST		;	/* System I/O reset */
PIN 4		= !ASx		;	/* AS from CPU X */
PIN 5		= !BGx		;	/* BG from CPU X */
PIN 6		= !EXTx		;	/* CPU X wants expansion bus */
PIN 7		= !WANTx	;	/* Expansion bus want X bus */
PIN 8		= !ASy		;	/* AS from CPU Y */
PIN 9		= !BGy		;	/* BG from CPU Y */
PIN 10		= !EXTy		;	/* CPU Y wants expansion bus */
PIN 11		= !WANTy	;	/* Expansion bus wants Y bus */
PIN 13		= !LOCK		;	/* Zorro III bus lock */

/**  Outputs  **/

PIN 15		= !RETRYy	;	/* Retry Y bus */
PIN 16		= !BRy		;	/* BR to CPU Y */
PIN 17		= !EMLy		;	/* Expansion masters Y bus */
PIN 18		= !LMEy		;	/* Y bus masters expansion bus */
PIN 19		= !RETRYx	;	/* Retry X bus */
PIN 20		= !BRx		;	/* BR to CPU X */
PIN 21		= !EMLx		;	/* Expansion masters X bus */
PIN 22		= !LMEx		;	/* X bus masters expansion bus */
PIN 23		= !BR		;	/* Expansion bus request */

/**  Used internally **/

PIN 14		= !MREG		;	/* Satellite is a registered master */

/**  Declarations and Intermediate Variable Definitions  **/

/**  Logic Equations  **/

/* In this system, the expansion bus is given priority over the satellites
   for cross access.  So when the expansion bus wants either satellite bus,
   we try to get it right away.  We request the bus based on want, and hold
   it as long as there is a want for it, or if it's locked.  EML here is
   essentially the same thing as BGACK. */

BRx		= !RST & WANTx & !EMLx;

EMLx 		= !RST & BRx & WANTx & BGx
		# !RST & EMLx & WANTx
		# !RST & EMLx & LOCK;

BRy		= !RST & WANTy & !EMLy;

EMLy		= !RST & BRy & WANTy & BGy
		# !RST & EMLy & WANTy
		# !RST & EMLy & LOCK;

/* Getting back to that priority bit, there's alway a chance that one of the
   satellites decides to access the expansion bus at the same time the 
   expansion bus wants the satellite.  This unfortunate situation is called a
   deadlock, and would result in a lock up if nothing were done about it.
   To break the deadlock, a relinquish and retry cycle is run on the 
   satellite to which the expansion bus desires access. */

RETRYx		= !RST & WANTx & BRx & EXTx;

RETRYy		= !RST & WANTy & BRy & EXTy;

/* If the expansion bus isn't occupied with cycles trying to get at the 
   satellite memory, the individual satellites can attempt to get at the
   expansion bus.  First thing to do in such a case is register  with the
   bus controller. */

BR.D		= !RST & !BR & !MREG & EXTx
		# !RST & !BR & !MREG & EXTy
		# !RST & !BR &  MREG & !EXTx & !EXTy & !LOCK;

		
MREG.D		= !RST & BR
		# !RST & MREG & LOCK
		# !RST & MREG & EXTx
		# !RST & MREG & EXTy;

/* Finally, it comes to gating satellite stuff onto the expansion bus.  The
   satellites can only start a cycle if they are registered and they receive
   a grant.  */

LMEx		= !RST & MREG & EXTx & !LMEy & BG
		# !RST & MREG & EXTx & LMEx;

LMEy		= !RST & MREG & EXTy & !EXTx & !LMEx & BG
		# !RST & MREG & EXTy & LMEy;