PARTNO		31XXXX ;
		NAME            U112 ;
		DATE            April 24, 1991 ;
		REV             1 ;
		DESIGNER        Dave Haynie ;
		COMPANY         Commodore ;
		ASSEMBLY        Gemini ;
		Location        U112 ;

/************************************************************************/
/*									*/
/*	Gemini:	Host Address Mapper					*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-15 				*/
/************************************************************************/
/*  Clock:		C7M						*/
/************************************************************************/
/*  Free Pins:		I(5)						*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Apr 24:	Completely new.					*/
/************************************************************************/

/** Inputs **/

PIN 1		=  C7M		;	/* 7MHz clock *
PIN 2		=  A24		;	/* Bus addresses */
PIN 3		=  A23		;
PIN 4		=  A22		;
PIN 6		= !CFGOUT	;	/* The board is configured */
PIN 7		= !ERST		;	/* Expansion bus I/O reset line */
PIN 8		=  FCS		;	/* Zorro III bus cycle strobe *.
PIN 9		= !SLAVE	;	/* Board select */
PIN 10		=  DOE		;	/* Data time strobe */
PIN 11		= !RETRYy	;	/* Retry processor Y */
PIN 13		= !RETRYx	;	/* Retry processor X */

/**  Outputs  **/

PIN 14		= !CINH		;	/* Bus cache inhibit */
PIN 15		= !RST		;	/* Buffered I/O reset */
PIN 16		= !SCRy		;	/* Satellite Control Register Y */
PIN 17		= !WANTy	;	/* Bus wants processor Y's memory */
PIN 18		= !HALTy	;	/* Processor Y halt  */
PIN 19		= !BERRy	;	/* Processor Y bus error */
PIN 20		= !SCRx		;	/* Satellite Control Register X */
PIN 21		= !WANTx	;	/* Bus wants processor X's memory */
PIN 22		= !HALTx	;	/* Processor X halt  */
PIN 23		= !BERRx	;	/* Processor X bus error */

/**  Declarations and Intermediate Variable Definitions  **/

/* The basic memory mapping, we put X down, Y up. */

xsel		= FCS & !ERST & SLAVE & CFGOUT & !A24;

ysel		= FCS & !ERST & SLAVE & CFGOUT &  A24;

/* Get the easy shit out of the way. */

RST 		= ERST;

/* At present, we always want to inhibit caching. */

CINH		= FCS & SLAVE;

/* X-Space and Y-Space are identical, execpt for the qualifier.  So we do
   e'm both together.  First up, the Satellite Control Register. */

SCRx		= xsel & A23 & !A22;

SCRy		= ysel & A23 & !A22;

/* Now, the WANT signal, this indicates to the satellite that the bus wants
   access to its memory. */

WANTx		= xsel & !A23 & !A22;

WANTx		= xsel & !A23 & !A22;

/* Finally, the HALT and BERR signals.  These get asserted in response to a
   corresponding retry signal. */

BERRx.D		= RETRYx & !HALTx;

HALTx.D		= RETRYx;

BERRy.D		= RETRYy & !HALTy;

HALTy.D		= RETRYy;