PARTNO		31XXXX ;
		NAME            U110 ;
		DATE            April 24, 1991 ;
		REV             1 ;
		DESIGNER        Dave Haynie ;
		COMPANY         Commodore ;
		ASSEMBLY        Gemini ;
		Location        U110 ;

/************************************************************************/
/*									*/
/*	Gemini:	Satellite Control Register, U110 and U111		*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-15 				*/
/************************************************************************/
/*  Clock:		NONE						*/
/************************************************************************/
/*  Free Pins:		NONE						*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Apr 24:	Completely new.					*/
/************************************************************************/

/** Inputs **/

PIN 1		=  bINTSR	;	/* Interrupt set/clear, bit 20 */
PIN 2		=  bRST		;	/* Reset */
PIN 3		=  FCS		;	/* Full cycle strobe */
PIN 4		=  READ		;	/* Bus read strobe */
PIN 5		= !SCR		;	/* Register select */
PIN 6		= !DS3		;	/* Strobe for D31..D24 */
PIN 7		= !DS1		;	/* Strobe for D15..D8  */
PIN 8		= !DS2		;	/* Strobe for D23..D16 */
PIN 9		= !IACK		;	/* Interrupt acknowledge */
PIN 10		= !EXT		;	/* External access request */
PIN 11		= !RST		;	/* I/O Reset */
PIN 13		= !TIME		;	/* Timer interrupt output */

/**  Outputs  **/

PIN 14		= !IPL2		;	/* Interrupt lines */
PIN 15		= !IPL1		;
PIN 16		= !IPL0		;
PIN 17		= !CIIN		;	/* Processor cache inhibit */
PIN 18		= !CPURST	;	/* Processor reset */
PIN 19		=  bSERV	;	/* Interrupt service, bit 24. */

/**  Bidirectionals  **/

PIN 20		=  bINT2	;	/* Interrupt request 2, bit 16 */
PIN 21		=  bINT6	;	/* Interrupt request 6, bit 17 */
PIN 22		=  sINT2	;	/* Interrupt request storage */
PIN 23		=  sINT6

/**  Declarations and Intermediate Variable Definitions  **/

/* Enables for the different bits. */

servenb		= !RST & SCR & DS3;
intenb		= !RST & SCR & DS2;
rstenb		= !RST & SCR & DS1;

/**  Logic Equations  **/

/* This PAL implements a Satellite Control Register.  This register is
   activated by the SCR input.  It is a 32 bit wide register, which looks
   like this:
       31            24      20   17 16              8 7             0
      +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
      |/////////////| |/////| |///| | |/////////////| |///////////////|
      +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
                     /       \     \ \               \
         Interrupt -+         \     \ +- Int2         +- Satellite
          Serviced             \     +-- Int6            Reset
                                +------- Set/Clear       Control */

/* The interrupt service bit is cleared on reset, and cleared whenever it
   is read.  It ignores writes, and gets set whenever IACK is asserted. */

bSERV		=  IACK & !RST
		# bSERV & !servenb & !RST
		# bSERV &  servenb & !READ
		# bSERV &  servenb &  FCS;

bSERV.OE	= servenb & READ;

/* When we read the interrupt register control, sINTs go to bINTs.  */

bINT2		= intenb & READ & sINT2;
bINT2.OE	= intenb & READ;

bINT6		= intenb & READ & sINT6;
bINT6.OE	= intenb & READ;


/* When we write the interrupt register control, some bINTs may get
   transferred to sINTs, based on the value of INTSR. */

sINT2		=  intenb & !READ &  bINTSR &  bINT2
		#  intenb & !READ & !bINTSR & !bINT2 & sINT2
		# !intenb & !RST & sINT2;

sINT6		=  intenb & !READ &  bINTSR &  bINT6
		#  intenb & !READ & !bINTSR & !bINT6 & sINT6
		# !intenb & !RST & sINT6;

/* The interrupt request lines drive the actual interrupt input codes. 
   These inputs are cleared on reset, otherwise they are set when the request
   lines are written.  The TIME interrupt will override a lower priority
   CPU-generated interrupt, going in at level 5. */

IPL0		= 'b'0;

IPL1		= !RST & sINT6
		# !RST & !TIME & sINT2;

IPL2		= !RST & sINT6
		# !RST &  TIME & !sINT6;

/* This is the satellite reset bit.  This comes up in the reset state, and
   may be written high or low at any time. */

CPURST		=    RST
		#   bRST &  rstenb
		# CPURST & !rstenb;