PARTNO		31XXXX ;
		NAME            U109 ;
		DATE            April 24, 1991 ;
		REV             1 ;
		DESIGNER        Dave Haynie ;
		COMPANY         Commodore ;
		ASSEMBLY        Gemini ;
		Location        U109 ;

/************************************************************************/
/*									*/
/*	Gemini:	Vector Manager & Slave Generator			*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-15 				*/
/************************************************************************/
/*  Clock:		NONE						*/
/************************************************************************/
/*  Free Pins:		NONE						*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Apr 24:	Completely new.					*/
/************************************************************************/

/** Inputs **/

PIN 1		= !MEMQUAL	;	/* Memory cycle qualifier */
PIN 2		=  A23		;	/* Bus addresses */
PIN 3		=  A19		;
PIN 4		=  A18		;
PIN 5		=  A17		;
PIN 6		=  A16		;
PIN 7		= !IVQUAL	;	/* Interrupt cycle qualifier */
PIN 8		= !MTCR		;	/* Multiple transfer cycle strobe */
PIN 9		= !CFGIN	;	/* Configuration chain in */
PIN 10		= !IREQx	;	/* Interrupt request X */
PIN 11		= !IREQy	;	/* Interrupt request Y */
PIN 13		= !FCS		; 	/* FCS, from bus */
PIN 14		=  DOE		;	/* Data time enable, from bus */
PIN 15		= !RST		;	/* System I/O reset */
PIN 23		= !MATCH	;	/* Match from comparator */

/**  Outputs  **/

PIN 16		= !INT		;	/* Actual interrupt to bus. */
PIN 17		= !DTACK	;	/* Data transfer acknowledge to bus. */
PIN 18		=  oFCS		;	/* Buffered FCS */
PIN 19		= !IACKy	;	/* Interrupt acknowledge Y */
PIN 20		= !IACKx	; 	/* Interrupt acknowledge X */
PIN 21		= !VECTOR	;	/* Vector cycle phase */

/**  Bidirectionals  **/

PIN 22		= !SLAVE	;	/* Slave I/O */

/**  Declarations and Intermediate Variable Definitions  **/

/* The basic cycle qualifier, merely assuring that we're not in reset, a
   cycle is occuring, and the pervious board is configured. */

cycle		= !RST & CFGIN & FCS;

/* Interrupt cycles are qualified by the interrupt (CPU Space) function code
   qualifier IVQUAL, and the CPU space type equal to $F. */

intcyc		= cycle & IVQUAL & A19 & A18 & A17 & A16;

/* The interrupt acknowledge is to this PIC iff we have an interrupt cycle,
   SLAVE back from the controller, the vector phase qualifier, and MTCR. */

intack		= intcyc & SLAVE & VECTOR & MTCR;

/* A memory cycle is given by the memory function code qualifier and an
   address comparator match. */

memcyc		= cycle & MEMQUAL & MATCH;

/**  Logic Equations  **/

/* Get the easy shit out of the way. */

oFCS 		= FCS;

/* The interrupt request/acknowledge stuff.  Each CPU can request a bus
   interrupt from the expansion bus, buy asserting its IREQ input.  This
   causes the INT line to be generated. */

INT		= IREQx # IREQy;

/* Things romp along happily until we see an interrupt acknowledge cycle
   happening.  This cycle is qualified by the IVQUAL input, FCS, and of
   course only happens during the poll phase of the cycle.  In the poll
   phase, we're generating a SLAVE if we want the vector.  Note that SLAVE
   also happens for a normal memory cycle. */

SLAVE		= intcyc & !VECTOR &  MTCR & IREQx
		# intcyc & !VECTOR &  MTCR & IREQy
		# memcyc;
SLAVE.OE	= !VECTOR;

/* The VECTOR signal indicates that the vector phase of an interrupt 
   acknowledge cycle is taking place.  At this point, the input of a SLAVE
   from the bus controller indicates that this device gets to respond to
   the interrupt vector. */

VECTOR		= intcyc & SLAVE & !MTCR
		# intcyc & VECTOR;

/* The interrupt acknowledges are returned during a vector cycle poll phase
   that we here win.  The X processor has a simple priority over the Y 
   processor. */

IACKx		= intack & iREQx;

IACKy		= intack & !iREQx & iREQy;

/* Warning: heavy juju ahead!
   OK, here's the thing.  We want an instant DTACK for any configuration
   register access.  Same for a vector phase reply, or control register
   access for either processor unit.  We don't want any DTACK at all for
   access to satellite memory, since BUSTER will relay RAMSEY's STERM back
   as a DTACK for all to see.  Configuration takes place at $ffff0000.
   Control registers are at offset $0800000 and $1800000 from the 
   configuration base.  An interrupt cycle sets all address lines high
   except for the vector number.  So, basically, when A23 is high, SLAVE
   is asserted, and DOE is asserted, make DTACK.  Otherwise, tristate it.
*/
   
DTACK		= SLAVE & A23 & DOE;
DTACK.OE	= SLAVE & A23 & DOE;