PARTNO		31XXXX ;
		NAME            U107 ;
		DATE            April 24, 1991 ;
		REV             1 ;
		DESIGNER        Dave Haynie ;
		COMPANY         Commodore ;
		ASSEMBLY        Gemini ;
		Location        U107 ;

/************************************************************************/
/*									*/
/*	Gemini:	Configuration						*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-15 				*/
/************************************************************************/
/*  Clock:		NONE						*/
/************************************************************************/
/*  Free Pins:		NONE						*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Apr 24:	Completely new.					*/
/************************************************************************/

/** Inputs **/

PIN [1..3]	=  [FC2..0]	;	/* Bus function codes */
PIN [4..8]	=  [A6..2]	;	/* Bus addresses */
PIN 9		= !DS3		;	/* High order data strobe */
PIN 10		=  A1		;	/* Logical A1 (actually A8) */
PIN 11		= !SLAVE	;	/* Board select */
PIN 13		=  READ		; 	/* Bus read strobe */
PIN 14		= !RST		;	/* I/O Reset */
PIN 15		= !BERR		;	/* Bus error signal */

/**  Outputs  **/

PIN 16		= !MEMQUAL	;	/* Memory space qualifier */
PIN 17		= !IVQUAL	; 	/* Interrupt vector qualifier */
PIN 18		=  CFGLT	;	/* Configuration latch */
PIN 19		= !CFGOUT	;	/* Configuration chain out */

/**  Bidirectionals  **/

PIN [20..23]	=  [D28..31]	;	/* Data outputs */

/**  Declarations and Intermediate Variable Definitions  **/

field addr 	= [A6..1];

memspace	= FC1 $ FC0;

cpuspace	= FC2 & FC1 & FC0;

/**  Logic Equations  **/

/* The memory qualifier is simply an XOR of two function codes, which gives
   us valid data or instruction space. */

MEMQUAL		= memspace & !RST;

/* This qualifies an interrupt vector cycle.  The vector cycle is based
   on the function codes and the appropriate vector address.  Since the
   current Buster messes up the low order address, we ignore it, and 
   go for vector level 6, since level 7 will never happen.  However, it
   would be proper to have A1 here as well to fully qualify the vector
   6 cycle. */

IVQUAL		= cpuspace & A3 & A2 & READ & !RST;

/* The configuration latch is based on a write to the configuration register,
   logically located at offset 44 of the configuration unit. */

CFGLT		= memspace & addr:44 & !READ & DS3 & !RST;

/* The configuration output is simply the configuration latch, once the 
   cycle is over with.  It stays around until reset. */

CFGOUT		=  CFGLT & !RST & !SLAVE
		# CFGOUT & !RST;

/* Here we have the configuration ROM for the board.  All Gemini boards
   are Commodore boards, with the product code $54.  The LSB of the serial
   number reads $03, indicating that this board has two standard Gemini
   68030 units on it, upper and lower.  The logical register table:

	REG	76543210	
	00	10000001	Zorro III, no link, 32 megabytes
	04	01011000	Product $54
	08	01110000	I/O card, no shut up, physical sized
	10	00000010	Commodore product
	14	00000010	
	18-20	00000000	High serial number bytes
	24	00000011	Lowest serial number, indicating features
	28-3c	00000000	The rest default to 0

  The actual contents of the ROMs invert every register except the first.
  This yields the bit patterns:

	ADDR	D31 D30 D29 D28
	 00	 1   0   0   0
	 02	 0   0   0   1
	 04	 1   0   1   0
	 06	 0   1   1   1
	 10	 1   1   1   1
	 12	 1   1   0   1
	 14	 1   1   1   1
	 16	 1   1   0   1
	 24	 1   1   1   1
	 26	 1   1   0   0
	 OTHERS	 1   1   1   1

   As usual, the zero terms are explicitly driven low in the PAL
   equation, all else goes high. */

!D31		= addr:02
		# addr:06;

!D30		= addr:00
		# addr:02
		# addr:04;

!D29		= addr:00
		# addr:02
		# addr:12
		# addr:16
		# addr:26;

!D28		= addr:00
		# addr:04
		# addr:26;