PARTNO		31XXXX ;
		NAME		U203 ;
		DATE            April 20, 1992 ;
		REV             6 ;
		DESIGNER        Dave Haynie;
		COMPANY         Commodore ;
		ASSEMBLY        AA3000 ;
		LOCATION        U203 ;
		DEVICE		p18p8 ;

/************************************************************************/
/*									*/
/*  AA3000	32 bit chip RAM Control logic				*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 16V8-10 				*/
/************************************************************************/
/*  Clock:		NONE						*/
/************************************************************************/
/*  Free Pins:		NONE						*/
/************************************************************************/
/*  HISTORY								*/
/*	GCB Dec 27:	Completely new.					*/
/*	DBH Jan 31:	Whoops, didn't run C1 here.  Jumper #1.		*/
/*	DBH Nov 20:	First Rev2 PCB revison. 			*/
/*	DBH Dec  4:	Fixes for 16-bit double-CAS mode.		*/
/*	DBH Jan 27:	Fix for bank bashing with A0.			*/
/*	DBH Apr 20:	Kludge for blitter busy bug in Alice.		*/
/*	DBH Apr 20:	Try again, take into accout more cycle states.	*/
/************************************************************************/

/**  Inputs  **/

PIN 1		= !INT3		;	/* Blitter busy interrupt */
PIN 2	 	=  C1		;	/* Video clock */
PIN 3		=  MA0		;	/* DRAM address line 0 */
PIN 4	  	= !CAS		;	/* CAS out of ALICE */
PIN 5		= !RAS		;	/* RAS out of ALICE */
PIN 6	 	= !PBLIT	;	/* Unlatched BLIT */
PIN 7	 	= !WE		;	/* Write enable */
PIN 8	 	=  C3		;	/* Video clocks */
PIN 9		= !CDAC		;
PIN 11		=  MA10I	;	/* DRAM Adress 10 from Alice */
PIN 12		=  BLISS	;	/* Blitter slowdown from Gary */
PIN 18	 	= !CBLIT	;	/* Latched Blitter Busy */

/**  Outputs  **/

PIN 13		=  MA10O	;	/* Mux'ed Adr bit 10 output */
PIN 14	 	= !BRIDGE	;	/* Bridge D0-D15 to D16-D31 during CHIP access */
PIN 15	 	=  BRIDGEDIR	;	/* Direction to bridge data buses */
PIN 17 		=  PLAU		;	/* Bank select address bit */
PIN 19		=  KBLISS	;	/* Kludged BLISS to Alice */

/**  Used Internally  **/

PIN 16		= !BLOCK	;	/* Bliss lock */

/**  Declarations and Intermediate Variable Definitions  **/

/* Which half of the bus? */

A1 		= MA0;

/**  Logic Equations  **/

/*	The current DRAM multiplexing scheme:

	MA10 MA9  MA8  MA7  MA6  MA5  MA4  MA3  MA2  MA1  MA0
	-----------------------------------------------------
ROW:	A22  A19  A18  A17  A16  A15  A14  A13  A12  A11  A20
COL:	A21  A10  A9   A8   A7   A6   A5   A4   A3   A2   A1

*/

/* We're messing a bit with the multiplexed addresses. This seems to be a
   rather useless hangover from the A3000; we don't really have 8MB of RAM,
   which is the only reason to mess with A10.  In a real 8MB system, we 
   would grab A20 and send it out at RAS time, taking A22 for the CAS bank
   switcher.  This would let the banks of 1Mx4 DRAM work contiguously.  In
   a 2MB system, this is useless. */

!MA10O	= !MA0 & !CDAC & C1 & !CAS /* Route MA0 (A20) to it at RAS time */
	# !MA10I & CDAC & C3	   /* Route it straight thru at CAS time ... */
	# !MA10I & C1		   /* ... hold it ... */
	# !MA10I & CAS;		   /* ... hold it 'til CAS goes away. */

/* The bridge logic.  We need bridging during chip write cycles (duplicate the 
   data, let the CAS strobes worry about clocking it in), or for Chip reads if
   A1 is true, indicating a read from the odd side of the bus.  Processor access
   never uses the bridge.  */


/* We logically want something like CBLIT here, but unfortunately, the CBLIT
   we make only works for DRAM cycles.  So we gotta base things on PBLIT here.
   When a double-CAS cycle runs, though, the second CAS is the one that
   needs the bridge.  So we need a CBLIT-based equation that detects the
   second CAS correctly.  To avoid MA0 causing a false BRIDGE, we have to
   wait for the first CAS before driving BRIDGE on read cycles. */

BRIDGE	= PBLIT &  C3 &  CDAC & WE	  /* ALWAYS Bridge on a Chip write... */
	# PBLIT &  C3 &  CDAC & A1 & CAS  /* ... or if A1 is high on first    */
	# CBLIT & !C3 & !CDAC & A1	  /* ... or second CAS. */
	# BRIDGE & (CAS # RAS);		  /* Hold it on ... */

!BRIDGEDIR	= !WE
		# !BRIDGEDIR & CAS;

/* Select the CAS bank based on A20. */

PLAU		= MA0;

/* Here's the blitter busy kludge.  The problem is that the blitter is telling
   us its done before it really is, thereby letting the CPU get in on top of
   registers it isn't done with yet.  The attempted fix here is to look for 
   this signal in hardware, which is the only thing out on INT3.  When INT3 is
   asserted, the Kludged BLISS signal into Alice is kept high, which will keep
   the CPU out and give the blitter all the time it can have.  Once the blitter
   is done, the CPU will again get cycles, and we can unlatch KBLISS and let 
   normal BLISS through.  BLOCK is the BLISS latch indicator. */

KBLISS		= BLOCK
		# !BLOCK & BLISS &   C1 & !C3
		# !BLOCK & KBLISS & !C1
		# !BLOCK & KBLISS &  C3;

/* We only want BLOCK to change when things are valid.  INT3 changes during 
   C1, so we sample at C3 high, C1 low (right after it becomes valid).  The
   BLIT signal is valid when C1 is high, C3 low, so I check it there.  At all
   other times, I want to maintain the state of BLOCK. */

BLOCK		=  INT3 & !C1 &  C3
		# BLOCK &  C1 & !C3 & PBLIT
		# BLOCK & !C1
		# BLOCK &  C3;