PARTNO		XXXXX ;
		NAME		U701 ;
		DATE		May 28, 1992 ;
		REV		7 ;
		DESIGNER	Dave Haynie ;
		COMPANY		Commodore ;
		ASSEMBLY	AA3000 ;
		LOCATION	U701 ;
		DEVICE		p16l8 ; 

/************************************************************************/
/*									*/
/*  AA3000	DSP Clock/Interrupt Manager				*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 16L8-7	 			*/
/************************************************************************/
/*  Free Pins:		NONE						*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Nov 20:	New for AA3000 Rev2				*/
/*	DBH Feb  6:	Added interrupt enable line from DSPCON		*/
/*	DBH Feb 10:	New clocking scheme.				*/
/*	DBH May 27:	Arbitration stuff added.			*/
/*	DBH May 28:	New 50MHz clock generation stuff.		*/
/************************************************************************/

/**  Inputs  **/

PIN 1		=  CPUCLK	;	/* 25MHz processor clock */
PIN 2		=  CLK90	;	/* 25MHz 90-degree offset clock */
PIN 3		= !dspMI2	;	/* DSP interrupt enable 2 */
PIN 4		= !dspMI6	;	/* DSP interrupt enable 6 */
PIN 5		=  CLK5		;	/* CPUCLK + 5ns (CA0) */
PIN 6		=  CLK25	;	/* CPUCLK + 25ns (CA1) */
PIN 7		= !BRin		;	/* System bus request in */
PIN 8		= !dspBR	;	/* Bus request from DSP */
PIN 9		= !dspCI2	;	/* Low priority DSP-to-CPU interrupt */
PIN 11		= !dspCI6	;	/* High priority DSP-to-CPU interrupt */
PIN 13		= !BG		;	/* System bus grant */

/**  Outputs  **/

PIN 19		= !INT6		;	/* Level 6 CPU interrupt */
PIN 18		=  PdspCLK	;	/* Main DSP clock */
PIN 17		= !NdspCLK	;	/* Inverted DSP clock */
PIN 16		= !BRout	;	/* Bus request output */
PIN 15		= !dspGO	;	/* DSP wins the arbitration. */
PIN 12		= !INT2		;	/* Level 2 CPU interrupt */

/* Used internally */

PIN 14		= !ARB		;	/* Lock on the idea that we won */

/** Declarations and Intermediate Variable Definitions **/

/**  Logic Equations  **/

 /* The DSP clock is an XOR of the bus clocks, for an effective 50MHz.  The
   skews on this may eventually lead us to a 5ns PAL. */

PdspCLK		= CLK5 $ CLK25;

!NdspCLK	= CLK5 $ CLK25;

/* The interrupts are really straight forward.  The outputs work like open
   collector/open drain drives based on the corresponding inputs. */

INT6		= dspCI6;
INT6.OE		= dspCI6 & dspMI6;

INT2		= dspCI2;
INT2.OE		= dspCI2 & dspMI2;

/* This system uses the Fast Arbiter function of Buster.  Buster always 
   samples and drives BR on the rising edge of CPUCLK, so we need to look
   at BR in a window that's near the falling edge of CPUCLK to decide if
   we can drive BR. */

ARB		= !CPUCLK & CLK5 & !BRin & dspBR
		#  ARB & dspBR;

BRout		= ARB;
BRout.OE	= ARB;

/* Once the request goes out from here rather than Buster, the grant coming
   back from the '030 is ours.  Relay this information on the other DSP 
   logic. */

dspGO		= ARB & BG;