PARTNO		31XXXX ;
		NAME            U124 ;
		DATE            March 13, 1992 ;
		REV             3 ;
		DESIGNER        Dave Haynie ;
		COMPANY         Commodore ;
		ASSEMBLY        AA3000 ;
		LOCATION        U124 ;
		DEVICE		p22v10 ;

/************************************************************************/
/*									*/
/*  AA3000	DSP3210 DMAC Kludge Logic				*/
/*									*/
/*	This replaces the write half of the DMAC's DSP control logic.	*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-10 				*/
/************************************************************************/
/*  Clock:		CPUCLK						*/
/************************************************************************/
/*  Free Pins:		20(IO),21(IO)					*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Mar 09:	Completely new.					*/
/*	DBH Mar 13:	Fixed problems.					*/
/************************************************************************/

/** Inputs **/

PIN 1		=  CPUCLK	;	/* Main 68030 bus clock */
PIN 2		=  A7		;	/* Address line */
PIN 3		= !DS		;	/* 68030 data strobe */
PIN 4		=  IACK0	;	/* DSP interrupt level 0 acknowledge. */
PIN 5		=  IACK1	;	/* DSP interrupt level 1 acknowledge. */
PIN 6		= !SCSIIN	;	/* SCSI chip select input. */
PIN 7		= !RST		;	/* System reset */
PIN 8		= !D0		;	/* Data lines */
PIN 9		= !D1		;
PIN 10		= !D4		;
PIN 11		= !D5		;
PIN 13		= !D7		;
PIN 23		=  RW		;

/**  Outputs  **/

PIN 14		= !dspRST	;	/* DSP reset */
PIN 15		= !dspMI6	;	/* Inhibit level 6 interrupt from DSP */
PIN 16		= !dspMI2	;	/* Inhibit level 2 interrupt from DSP */
PIN 17		= !dspINT1	;	/* Cause DSP interrupt level 1 */
PIN 18		= !dspINT0	;	/* Cause DSP interrupt level 0 */
PIN 19		= !SCSIOUT	;	/* SCSI select out to DMAC */
PIN 22		= !DSACK0	;	/* 030 Asynchronous termination */

/**  Bidirectionals  **/

/**  Declarations and Intermediate Variable Definitions  **/

localcyc	= SCSIIN &  A7 & !RW & !RST;

dmaccyc		= SCSIIN & !A7 & !RST;

/* Qualified basic DSP address strobe. */

/* The dsp Reset line tracks reset and data bit seven. */

dspRST		=  localcyc & DS & D7
		#  localcyc &  dspRST & DSACK0 
		# !localcyc &  dspRST
		#  RST;

/* The interrupt inhibit lines work with bits four and five.  They come up
   active after reset, and are considered active low from the register
   view. */

dspMI2		=  localcyc & !RST & DS & D4
		#  localcyc & !RST & dspMI2 & DSACK0
		# !localcyc & !RST & dspMI2;

dspMI6		=  localcyc & !RST & DS & D5
		# !localcyc & !RST & dspMI6 & DSACK0
		# !localcyc & !RST & dspMI6;

/* The DSP interrupt control lines work with bits zero and one.  They come up
   disabled after reset, and are considered active low from the register 
   view. */

dspINT0		= !IACK0 & !RST & localcyc & DS & D0
		# !IACK0 & !RST & localcyc & dspINT0 & DSACK0
		# !IACK0 & !RST & !localcyc & dspINT0;

dspINT1		= !IACK1 & !RST & localcyc & DS & D1
		# !IACK1 & !RST & localcyc & dspINT0 & DSACK0
		# !IACK1 & !RST & !localcyc & dspINT1;

/* When its a DMAC select cycle, pass on the SCSI select. */

SCSIOUT		= dmaccyc;

/* The termination signal is simple -- if the cycle is for this pal, terminate 
   as soon as possible. */

DSACK0.D	= localcyc & DS;
DSACK0.OE	= localcyc & DS;