PARTNO		31XXXX ;
		NAME            U123 ;
		DATE            May 15, 1992 ;
		REV             7 ;
		DESIGNER        Dave Haynie ;
		COMPANY         Commodore ;
		ASSEMBLY        AA3000 ;
		LOCATION        U123 ;
		DEVICE		p22v10 ;

/************************************************************************/
/*									*/
/*  AA3000	DSP3210 Bus Arbiter 					*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22v10-10 				*/
/************************************************************************/
/*  Clock:		dspCLK (50MHz)					*/
/************************************************************************/
/*  Free Pins:		NONE						*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Jan 31:	Completely new.					*/
/*	DBH Nov 20:	Revised for Rev2 PCB.				*/
/*	DBH Feb  4:	Arbiter if FUBAR, new arbiter design put in.	*/
/*	DBH Feb  6:	Improved handling of consecutive cycles.	*/
/*	DBH Feb  6:	Changed BURST/CBREQ and added CPUCLK.		*/
/*	DBH Feb 10:	Improved SNOOP function, AS* input added. 	*/
/*	DBH May 15:	Arbiter seems to jam, try simpler design.	*/
/*	DBH May 15:	Added reset logic.				*/
/************************************************************************/

/** Inputs **/

PIN 1		=  dspCLK	;	/* Main DSP clock. */
PIN 2		= !dspENABLE	;	/* Enables DSP. */
PIN 3		= !dspBR	;	/* DSP bus request. */
PIN 4		= !SBR		;	/* SCSI bus request. */
PIN 5		= !XBG		;	/* Arbitrated bus grant. */
PIN 6		= !dspBGACK	;	/* DSP bus grant acknowledge. */
PIN 7		= !preBERR	;	/* Unsynced Bus Error. */
PIN 8		= !CBREQ	;	/* Burst cycle, could be for DSP. */
PIN 9		= !AS		;	/* 030 Address strobe. */
PIN 10		=  CPUCLK	;	/* 030 processor clock. */
PIN 11		=  A3		;	/* 030 Addresses */
PIN 13		=  A2		;
PIN 16		= !RST		;	/* System I/O Reset */

/**  Outputs  **/

PIN 18		= !dspBERR	;	/* DSP bus error */
PIN 20		= !SBG		;	/* SCSI bus grant */
PIN 21		= !SBSYNC	;	/* SCSI bus request synch-up */
PIN 22		= !dspBG	;	/* DSP bus grant */
PIN 23		= !XBR		;	/* 030 bus request */

/**  Bidirectionals  **/

PIN 14		= !dspWIN	;	/* DSP wins the bus arbitration */
PIN 15		= !SNOOP	;	/* Arbitration/burst snooper */
PIN 17		= !dspCYC	;	/* DSP is in charge */
PIN 19		= !BGACK	;	/* 68030 system bus grant acknowledge */

/**  Declarations and Intermediate Variable Definitions  **/

/**  Logic Equations  **/

/* As an output, the SNOOP line is asserted when A3-A2=11.  As an input,
   it's used by the BGACK logic. */

SNOOP		= dspBGACK & A3 & A2;
SNOOP.OE	= AS & dspBGACK;

/* The DSP bus error line is just system BERR, when the DSP is bus
   master, synched up to the clock. */

dspBERR.D	= preBERR & dspBGACK;
dspBERR.AR	= RST;

/* The SCSI bus request signal can come in asynchronously.  It needs to be
   synched up.  Extra stuff holds off SBSYNC if any DSP activity is present,
   which is kind of extra insurance. */

SBSYNC.D	= SBR & !dspBR & !dspBGACK & !dspCYC
		# SBR & SBSYNC;
SBSYNC.AR	= RST;

/* The system bus request goes out whenever DSP or SCSI want the bus.  
   There's no need to re-request the bus if we already have it (eg, dspCYC 
   is asserted). */

XBR		= dspBR & !dspBGACK & !dspCYC
		# SBR & SBSYNC;

/* This is the basic bus arbiter.  SCSI and DSP share the same DMA channel
   in the Buster Chip.  This logic must select one of the two to receive a
   grant; dspWIN is basically a 68000-equivalent grant for the DSP subsystem.
   As long as the SCSI device hasn't already been granted the bus, the DSP
   will get it when a grant is returned.  This grant signal is held until
   the DSP actually takes the bus, as indicted by dspCYC. */

dspWIN.D	=    XBG & dspBR & !SBG 
		# dspWIN & !dspCYC;
dspWIN.AR	= RST;

/* The SCSI grant is asserted when a grant is received and the DSP doesn't
   already have that grant.  For extra paranoia, we don't give SCSI the
   grant if any DSP activity is present.  This isn't likely necessary, but
   it should eliminate all the arbitration uncertainties we have now. */

SBG.D		= XBG & SBSYNC & !dspWIN & !dspBR & !dspBGACK & !dspCYC
		# XBG & SBG;
SBG.AR		= RST;

/* The DSP cycle can only begin when we have a dspWIN, no other BGACK on the
   bus, and no SNOOP activity.   Once the DSP has the bus, it keeps the bus
   as long as its asserting dspBGACK or dspBR. */

dspCYC		= !BGACK & dspWIN & !SNOOP & !AS & CPUCLK 
		# dspCYC & dspWIN
		# dspCYC & dspBGACK
		# dspCYC & dspBR
		# dspCYC &  SNOOP
		# dspCYC & !CPUCLK;

/* This is the actual bus grant acknowledge logic for the system.  I drive
   this out to the system once dspCYC assures me that other system bu masters 
   have dropped it.  It stays on as long as dspCYC. */

BGACK		= dspCYC;
BGACK.OE	= dspCYC;

/* The grant out to the DSP, like most DSP signals, is driven synchronously.
   Grant back to the DSP will cause it to take the bus immediately, so I have
   to wait until I really have the bus before letting the DSP in on things.
   Once request is dropped by the DSP, I'll let grant go.  */

dspBG.D		= dspCYC & dspBR;
dspBG.AR	= RST;