PARTNO		31XXXX ;
		NAME		U203 ;
		DATE            October 1, 1991 ;
		REV             3 ;
		DESIGNER        Dave Haynie ;
		COMPANY         Commodore ;
		ASSEMBLY        A3000+ ;
		LOCATION        West Chester ;

/************************************************************************/
/*									*/
/*  A3000+	32 bit chip RAM Control logic				*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-10 				*/
/************************************************************************/
/*  Clock:		Made Here					*/
/************************************************************************/
/*  Free Pins:		10(I),11(I)					*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Aug 13:	Based on U203r2 for A3000+ Rev1 PCB.		*/
/*	DBH Sep 24:	Messed up Read/Write strobe directions.		*/
/*	DBH Oct  1:	Fixed DRA9 latch, CBLIT, turned off CMALT.	*/
/************************************************************************/

/**  Inputs  **/

PIN 1	 	=  ICLK 	;	/* Clock for any latched outputs */
PIN 2	 	= !RAS		;	/* RAS out of Alice */
PIN 3		= !CAS		;	/* CAS out of Alice */
PIN 4		= !BLIT		;	/* Unlatched BLIT from Alice */
PIN 5		= !WE		;	/* Write enable */
PIN 6		=  C3		;	/* Chip bus clocks */
PIN 7		=  C1		;
PIN 8		= !CDAC		;
PIN 9		=  RW		;	/* 68030 R/W line */
PIN 13		=  MA0		;	/* DRAM address line 0 */

/**  Outputs  **/

PIN 14		= !CMALT	;	/* Chip RAM address latch enable */
PIN 15		=  DRA9		;	/* Chip RAM address MA10 (DRAB9) */
PIN 16		= !BCRAS	;	/* Buffered RAS to Chip RAM */
PIN 17		=  DRW		;	/* DRAM R/W */
PIN 18		= !CBWE		;	/* Chip RAM buffer write enable */
PIN 19		= !CBRE		;	/* Chip RAM buffer read enable */
PIN 20	 	= !BRIDGE	;	/* Bridge D0-D15 to D16-D31 during CHIP access */
PIN 21	 	=  BRIDGEDIR	;	/* Direction to bridge data buses */
PIN 22 		= !CBLIT	;	/* BLIT latched through cycle */
PIN 23		=  OCLK		;	/* Clock output */

/**  Declarations and Intermediate Variable Definitions  **/

/* Which half of the bus? */

A1 		= MA0;

/**  Logic Equations  **/

/*	The current DRAM multiplexing scheme:

	MA10 MA9  MA8  MA7  MA6  MA5  MA4  MA3  MA2  MA1  MA0
	-----------------------------------------------------
ROW:	A22  A19  A18  A17  A16  A15  A14  A13  A12  A11  A20
COL:	A21  A10  A9   A8   A7   A6   A5   A4   A3   A2   A1

*/

/* This is the high order DRAM address.  We want to send out
   A20 on this, which is MA0 at RAS time, and get A1 for bridging,
   from MA0 at CAS time.  Since the A3000+ uses 512Kx8 DRAM for Chip
   RAM, this line is only important during RAS, so it stays as A20
   throughout the cycle. */

DRA9	=  MA0 & !CDAC & C1 & !CAS	/* Send A20 at RAS time */
	# DRA9 & C1			/* Latch it */
	# DRA9 & CAS;

/* Here's the bridge function.  We want the bridge turned on if there's
   a write cycle, or if the address is on an odd word. */

BRIDGE	= BLIT & C3 & CDAC & WE		/* ALWAYS Bridge on a Chip write... */
	# BLIT & C3 & CDAC & A1		/* ... or if A1 is high.       */
	# BRIDGE & RAS			/* Hold it through the cycle. */
	# BRIDGE & CAS;		

/* It's a bridge to the low order bank during a write, from the low order
   bank during a read (that's the default setting).  We latch this through
   the end of CAS, which again won't be a double CAS, because its a write
   cycle. */

!BRIDGEDIR	= !WE
		# !BRIDGEDIR & CAS;

/* This is a latched version of BLIT.  The A3000 latched this at RAS time
   and cleared it with C3 going low.  Latching it at RAS time is a good
   move, but clearing with C3 doesn't hold it through a double-CAS cycle.
   Here, I latch CBLIT at RAS time, but hold it through the end of the
   cycle, for single or double CAS cycles. */

CBLIT		=  BLIT &  RAS
		# CBLIT &  RAS
		# CBLIT &  CAS;

/* This one latches Chip RAM addresses, for support of static column mode
   DRAM.  This line is probably not necessary, since the new Alice is
   supposed to support static column DRAM, and now I'm using a different
   kind of DRAM on the Chip bus anyway.  But what the hell, I had the 
   free pin, and the latched buffer works as well as the non-latched
   buffer. */

CMALT		= 'b'0;

/* This is just a buffered RAS. */

BCRAS		=  RAS;

/* These are all basically buffered R/W lines.  The Chip RAM bus is buffered
   with 74ACT543 bidirectional transparent latches.  These parts have active
   low enables in each direction, so I create one strobe that's low during
   read, one that's low during write, to drive this. */

DRW		=  RW;

CBWE		= !RW;

CBRE		=  RW;