PARTNO		31XXXX ;
		NAME            U202 ;
		DATE            October 1, 1991 ;
		REV             3 ;
		DESIGNER        Dave Haynie ;
		COMPANY         Commodore ;
		ASSEMBLY        A3000+ ;
		Location        West Chester ;

/************************************************************************/
/*									*/
/*  A3000+	32 bit chip RAM CAS and banking logic			*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-10 				*/
/************************************************************************/
/*  Clock:		NONE						*/
/************************************************************************/
/*  Free Pins:		NONE						*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Aug 13:	Based on U202r4 for A3000+ Rev1 PCB.		*/
/*	DBH Sep 26:	Fixed bank logic write enable polarity.		*/
/*	DBH Oct  1:     Change for new banking logic gizmo.             */
/************************************************************************/

/** Inputs **/

PIN 1		= !RAS		;	/* RAS out of Alice */
PIN 2		= !CAS		;	/* CAS out of Alice */
PIN 3		= !LLDS		;	/* 68030 byte strobes */
PIN 4		= !LMDS		;
PIN 5		= !UMDS		;
PIN 6		= !UUDS		;
PIN 7		=  C3		;	/* Chip bus clocks */
PIN 8		=  C1		;
PIN 9		= !CDAC		;
PIN 10		= !WE		;	/* Write enable */
PIN 11		=  MEG8		;	/* For 8M, MA10, for 2M, GND */
PIN 13		=  MA0		;	/* Multiplexed Address 0 */
PIN 14		= !CBLIT	;	/* Latched blitter-busy line */
PIN 22		=  A21		;	/* CPU bank addresses */
PIN 23		=  A22		;

/**  Outputs  **/

PIN 15		=  !BENB	;	/* DRAM banking enable. */
PIN 16		=  BANK1	;	/* DRAM bank select. */
PIN 17		=  BANK0	;
PIN 18		= !CAS3		; 	/* Chip RAM CASs */
PIN 19		= !CAS2		;
PIN 20		= !CAS1		;
PIN 21		= !CAS0		;


/**  Declarations and Intermediate Variable Definitions  **/

/* The basic CAS qualifier for 68030 cycles */

CPUcyc		= !CBLIT & CAS & !CDAC & C3;

/* The basic CAS qualified for CHIP cycles */

CHIPcyc		=  CBLIT & CAS & CDAC & !C1;

/* The refresh cycle qualifier */

REFcyc		=  CAS & !RAS & C3;

/* Which half of the bus? */

A1 		= MA0;

/**  Logic Equations  **/

/*	The current DRAM multiplexing scheme:

	MA10 MA9  MA8  MA7  MA6  MA5  MA4  MA3  MA2  MA1  MA0
	-----------------------------------------------------
ROW:	A22  A19  A18  A17  A16  A15  A14  A13  A12  A11  A20
COL:	A21  A10  A9   A8   A7   A6   A5   A4   A3   A2   A1

*/

/* The CAS strobes.  CAS strobes are used as byte selects for each byte
   wide bank of DRAM.  CAS3 strobes for D31..D24, CAS2 strobes for 
   D23..D16, CAS1 strobes for D15..D8, and CAS0 strobes for D7..D0.
   The bridge banking is implicit here.  All reads are 32-bits wide
   if A1 is low, or to the low order data bank if A1 is high.  For
   writes, A1 low signals the high order data bank, A1 high the low
   order data bank. */


CAS3	=  CPUcyc & UUDS		/* start for 68030 */
	# CHIPcyc & !A1			/* start for CHIP */
	#  REFcyc			/* refresh */
	#  CAS3 & CAS;			/* hold */

CAS2	=  CPUcyc & UMDS		/* start for 68030 */
	# CHIPcyc & !A1			/* start for CHIP */
	#  REFcyc	 		/* refresh */
	#  CAS2 & CAS;			/* hold */

CAS1	=  CPUcyc & LMDS		/* start for 68030 */
	# CHIPcyc &  WE & A1		/* start for CHIP write */
	# CHIPcyc & !WE			/* start for CHIP read */
	#  REFcyc	 		/* refresh */
	#  CAS1 & CAS;			/* hold */

CAS0	=  CPUcyc & LLDS		/* start for 68030 */
	# CHIPcyc &  WE & A1		/* start for CHIP write */
	# CHIPcyc & !WE			/* start for CHIP read */
	#  REFcyc	 		/* refresh */
	#  CAS0 & CAS;			/* hold */


/* This scheme may be kind of brain damaged, but the replacement of this has 
   already been planned, using Greg's SIMM module logic, so we really don't 
   care.  The problem is that we don't have the full bank address until CAS
   time, since the Agnus generated A21 is on MEG8 at CAS time.  If we let any
   writes through before this, false writes will occur in the wrong bank.
   Letting the write strobe through afterwards, though, forces a late write
   cycle, which I'm not sure we want either.  Since this scheme will be
   obselete long before we have a working 8M Alice, I'm not worried about
   the banking here.  Since the actual bank is currently always known by RAS
   time or earlier, we can enable early on.  */

BENB	= RAS
	# BENB & CAS;

/* This is the DRAM banking address.  There will either be support for
   2M or for 8M, based on Alice.  The 8374 Alice can only drive 2M, and
   its MA10 line is pure nonsense, and must be ignored.  A new Alice 
   would supply A22 at RAS time, A22 at CAS time, on MA10.  The CPU gets
   its bank from CPU addresses A22 and A21, and therefore doesn't worry
   about the Alice version. */
   
BANK1	=  CBLIT & RAS &  C3 & !CDAC & MEG8	/* Chip access start, RAS time */
	# !CBLIT &  A22				/* CPU access start */
	#  BANK1 & RAS				/* Latch through end of memory cycle. */
	#  BANK1 & CAS;
	

BANK0	=  CBLIT & CAS & !C1 & !CDAC & MEG8	/* Chip access start */
	# !CBLIT &  A21				/* CPU access start */
	#  BANK0 & RAS				/* Latch through end of memory cycle. */
	#  BANK0 & CAS;