PARTNO		31XXXX ;
		NAME		U122 ;
		DATE		August 14, 1991 ;
		REV		1 ;
		DESIGNER	Dave Haynie ;
		COMPANY		Commodore ;
		ASSEMBLY	A3000+ ;
		LOCATION	West Chester ;

/************************************************************************/
/*									*/
/*  A3000+	DSP3210 Bus Arbiter/Interrupt Logic			*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-10 				*/
/************************************************************************/
/*  Clock:		dspCLK (50MHz)					*/
/************************************************************************/
/*  Free Pins:		2(I)						*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Aug 14:	Almost completely new.				*/
/************************************************************************/

/** Inputs **/

PIN 1		=  DSPCLK	;	/* DSP system clock */
PIN 3		= !DSPBR	;	/* DSP bus request */
PIN 4		= !SBR		; 	/* SCSI bus request */
PIN 5		= !XBG		;	/* System bus grant */
PIN 6		= !DSPBGACK	;	/* DSP bus grant acknowledge */
PIN 7		= !BERR		;	/* 68030 bus error */
PIN 8		= !DSPCI6	;	/* DSP interrupt out 6 */
PIN 9		= !DSPCI2	;	/* DSP interrupt out 2 */
PIN 10		= !BURST	;	/* DSP burst/block transfer */
PIN 11		=  A3		;	/* 68030 addresses */
PIN 13		=  A2		;

/**  Outputs  **/

PIN 16		= !INT2		;	/* Processor interrupt level 2 */
PIN 17		= !INT6		;	/* Processor interrupt level 6 */
PIN 18		= !DSPBERR	;	/* System bus error to DSP */
PIN 20		= !SBG		;	/* SCSI bus grant */
PIN 21		= !SBSYNC	;	/* SCSI bus request synch-up */
PIN 22		= !DSPBG	;	/* Bus grant to DSP */
PIN 23		= !XBR		;	/* System bus request */

/** Bidirectionals **/

PIN 14		= !DSPWIN	;	/* DSP wins the bus arbitration */
PIN 15		= !SNOOP	;	/* Arbitration/burst snooper */
PIN 19		= !BGACK	;	/* 68030 system bus grant acknowledge */

/**  Declarations and Intermediate Variable Definitions  **/

/**  Logic Equations  **/

/* The interrupts are simple -- see a request, send it out. */

INT2		= 'b'1;
INT2.OE		= DSPCI2;

INT6		= 'b'1;
INT6.OE		= DSPCI6;

/* As an output, the SNOOP line is asserted when A3-A2=11.  As an input,
   it's used by the BGACK logic. */

SNOOP		= DSPBGACK & A3 & A2;
SNOOP.OE	= DSPBGACK;

/* The DSP bus error line is just system BERR, when the DSP is bus
   master, synched up to the clock. */

DSPBERR.D	= BERR & DSPBGACK;

/* The SCSI bus request signal can come in asynchronously.  It needs to be
   synched up. */

SBSYNC.D	= SBR;


/* The system bus request goes out whenever DSP or SCSI want the bus.  Note
   that unlike 680x0 type bus requests, the DSP bus request stays low as
   long as the DSP wants the bus.  Therefore, we have to negate XBR once
   the DSP actually has the bus. */

XBR		= DSPBR & !DSPBGACK
		# SBR;


/* This is the basic bus arbiter.  Both SBG and DSPWIN can get a bus grant,
   but not both of them at once.  The DSP should be priority in a draw. */


DSPWIN.D	= XBG & DSPBR & !DSPBGACK;

SBG.D		= XBG & SBSYNC & DSPBGACK
		# XBG & SBSYNC & !DSPBR;

/* This is the actual bus grant acknowledge logic for the system.  The DSP's
   BG line is essentially a BGACK kind of thing, it says "go ahead now!".  
   So we need to get a real BGACK going before DSPBG can be asserted.  Like
   most of the DSP input, DSPBGACK is synchronous. */

BGACK		= !BGACK & DSPWIN & !SNOOP
		#  BGACK & DSPBR;
BGACK.OE	=  DSPBR;

DSPBG.D		= BGACK & DSPBR;