PARTNO	  	XXXXX ;
		NAME	  	U105;
		DATE	  	August 14, 1991;
		REV		1 ;
		DESIGNER	Dave Haynie ;
		COMPANY		Commodore ;
		ASSEMBLY	A3000+ ;
		LOCATION	West Chester ;

/************************************************************************/
/*									*/
/*  A3000+	Clock driver						*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-10	 			*/
/************************************************************************/
/*  Clock:		50MHz SYSTEM BASIS CLOCK			*/
/************************************************************************/
/*  Free Pins:		9(I),10(I),14(I/O),15(I/O)			*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Aug 14:	Brand stinking new				*/
/************************************************************************/

/**  Inputs  **/

PIN 1		=  C50M		;	/* 50MHz system basis clock */
PIN 2		=  C25FB	;	/* 25MHz feedback */
PIN 3		=  C25D10	;	/* 25MHz delayed by 10ns */
PIN 4		=  EXT90	;	/* External CLK90 */
PIN 5		=  EXTCPU	;	/* External CPUCLK */
PIN 6		=  JCPUCLK	;	/* "CPUCLK SRC" jumper */
PIN 7		=  JBOARD	;	/* "BOARDCLK SRC" jumper */
PIN 8		=  JCLK90	;	/* "CLK90 SRC" jumper */
PIN 11		=  DISCLKS	;	/* System clock disable */
PIN 13		=  DISCLK30	;	/* CLK30 disable */

/**  Outputs  **/

PIN 23		=  C25OUT	;	/* Primary 25MHz clock */
PIN 22		= !DSPCLKN	;	/* Inverted 50MHz DSP clock */
PIN 21		=  DSPCLKP	;	/* 50MHz DSP clock */
PIN 19		=  CPUCLKB	;	/* Second 25MHz CPUCLK */
PIN 17		=  CLK90B	;	/* Second 25MHz CLK90 */
PIN 16		=  CLK30	;	/* 25MHz 68030 clock */

/** Bidirectionals **/

PIN 20		=  CPUCLKA	;	/* First 25MHz CPUCLK */
PIN 18		=  CLK90A	;	/* First 25MHz CLK90 */

/** Declarations and Intermediate Variable Definitions **/

/* JUMPER EXPLANATION:

   The configuration jumper system here was designed to mimic that of
   the A3000.  There are more jumpers here than necessary, and since
   things are being logically switched, I won't let an invalid 
   situation exist like it can on the A3000.

   JCPUCLK, when low, expects clocks based on C25FB/C25D10, the on-board
   clocks.  When high, CLK30 comes from EXTCPU.  When JBOARD is low, 
   both CPUCLKs are supposed to be derived from EXTCPU, when high, the
   on-board clocks.  When JCLK90 is low, CLK90 is supposed to derive
   from the on-board clocks, when high, from EXTCLK90.  What really
   happens is a little different.  There are only three valid clock
   settings.  CPUCLK and CLK90 must both either be internal or external.
   CLK30 can be internal if CPUCLK/CLK90 are external, but if CLK30 is
   external, they all are.  The truth-table looks something like this:

	 J100	 J102	 J104
	JCLK90	JBOARD	JCPUCLK		CPUCLK	CLK90	CLK30

	   0	   0	   0		EXTCPU	EXT90	onboard
	   0	   0	   1		EXTCPU	EXT90	EXTCPU
	   0	   1	   0		onboard	onboard	onboard
	   0	   1	   1		EXTCPU	EXT90	EXTCPU
	   1	   0	   0		EXTCPU	EXT90	onboard
	   1	   0	   1		EXTCPU	EXT90	EXTCPU
	   1	   1	   0		EXTCPU	EXT90	onboard
	   1	   1	   1		EXTCPU	EXT90	EXTCPU

   The redundancy is simply to make things seem the same as on an
   A3000, mainly to avoid too much documentation redundancy.  For
   all intents and purposes, JBOARD is just !JCLK90.  The A3000 
   made it possible to set CPUCLK and CLK30 up asynchronous to one
   another, which yields a totally non-functional system.  That
   was not intentional, simply due to the A3000's switching of
   clocks through jumpers; one jumper could not control multiple
   clocks.
*/

syslocal	= !JCLK90 & JBOARD & !JCPUCLK;

/**  Logic Equations  **/

/* The primary 25MHz clock is simply the 50MHz clock divided by two. */

C25OUT.D	= !C25OUT;

/* The DSP clocks are simply the 50MHz clock run through the PAL, nomally.
   If external clocks are being sourced, we have to try and run synchronous
   to them.  There are two cases, either we're running from the EXTCLKs, or
   the system clocks are disabled and being driven on their own. */

DSPCLKN		=  syslocal & !DISCLKS & C50M
		# !syslocal & !DISCLKS &  (EXTCPU $ EXT90)
		#              DISCLKS & (CPUCLKA $ CLK90A);

DSPCLKP		=  syslocal & !DISCLKS & C50M
		# !syslocal & !DISCLKS &  (EXTCPU $ EXT90)
		#              DISCLKS & (CPUCLKA $ CLK90A);

/* The main system clocks here, which depend on input clocks and
   the system clock enables. */

CPUCLKA		=  syslocal & C25FB
		# !syslocal & EXTCPU;
CPUCLKA.OE	= !DISCLKS;

CPUCLKB		=  syslocal & C25FB
		# !syslocal & EXTCPU;
CPUCLKB.OE	= !DISCLKS;

CLK90A		=  syslocal & C25D10
		# !syslocal & EXT90;
CLK90A.OE	= !DISCLKS;

CLK90B		=  syslocal & C25D10
		# !syslocal & EXT90;
CLK90B.OE	= !DISCLKS;

/* The 68030 clock works in basically the same way, only the 
   enables are different. */

CLK30		= !JCPUCLK & C25FB
		#  JCPUCLK & EXTCPU;
CLK30.OE	= !DISCLK30;