PARTNO	  	XXXXX ;
		NAME	  	U3;
		DATE	  	September 19, 1991;
		REV		2 ;
		DESIGNER	Dave Haynie ;
		COMPANY		Commodore ;
		ASSEMBLY	A3000+ ;
		LOCATION	West Chester ;

/************************************************************************/
/*									*/
/*  A3000+ Gary+ Tower	Qualifier					*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-10	 			*/
/************************************************************************/
/*  Clock:		CPUCLK						*/
/************************************************************************/
/*  Free Pins:		I(3)						*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Aug 30:	Brand stinking new				*/
/*	DBH Sep 19:	Changed around DSACK machine			*/
/************************************************************************/

/**  Inputs  **/

PIN 1		=  CPUCLK	;	/* System clock */
PIN 2		= !N32ERR	;	/* Generate errors when unsizable */
PIN [4..10]	= [A18..12]	;	/* Bus address */
PIN 11		=  A1		;
PIN 13		=  A0		;
PIN 18		= !TERM		;	/* Termination signal */

/**  Outputs  **/

PIN 14		=  SCSICLK	;	/* SCSI bus clock */
PIN 15		= !BERR		;	/* Bus error */
PIN 19		= !NCPUCLK	;	/* Inverted CPUCLK */
PIN 21		= !NETREG	;	/* Network register select */
PIN 22		= !DSPREG	;	/* DSP reset register select */
PIN 23		= !RSTREG	;	/* Reset lock register select */

/**  Bidirectionals  **/

PIN 16		= !DSACK0	;	/* 68030 asynchronous termination */
PIN 17		= !DSACK1	;

/**  Used internally  **/

PIN 20		= !BERREN	;	/* Bus Error enable */

/**  Declarations and Intermediate Variable Definitions  **/

/* Main address of interest */

field addr	= [A18..A12,A1..A0];

/* Where the DSP reset register lives */

dreg		= addr:[61001];

/* Where the keyboard lock register lives */

kreg		= addr:[61000];

/* Where the network chip lives */

nreg		= addr:[10000..1ffff];

/**  Logic Equations  **/

/* The register qualifiers.  These babies just look at address. */

NETREG		= nreg;

RSTREG		= kreg;

DSPREG		= dreg;

/* The SCSI clock is just a CPUCLK divided by two. */

SCSICLK.D	= !SCSICLK;

/* The DSACK lines are driven when we have a network select or STERM. */

DSACK1		= TERM;
DSACK1.OE	= TERM;

DSACK0		= TERM;
DSACK0.OE	= TERM;

/* The bus error is driven if there's an N32ERR asserted and we see a
   non-32-bit termination. */

BERR		= 'b'0;
BERR.OE		= BERREN;

BERREN		= N32ERR & !(DSACK1 $ DSACK0);

/* The CPUCLK inversion... */

NCPUCLK		= CPUCLK;