PARTNO	  XXXXX ;
		NAME	  U681;
		DATE	  January 29, 1991;
		REV	  1 ;
		DESIGNER  Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  A3000+ ;
		LOCATION  U681 ;

/************************************************************************/
/*									*/
/*  A3000+	Interrupt mixing & latch, primary bus arbitration	*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 16R4A	 			*/
/************************************************************************/
/*  Clock:		7Mhz						*/
/************************************************************************/
/*  Free Pins:		14(Q)						*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Jan 29:	Descended from A3000 U701, Rev 2		*/
/************************************************************************/

/**  Inputs  **/

PIN 2		= !CIPL0	;	/* Chip conditioned interrupts */
PIN 3		= !CIPL1	;
PIN 4		= !CIPL2	;
PIN 5		= !PINT1	;	/* Bus interrupts */
PIN 6		= !PINT4	;
PIN 7		= !PINT5	;
PIN 8		= !PINT7	;
PIN 9		= !INTENB	;	/* Interrupt enable */

PIN 13		= !BG30		;	/* Bus Grant from 68030 */
PIN 18		= !CBR		;	/* Coprocessor slot bus request */
PIN 19		= !BOSS		;	/* Coprocessor slot owns system */

/**  Outputs  **/

PIN 17		= !IPL0		;	/* CPU interrupts */
PIN 16		= !IPL1		;
PIN 15		= !IPL2		;

PIN 12		= !BG		;	/* Bus grant out to Buster */

/** Declarations and Intermediate Variable Definitions **/

/* This sets up the different interrupt levels, as they may be 
   generated by Paula or the discrete interrupt lines.  These
   terms handle the prioritization. */

level0	= !CIPL2 & !CIPL1 & !CIPL0 & !(PINT1 # PINT4 # PINT5 # PINT7);

level1	= !CIPL2 & !CIPL1 &  CIPL0 & !(PINT4 # PINT5 # PINT7)
	#  PINT1 & !(PINT4 # PINT5 # PINT7);

level2	= !CIPL2 &  CIPL1 & !CIPL0 & !(PINT4 # PINT5 # PINT7);

level3	= !CIPL2 &  CIPL1 &  CIPL0 & !(PINT4 # PINT5 # PINT7);

level4	=  CIPL2 & !CIPL1 & !CIPL0 & !(PINT5 # PINT7)
	#  PINT4 & !(PINT5 # PINT7);

level5	=  CIPL2 & !CIPL1 &  CIPL0 & !PINT7
	#  PINT5 & !PINT7;

level6	=  CIPL2 &  CIPL1 & !CIPL0 & !PINT7;

level7	=  CIPL2 &  CIPL1 &  CIPL0 
	#  PINT7 ;

/**  Logic Equations  **/

/* Here we drive the interrupt bits. */

IPL2.D	= level7 & INTENB
	# level6 & INTENB
	# level5 & INTENB
	# level4 & INTENB ;

IPL1.D	= level7 & INTENB
	# level6 & INTENB
	# level3 & INTENB
	# level2 & INTENB ;

IPL0.D	= level7 & INTENB
	# level5 & INTENB
	# level3 & INTENB
	# level1 & INTENB ;

/* This is the bus grant output term.  In general, we want BG30 connected
   with BG when the coprocessor is not in charge of things.  However, we
   have to take care that this arbitration doesn't take place out of sync
   with the secondary arbitrations that happen in Buster.  So the CPU slot
   can't assert CBR until it sees BG and BGACK negated.  The CBR term here
   keeps the Coprocessor-initiated BG from being seen by the main bus
   arbiter.  The 68030 and coprocessor slots are called primary bus masters;
   they're the ones responsible for driving BG and acknowledging BR. */

BG	= BG30 & !CBR;
BG.OE	= !BOSS;