PARTNO		31XXXX ;
		NAME		U203 ;
		DATE            11/27/90 ;
		REV             01 ;
		DESIGNER        Greg Berlin ;
		COMPANY         Commodore ;
		ASSEMBLY        A3000+ ;
		LOCATION        U203 ;

/************************************************************************/
/*									*/
/*  A3000+	32 bit chip RAM Control logic				*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 16L8-10 				*/
/************************************************************************/
/*  Clock:		NONE						*/
/************************************************************************/
/*  Free Pins:		12(O),19(O)					*/
/************************************************************************/
/*  HISTORY								*/
/*	GCB Dec 27:	Completely new.					*/
/*	DBH Jan 31:	Whoops, didn't run C1 here.  Jumper #1.		*/
/************************************************************************/

/**  Inputs  **/

PIN 1	 	=  CPU8M	;	/* CPU space is 8MB (else 2MB) */
PIN 2	 	=  CHIP8M	;	/* CHIP space is 8MB (else 2MB) */
PIN 3		=  MA0		;	/* DRAM address line 0 */
PIN 4	  	= !CAS		;	/* CAS out of ALICE */
PIN 5		= !RAS		;	/* RAS out of ALICE */
PIN 6	 	= !PBLIT	;	/* Unlatched BLIT */
PIN 7	 	= !WE		;	/* Write enable */
PIN 8	 	=  C3		;	/* Video clocks */
PIN 9		= !CDAC		;
PIN 16		=  C1		;
PIN 11		=  MA10I	;	/* DRAM Adress 10 from Alice */
PIN 18	 	= !BLIT		;	/* Blitter access */

/**  Outputs  **/

PIN 13		=  MA10O	;	/* Mux'ed Adr bit 10 output */
PIN 14	 	= !BRIDGE	;	/* Bridge D0-D15 to D16-D31 during CHIP access */
PIN 15	 	=  BRIDGEDIR	;	/* Direction to bridge data buses */
PIN 17 		= PLAU		;	/* Bank select address bit */

/**  Declarations and Intermediate Variable Definitions  **/

/* Which half of the bus? */

A1 		= MA0;

/**  Logic Equations  **/

/*	The current DRAM multiplexing scheme:

	MA10 MA9  MA8  MA7  MA6  MA5  MA4  MA3  MA2  MA1  MA0
	-----------------------------------------------------
ROW:	A22  A19  A18  A17  A16  A15  A14  A13  A12  A11  A20
COL:	A21  A10  A9   A8   A7   A6   A5   A4   A3   A2   A1

*/

!MA10O	= !MA0 & !CDAC & C1 & !CAS /* Route MA0 (A20) to it at RAS time */
	# !MA10I & CDAC & C3	   /* Route it straight thru at CAS time ... */
	# !MA10I & C1		   /* ... hold it ... */
	# !MA10I & CAS;		   /* ... hold it 'til CAS goes away. */

BRIDGE	= BLIT & C3 & CDAC & WE		/* ALWAYS Bridge on a Chip write... */
	# BLIT & C3 & CDAC & A1		/* ... or if A1 is high.       */
	# BRIDGE & (CAS # RAS);		/* Hold it on ... */

!BRIDGEDIR	= !WE
		# !BRIDGEDIR & CAS;

!PLAU	= !CDAC &  PBLIT &  CHIP8M & !MA10I	/* 8 meg CHIP space */
	# !CDAC &  PBLIT & !CHIP8M & !MA0	/* 2 meg CHIP space */
	# !CDAC & !PBLIT &   CPU8M & !MA10I	/* 8 meg CPU space */
	# !CDAC & !PBLIT &  !CPU8M & !MA0;	/* 2 meg CPU space */