PARTNO		31XXXX ;
		NAME            U202 ;
		DATE            March 7, 1991 ;
		REV             4 ;
		DESIGNER        Greg Berlin ;
		COMPANY         Commodore ;
		ASSEMBLY        A3000+ ;
		Location        U202 ;

/************************************************************************/
/*									*/
/*  A3000+	32 bit chip RAM CAS logic 				*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 22V10-10 				*/
/************************************************************************/
/*  Clock:		NONE						*/
/************************************************************************/
/*  Free Pins:		22(IO)						*/
/************************************************************************/
/*  HISTORY								*/
/*	GCB Dec 27:	Completely new.					*/
/*	DBH Feb  5:	BIGTIME Pinout corrections!			*/
/*	DBH Feb  7:	CAS and RAS were reversed.  Now they aren't.	*/
/*	DBH Mar  5:	Kludge for slow addresses during CPU access.	*/
/*	DBH Mar  7:	Fix low word CAS for 32 bit fetch modes!	*/
/************************************************************************/

/** Inputs **/

PIN 1		= !RAS		;	/* RAS out of ALICE */
PIN 2		= !CAS		;	/* CAS out of ALICE */
PIN 3		= !LLDS		;	/* 68030 byte strobes */
PIN 4		= !LMDS		;
PIN 5		= !UMDS		;
PIN 6		= !UUDS		;
PIN 7		=  C3		;	/* Video clocks */
PIN 8		=  C1		;
PIN 9		= !CDAC		;
PIN 10		= !BLIT		;	/* Blitter Busy */
PIN 11		=  MA0		;	/* Multiplexed Address 0 */
PIN 13		=  LAU		; 	/* Latched MSb of Address */
PIN 23		= !WE		;	/* Write enable */

/**  Outputs  **/

PIN 21		= !CAS0		; 	/* Chip RAM CASs */
PIN 20		= !CAS1		;
PIN 19		= !CAS2		;
PIN 18		= !CAS3		;
PIN 17		= !CAS4		;
PIN 16		= !CAS6		;
PIN 15		= !CAS5		;
PIN 14		= !CAS7		;

/**  Declarations and Intermediate Variable Definitions  **/

/* The basic CAS qualifier for 68030 cycles */

CPUcyc		= !BLIT & CAS & !CDAC & C3;

/* The basic CAS qualified for CHIP cycles */

CHIPcyc		=  BLIT & CAS & CDAC & !C1;

/* The refresh cycle qualifier */

REFcyc		=  CAS & !RAS & C3;

/* Which half of the bus? */

A1 		= MA0;

/**  Logic Equations  **/

/*	The current DRAM multiplexing scheme:

	MA10 MA9  MA8  MA7  MA6  MA5  MA4  MA3  MA2  MA1  MA0
	-----------------------------------------------------
ROW:	A22  A19  A18  A17  A16  A15  A14  A13  A12  A11  A20
COL:	A21  A10  A9   A8   A7   A6   A5   A4   A3   A2   A1

*/

/* CAS lines for DRAM on the high side of the data bus */

CAS0	=  CPUcyc & !LAU & UMDS			/* start for 68030 */
	# CHIPcyc & !LAU & !A1			/* start for CHIP */
	#  REFcyc	 			/* refresh */
	#  CAS0 & CAS;				/* hold */

CAS1	=  CPUcyc & !LAU & UUDS			/* start for 68030 */
	# CHIPcyc & !LAU & !A1			/* start for CHIP */
	#  REFcyc				/* refresh */
	#  CAS1 & CAS;				/* hold */

CAS2	=  CPUcyc &  LAU & UMDS			/* start for 68030 */
	# CHIPcyc &  LAU & !A1			/* start for CHIP */
	#  REFcyc	 			/* refresh */
	#  CAS2 & CAS;				/* hold */

CAS3	=  CPUcyc &  LAU & UUDS			/* start for 68030 */
	# CHIPcyc &  LAU & !A1			/* start for CHIP */
	#  REFcyc	 			/* refresh */
	#  CAS3 & CAS;				/* hold */

/* CAS lines for DRAM on the low side of the data bus */

CAS4	=  CPUcyc & !LAU & LLDS			/* start for 68030 */
	# CHIPcyc & !LAU & A1 & WE		/* start for CHIP write */
	# CHIPcyc & !LAU & !WE			/* start for CHIP read */
	#  REFcyc		 		/* refresh */
	#  CAS4 & CAS;				/* hold */

CAS5	=  CPUcyc & !LAU & LMDS			/* start for 68030 */
	# CHIPcyc & !LAU & A1 & WE		/* start for CHIP write */
	# CHIPcyc & !LAU & !WE			/* start for CHIP read */
	#  REFcyc	 		 	/* refresh */
	#  CAS5 & CAS;				/* hold */

CAS6	=  CPUcyc &  LAU & LLDS			/* start for 68030 */
	# CHIPcyc & !LAU & A1 & WE		/* start for CHIP write */
	# CHIPcyc & !LAU & !WE			/* start for CHIP read */
	#  REFcyc  				/* refresh */
	#  CAS6 & CAS;				/* hold */

CAS7	=  CPUcyc &  LAU & LMDS			/* start for 68030 */
	# CHIPcyc & !LAU & A1 & WE		/* start for CHIP write */
	# CHIPcyc & !LAU & !WE			/* start for CHIP read */
	#  REFcyc		 		/* refresh */
	#  CAS7 & CAS;				/* hold */