PARTNO		31XXXX ;
		NAME            U122 ;
		DATE            January 28, 1991 ;
		REV             1 ;
		DESIGNER        Dave Haynie ;
		COMPANY         Commodore ;
		ASSEMBLY        A3000+ ;
		Location        U122 ;

/***** CHECK OUT ALL EDGE-BASED SIGNALS CAREFULLY!  THIS MAY NEED TO GROW
       SOME.... *****/

/************************************************************************/
/*									*/
/*  A3000+	DSP3210 Bus Interface Logic  				*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 20R4-10 				*/
/************************************************************************/
/*  Clock:		CPUCLK (25MHz)					*/
/************************************************************************/
/*  Free Pins:		11(I),14(I),23(I)				*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Jan 28:	Completely new.					*/
/************************************************************************/

/** Inputs **/

PIN 2		= !dspBR	;	/* DSP Bus Request */
PIN 3		= !dspAS	;	/* DSP Address Strobe */
PIN 4		= !dspCS	; 	/* DSP Cycle Start */
PIN 5		=  RW		;	/* 030 R/W Strobe */
PIN 6		= !RMC		;	/* 030 Bus Lock */
PIN 7		= !DSACK0	;	/* 030 Asynchronous termination */
PIN 8		= !DSACK1	;
PIN 9		= !STERM	;	/* 030 Synchronous termination */
PIN 10		= !SBR		;	/* SCSI Bus Request */
PIN 14		= !dspBGACK	;	/* The DSP has mastered the bus */
PIN 15		= !BERR		;	/* 030 Bus Error */

/**  Outputs  **/

PIN 16		= !BR		;	/* Bus request */
PIN 17		=  FC1		;	/* 030 Function code 1 */
PIN 18		= !DS		;	/* 030 Data Strobe */
PIN 19		= !AS		;	/* 030 Address Strobe */
PIN 20		= !XFER32	;	/* A 32 bit transfer is done */
PIN 21		=  dspDLE	;	/* DSP Data Latch */
PIN 22		= !preBERR	;	/* Unsynched DSP Bus Error */

/**  Declarations and Intermediate Variable Definitions  **/

/**  Logic Equations  **/

/* For now at least, a master bus request is simply either the DSP or the
   SCSI device requesting the bus.  The arbiter PAL worries about who really 
   gets it.... */

XBR		= dspBR & !dspBGACK
		# SBR;

/* We need to indicate some valid memory space when the DSP has the bus. 
   If this wasn't a clocked output (doesn't need to be), it would have its
   output enabled driven by dspBGACK. */

FC1.D	= 'b'0;

/* The DSP's address strobe needs to be clocked by the bus clock to become
   a 68030 bus equivalent AS*.  Doesn't this really want to be clocked on
   CPUCLK*? */

AS.D		= dspAS;

/* A 68030 data strobe is based on dspAS or AS, depending on whether we have
   a read or a write cycle.  This wants the same clocking edge as AS*.  */

DS.D		=  RW & dspAS
		# !RW & AS & dspAS;

/* A 32-bit transfer based on asynchronous termination is from both DTACKs. 
   This is pretty happy being clocked by CPUCLK. */

XFER32.D	= DSACK0 & DSACK1 & AS;

/* This latches data into the DSP3210.  This seems to require a CPUCLK*
   clocking edge, since data is valid on the falling edge after STERM*
   or XFER32*.  */

!dspDLE		= dspBGACK & RW & STERM
		# dspBGACK & RW & XFER32;

/* Signal an error to the DSP if it attempts to access non-32 bit memory. 
   Also, externally generated BERR will get passed along to the DSP's BERR 
   if the DSP owns the bus. */

preBERR		= dspBGACK & DSACK0 & !DSACK1
		# dspBGACK & !DSACK0 &  DSACK1
		# dspBGACK & BERR;