PARTNO		U301 ;
	NAME		ARBITRATION ;
	DATE		May 23, 1991 ;
	REV		1 ;
	DESIGNER	Dave Haynie;
	COMPANY		Commodore ;
	ASSEMBLY	A2631 ;
	LOCATION	West Chester;

/************************************************************************/
/*									*/
/*	A2631	Bus Arbitration						*/
/*									*/
/*	This deals with powerup bus takeover, expansion & SCSI bus	*/
/*	arbitration, and VPA/VMA protocol.  It assumes the A2000 has	*/
/*	a 68000 on board.						*/
/*									*/
/************************************************************************/
/*									*/
/* DEVICE DATA:								*/
/*									*/
/*	Device:		22V10-15					*/
/*	Clock:		A7M						*/
/*	Unused:		NONE						*/
/*									*/
/************************************************************************/
/*									*/
/* REVISION HISTORY:							*/
/*									*/
/*	DBH	May 23:	Original version.				*/
/*									*/
/************************************************************************/

/** INPUTS: **/

PIN 1		=	 A7M		;	/* A2000 7MHz clock */
PIN [2..4]	=	![AIPL0..2]	;	/* Input interrupts */
PIN 5		=	 E		;	/* A2000 E clock */
PIN 6		=	!VPA		;	/* A2000 VPA */
PIN 7		=	!ADTACK		;	/* A2000 output DTACK */
PIN 8		=	!MODE68K	;	/* 68000 mode */
PIN 9		=	!HALT		;	/* A2000 halt line */
PIN 10		=	!RESET		;	/* A2000 reset line */
PIN 11		=	!ABG		;	/* Coprocessor bus grant */
PIN 13		=	!AAS		;	/* A2000 address strobe */

/** OUTPUTS: **/

PIN 14		=	!BOSS		;	/* A2000 bus BOSS */
PIN 15		=	!ABR		;	/* Coprocessor bus request */
PIN 19		=	!DTACK		;	/* DTACK* to Buster */
PIN 20		=	!VMA		;	/* Valid memory address */
PIN [21..23]	=	![IPL2..0]	;	/* Synchronized interrupts */

/** BIDIRECTIONALS **/


/** USED INTERNALLY **/

PIN 16		=	SY2		;	/* VMA counter */
PIN 17		=	SY1		;
PIN 18		=	SY0		;

/** INTERNAL TERMS: **/

/** OUTPUT TERMS: **/

/* This is the bus grabber mechanism.  I wait for reset to finish up, then grab
   the 68000 bus by asserting ABR*, waiting for ABG*.  When I get ABG*, BOSS* is
   asserted, ABR* negated and tri-stated. */

ABR		= !RESET & !DTACK &  !AAS & !MODE68K
		#    ABR & !RESET & !HALT & !MODE68K;

BOSS		=  ABR & ABG & !RESET & !HALT
		# BOSS & !RESET & !MODE68K
		# BOSS &  !HALT & !MODE68K;

/* Here's the simple interrupt synchronizer. */

IPL2.D		= AIPL2;
IPL1.D		= AIPL1;
IPL0.D		= AIPL0;


/* Now we manage the E-Clock nonsense.  Basically, VPA* comes in any time it likes.
   I generate DTACK* here to cause the cycle's end to be nicely lined up with the 
   high end of E.  Data latching, of course, still takes place.  */

SY2.D		=  SY0 & SY1 & VPA
		#  SY2 & AAS;


SY1.D		=  SY0 & !SY1 & !SY2 & !E & VPA
                #  SY0 & !SY1 &  SY2 &  E
                #         SY1 &  SY2 &  E;

		
SY0.D		=  AAS & BOSS & !E & VPA
		# !SY0 &  SY1 & !SY2 & !E & VPA
		# !SY0 & !SY1 &  SY2 &  E
		#         SY1 &  SY2 &  E;

/* The DTACK* line is just the composite of the input DTACK* and the VPA* generated
   DTACK*. */

DTACK		= ADTACK
		# !SY0 &  SY1 &  SY2 &  E;

/* VMA* goes out when we've found the safe part of the E cycle. */

VMA		= !SY0 & !SY1 &  SY2 &  E
		#  VMA &  SY2;