name	TAXLAT;
Partno	xx;
Revision 01;
Date	11/24/89;
Designer Scott Schaeffer;
Company	CBM;
Assembly A3000 040 coprocessor;
Location U213;
Device	G22V10;

/**	68040 Bus translator Control PAL **/
/**	heisted from MOT bus adapter app note **/

/** Inputs **/

PIN [1..4]	=	[a1,a0,siz1,siz0];
PIN [5..9]	=	[tt1,tt0,tm2,tm1,tm0];
PIN [10,11,13,14]	=	[mast3,mast2,mast1,mast0];
PIN 23		=	TRI;

/** Outputs **/
 
PIN [22,21,19,18]	=	[_030_a1,_030_a0,_030_siz1,_030_siz0];
PIN [17..15]	=	[fc2,fc1,fc0];
PIN 20      	=	!iack;

/** Declarations**/
 
field mreg = [mast3,mast2,mast1,mast0];
field address = [a1,a0];
field size = [siz1,siz0];
field type = [tt1,tt0];
field mod  = [tm2,tm1,tm0];
field fcode = [fc2,fc1,fc0];
field _030_size = [_030siz1,030_siz0];
field _030_addr = [_030_a1,_030_a0];

/** master state definitions **/
$define MSI 'h'0
$define MSA 'h'1
$define MSB 'h'5
$define MSC 'h'D
$define MSD 'h'4
$define MSE 'h'C
$define MSF 'h'9
$define MSG 'h'B
$define MSH 'h'F
$define MSJ 'h'E
$define MSK 'h'3
$define MSL 'h'2
$define MSM 'h'7
$define MSN 'h'6
$define MSZ 'h'8
$define MSDC 'h'A
 
 
/** Master state equates **/
i = mreg:'h'0;
a = mreg:'h'1;
b = mreg:'h'5;
c = mreg:'h'D;
d = mreg:'h'4;
e = mreg:'h'C;
f = mreg:'h'9;
g = mreg:'h'B;
h = mreg:'h'F;
j = mreg:'h'E;
k = mreg:'h'3;
l = mreg:'h'2;
m = mreg:'h'7;
n = mreg:'h'6;
z = mreg:'h'8;
dc = mreg:'h'A;
 
$define norm 'h'00
$define alt  'h'02
$define intack  'h'03
$define mov16  'h'01
 
$define line   'h'03
$define long   'h'00
$define word   'h'02
$define byte   'h'01

$define sup_dat  'h'1
$define sup_cod  'h'6
$define usr_dat  'h'0
$define usr_cod  'h'2
$define cpu_spc  'h'7

/**	logic equations		**/
_030_a0		=	i & a0
		#	z & a0
		#	dc & a0
		#	c # e # h # j # l # n;

_030_a1		=	i & a1
		#	z & a1
		#	dc & a1
		#	b # d # e # g # j # m # n;

_030_siz0	=	i & siz0 & !(siz0 & siz1)
		#	z & siz0
		#	dc & siz0
		#	c # e # h # j # k # l # m # n;

_030_siz1	=	i & siz1 & !(siz0 & siz1)
		#	z & siz1
		#	dc & siz1
		#	b # d # f # g;

fc2		=	type:intack 
		#	type:mov16 & tm2 
		#	type:alt & tm2
		#	type:norm & mod:'h'0
		#	type:norm & mod:'h'3
		#	type:norm & mod:'h'4
		#	type:norm & mod:'h'5
		#	type:norm & mod:'h'6
		#	type:norm & mod:'h'7;

fc1		=	type:intack 
		#	type:alt & tm1
		#	type:norm & mod:'h'2
		#	type:norm & mod:'h'6;

fc0		=	type:intack
		#	type:mov16 & tm0
		#	type:alt & tm0
		#	type:norm & mod:'h'0
		#	type:norm & mod:'h'1
		#	type:norm & mod:'h'3
		#	type:norm & mod:'h'4
		#	type:norm & mod:'h'5
		#	type:norm & mod:'h'7;







iack	=	type:intack & address:3;
_030_a0.oe	=	!TRI;
_030_a1.oe	=	'b'1;
fc2.oe		=	!TRI;
fc1.oe		=	!TRI;
fc0.oe		=	!TRI;
_030_siz0.oe	=	!TRI;
_030_siz1.oe 	=	!TRI;