Name	OEBUS;
Partno	xx;
Revision 01;
Date	10/24/89;
Designer Scott Schaeffer;
Company	CBM;
Assembly A3000 040 coprocessor;
Location U207;
Device	G22V10;

/**	68040 Bus translator Control PAL **/
/**	heisted from MOT bus adapter app note **/

/** Inputs **/

PIN 1		=	bclk;
PIN [2..5]	=	[mast0,mast1,mast2,mast3];
PIN [6..8]	=	[!s2w,s1,rd];
PIN [9..11]	=	[!rberr,!rdsack0,!rdsack1];

/** Outputs **/
 
PIN [23..15]	=	[!dmaoe,!aoe,!b2oe,!b1oe,!c2oe,!c1oe,!d3oe,!d2oe,!d1oe];

/** Declarations**/
 
field mreg = [mast3,mast2,mast1,mast0];
field DSACK = [rdsack1,rdsack0];

/** master state definitions **/
$define MSI 'h'0
$define MSA 'h'1
$define MSB 'h'5
$define MSC 'h'D
$define MSD 'h'4
$define MSE 'h'C
$define MSF 'h'9
$define MSG 'h'B
$define MSH 'h'F
$define MSJ 'h'E
$define MSK 'h'3
$define MSL 'h'2
$define MSM 'h'7
$define MSN 'h'6
$define MSZ 'h'8
$define MSDC 'h'A
 
 
/** master state equates **/
i = mreg:'h'0;
a = mreg:'h'1;
b = mreg:'h'5;
c = mreg:'h'D;
d = mreg:'h'4;
e = mreg:'h'C;
f = mreg:'h'9;
g = mreg:'h'B;
h = mreg:'h'F;
j = mreg:'h'E;
k = mreg:'h'3;
l = mreg:'h'2;
m = mreg:'h'7;
n = mreg:'h'6;
z = mreg:'h'8;
dc = mreg:'h'A;
 
$define wr (!rd) 
$define long ( rdsack1 & rdsack0 & !rberr )
$define word ( rdsack1 & !rdsack0 & !rberr)
$define byte ( !rdsack1 & rdsack0 & !rberr )
 

/** logic equations **/

aoe.d	=	wr & (a # f # k) & !s1
	#	rd & ((byte # word # long) & s1 # aoe & s2w);

b2oe.d	=	wr & (c # h # l) & !s1
	#	rd & (byte & s1 # b2oe & s2w);

b1oe.d	=	wr & (a # f # h # k # l # m) & !s1
	#	rd & ((word # long) & s1 # b1oe & s2w);
 
c2oe.d	=	wr & (d # g # m # b) & !s1
	#	rd & ((byte # word) & s1 # c2oe & s2w);

c1oe.d	=	wr & !(i # z) & !s1
	#	rd & ((long & s1) # c1oe & s2w);

d3oe.d	=	wr & (e # j # n) & !s1
	#	rd & ((byte & s1) # d3oe & s2w);

d2oe.d	=	wr & (c # b # d # e # g # j # n) & !s1
	#	rd & ((word & s1) # d2oe & s2w);

d1oe.d	=	wr & !(i # z # l) & !s1
	#	rd & ((long & s1) # d2oe & s2w);

dmaoe.d =	wr & l & !s1;