Name	LEBUS;
Partno	xx;
Revision 01;
Date	11/24/89;
Designer Scott Schaeffer;
Company	CBM;
Assembly A3000 040 coprocessor;
Location U208;
Device	G16V8;

/** 68040 Bus translator Control PAL **/
/**	heisted from MOT bus adapter app note **/

/** Inputs **/

PIN 1		=	bclk;
PIN [3]		=	[!s3_or_sr1];
PIN [4..7]	=	[mast0,mast1,mast2,mast3];
PIN [8..9]	=	[!at,!st];
PIN 11		=	!oe;

/** Outputs **/
 
PIN [19..12]	=	[a_le,b2_le,b1_le,c2_le,c1_le,d3_le,d2_le,d1_le];

/** Declarations**/
 
field mreg = [mast3,mast2,mast1,mast0];

 
 
/** master state equates **/
i = mreg:'h'0;
a = mreg:'h'1;
b = mreg:'h'5;
c = mreg:'h'D;
d = mreg:'h'4;
e = mreg:'h'C;
f = mreg:'h'9;
g = mreg:'h'B;
h = mreg:'h'F;
j = mreg:'h'E;
k = mreg:'h'3;
l = mreg:'h'2;
m = mreg:'h'7;
n = mreg:'h'6;
z = mreg:'h'8;
dc = mreg:'h'A;
 
$define neg_le (s3_or_sr1)

/** don't latch on burst cycle **/ 

/** Logic equations **/

a_le.d	=	at # st # (a_le & !neg_le  & (i # z # a # f # k)) # b # c 
	#	d # e # h;

b1_le.d =	at # st # (b1_le & !neg_le & (i # z # a # f # l)) # b;

b2_le.d =	at # st # (b2_le & !neg_le & (i # z # c # h # l)) # d
	#	e;

c1_le.d =	at # st # (c1_le & !neg_le & (i # z # a # g # m));

c2_le.d =	at # st # (c2_le & !neg_le & (i # z # b # g # m # d
	#	dc)) # e # j # c # h;

d1_le.d =	at # st # (d1_le & !neg_le & (i # z # a # g # n)); 

d2_le.d =	at # st # (d2_le & !neg_le & (i # z # b # g # n # dc)); 

d3_le.d =	at # st # (d3_le & !neg_le & (i # z # j # n # e));