name	BUSTERM;
Partno	xx;
Revision 02;
Date	12/10/89;
Designer Scott Schaeffer;
Company	CBM;
Assembly A3000 040 enhanced coprocessor;
Location U205;
Device	G22V10;

/**	68040 Bus translator Termination PAL **/
/**	heisted from MOT bus adapter app note **/

/** Inputs **/

PIN 1		=	bclk;
PIN [2..6]	=	[rd,slave0,slave1,slave2,slave3];
PIN [9,10]	=	[!plsterm,!aterm];
PIN [7,8,11,13]	=	[!cycpend,siz1,!ts,siz0];
PIN [23] =	[!bgack040];
PIN 21		=	!rsti;
/** Outputs **/
 
PIN 22		=	!ta;
PIN 20		=	[!tbi];
PIN [17..15,18,19] =	[!as,!ds,!nca,!ncb,!tea];
/** Declarations**/
 
field strob = [as,ds,nca,ncb];
field sreg = [slave3,slave2,slave1,slave0];

 
/** slave state definitions **/
$define S0 4
$define S1 8
$define S2 1
$define SB 6
$define S3 0
 
 
/** slave state equates **/
s0 = sreg:4;
$define s1 slave3
s2 = sreg:1;
sb = sreg:6;
s3 = sreg:0;
 
/** abbreviations for state transiations **/
$define sidle 'b'0000 
/** idle state wait for ts assertion **/
$define ts_rec 'b'0010  
/** transfer start recognized **/
$define rd_state 'b'1100 
/** assert as and ds**/
$define wr_state 'b'1000 
/** assert as only **/
$define wait_term 'b'1101
/** wait for termination **/
$define cycle_end 'b'0001 

$define wr = !rd
c_end = strob:1;

$define start (ts # cycpend) & bgack040
$define line siz1 & siz0

/** logic equations **/
tbi	=	s2 & line & c_end;
ta	=	s2 & c_end ;
tea 	=	sb;
 
sequence strob {

	present sidle	if start		next ts_rec;
			if !start		next sidle;

	present ts_rec	if rd & !rsti 	next rd_state;
			if !rd & !rsti	next wr_state;
			if rsti 	next sidle;

	present rd_state if !plsterm	next wait_term;
			if plsterm 	next cycle_end;

	present wr_state if !plsterm	next wait_term;
			if plsterm 	next cycle_end;

	present wait_term	if (aterm # plsterm )	next cycle_end;
			if !(aterm # plsterm) 		next wait_term;
 
	present cycle_end	if (s2 # sb) & !(s3) next sidle;
			if !(s2 # sb) & (s3) & rd & !rsti next rd_state;
			if !(s2 # sb) & (s3) & !rd & !rsti next wr_state;
			if !(s2 # sb) & !(s3) & !rsti next cycle_end;
			if (s2 # sb) & (s3) next sidle;
			if rsti next sidle;

}