name	BUSCON;
Partno	xx;
Revision 01;
Date	10/24/89;
Designer Scott Schaeffer;
Company	CBM;
Assembly A3000 040 coprocessor;
Location U204;
Device	G22V10;
/**	68040 Bus translator Control PAL **/
/**	halt wait and retry NOT supported due to EC small buffer mode **/
/** USE -m0 to reduce all others run out of memory                    **/
/** Inputs **/

PIN 1		=	bclk;
PIN [2..6,23]	=	[!bgack040_,a0,a1,siz0,siz1,!ts];
PIN [7..11]	=	[!term,!rdsack1,!rdsack0,!rberr,!cycpend];
PIN 14     	=	!lsterm;
PIN 13		=	!reset;

/** Outputs **/
 
PIN [22..19]	=	[mast1,mast0,mast2,mast3];
PIN [18..16] =	[slave1,slave2,slave0];
PIN 15		=	slave3;
/** Declarations**/
 
field mreg = [mast3,mast2,mast1,mast0];
field sreg = [slave3,slave2,slave1,slave0];
field ADDR = [a1,a0];
field SIZE = [siz1,siz0];
field DSACK = [rdsack1,rdsack0];
field sreg_sub = [slave2,slave1,slave0];

/** master state definitions **/
$define MSI 'h'0
$define MSA 'h'1
$define MSB 'h'5
$define MSC 'h'D
$define MSD 'h'4
$define MSE 'h'C
$define MSF 'h'9
$define MSG 'h'B
$define MSH 'h'F
$define MSJ 'h'E
$define MSK 'h'3
$define MSL 'h'2
$define MSM 'h'7
$define MSN 'h'6
$define MSZ 'h'8
$define MSDC 'h'A
 
/** slave state definitions **/
$define S0 4
$define S1 8
$define S2 1
$define SB 6
$define S3 0
 
/** master state equates **/
i = mreg:'h'0;
a = mreg:'h'1;
b = mreg:'h'5;
c = mreg:'h'D;
d = mreg:'h'4;
e = mreg:'h'C;
f = mreg:'h'9;
g = mreg:'h'B;
h = mreg:'h'F;
j = mreg:'h'E;
k = mreg:'h'3;
l = mreg:'h'2;
m = mreg:'h'7;
n = mreg:'h'6;
z = mreg:'h'8;
dc = mreg:'h'A;
 
/** slave state equates **/
s0 = sreg:4;
$define s1 slave3
s2 = sreg:1;
sb = sreg:6;
s3 = sreg:0;
 
/** abbreviations for state transitions **/
line = SIZE:'b'11;
long = SIZE:'b'00;
word = SIZE:'b'10;
byte = SIZE:'b'01;
 
addr0 = ADDR:'b'00;
addr1 = ADDR:'b'01;
addr2 = ADDR:'b'10;
addr3 = ADDR:'b'11;
 
$define longport ( rdsack1 & rdsack0 & !rberr )
$define wordport ( rdsack1 & !rdsack0 & !rberr)
$define byteport ( !rdsack1 & rdsack0 & !rberr )
$define noport ( !rdsack1 & !rdsack0 & !rberr )
 
$define bus_err ( rberr )
 
$define first_term_sample (rdsack0 # rdsack1 # rberr)

$define f1  (rdsack1 & rdsack0 & !rberr & (a # f # g # k # l # m # n))
$define f2  (rdsack1 & !rdsack0 & !rberr & (b # f # g # k # l # m # n))
$define f3  (!rdsack1 & rdsack0 & !rberr & (e # h # j # k # l # m # n))

$define start (ts # cycpend) & bgack040_

/** logic equations **/
mast0.oe = 'b'1;
mast1.oe = 'b'1;
mast2.oe = 'b'1;
mast3.oe = 'b'1;
slave0.oe = 'b'1;
slave1.oe = 'b'1;
slave2.oe = 'b'1;
slave3.oe = 'b'1;

 
sequence mreg {

 	present MSI	if (start & line) & !reset		next MSA;
			if (start & long) & !reset		next MSA;
			if (start & word & addr0) & !reset next MSF;
			if (start & word & addr2) & !reset next MSG;
			if (start & byte & addr0) & !reset next MSK;
			if (start & byte & addr1) & !reset next MSL;
			if (start & byte & addr2) & !reset next MSM;
			if (start & byte & addr3) & !reset next MSN;
			if (!start) & !reset		next MSI;
			if (start & word & addr1) & !reset next MSI;
			if (start & word & addr3) & !reset next MSI;
			if reset			next MSI;

	present MSA	if (!s1) & !reset		next MSA;
			if (s1 & bus_err) & !reset	next MSZ;
			if (s1 & byteport ) & !reset	next MSC;
			if (s1 & wordport) & !reset	next MSB;
			if (s1 & longport) & !reset	next MSI;
			if (s1 & noport) & !reset	next MSI;
			if reset			next MSI;
 
	present MSB	if (!s1) & !reset		next MSB;
			if (s1 & bus_err) & !reset	next MSZ;
			if (s1 & byteport) & !reset	next MSI;
			if (s1 & wordport) & !reset	next MSI;
			if (s1 & longport) & !reset	next MSI;
			if (s1 & noport) & !reset	next MSI;
 			if reset			next MSI;


	present MSC	if (!s1) & !reset		next MSC;
			if (s1 & bus_err) & !reset	next MSZ;
			if (s1 & byteport) & !reset	next MSD;
			if (s1 & wordport) & !reset	next MSI;
			if (s1 & longport) & !reset	next MSI;
			if (s1 & noport) & !reset	next MSI;
 			if reset			next MSI;

	present MSD	if (!s1) & !reset		next MSD;
			if (s1 & bus_err) & !reset	next MSZ;
			if (s1 & byteport) & !reset	next MSE;
			if (s1 & wordport) & !reset	next MSI;
			if (s1 & longport) & !reset	next MSI;
			if (s1 & noport) & !reset	next MSI;
 			if reset			next MSI;

	present MSE	if (!s1) & !reset		next MSE;
			if (s1 & bus_err) & !reset	next MSZ;
			if (s1 & byteport) & !reset	next MSI;
			if (s1 & wordport) & !reset	next MSI;
			if (s1 & longport) & !reset	next MSI;
			if (s1 & noport) & !reset	next MSI;
 			if reset			next MSI;

	present MSF	if (!s1) & !reset		next MSF;
			if (s1 & bus_err) & !reset	next MSZ;
			if (s1 & byteport) & !reset	next MSH;
			if (s1 & wordport) & !reset	next MSI;
			if (s1 & longport) & !reset	next MSI;
			if (s1 & noport) & !reset	next MSI;
 			if reset			next MSI;

	present MSG	if (!s1) & !reset		next MSG;
			if (s1 & bus_err) & !reset	next MSZ;
			if (s1 & byteport) & !reset	next MSJ;
			if (s1 & wordport) & !reset	next MSI;
			if (s1 & longport) & !reset	next MSI;
			if (s1 & noport) & !reset	next MSI;
 			if reset			next MSI;

	present MSH	if (!s1) & !reset		next MSH;
			if (s1 & bus_err) & !reset	next MSZ;
			if (s1 & byteport) & !reset	next MSI;
			if (s1 & wordport) & !reset	next MSI;
			if (s1 & longport) & !reset	next MSI;
			if (s1 & noport) & !reset	next MSI;
 			if reset			next MSI;

	present MSJ	if (!s1) & !reset		next MSJ;
			if (s1 & bus_err) & !reset	next MSZ;
			if (s1 & byteport) & !reset	next MSI;
			if (s1 & wordport) & !reset	next MSI;
			if (s1 & longport) & !reset	next MSI;
			if (s1 & noport) & !reset	next MSI;
 			if reset			next MSI;

	present MSK	if (!s1) & !reset		next MSK;
			if (s1 & bus_err) & !reset	next MSZ;
			if (s1 & byteport) & !reset	next MSI;
			if (s1 & wordport) & !reset	next MSI;
			if (s1 & longport) & !reset	next MSI;
			if (s1 & noport) & !reset	next MSI;
 			if reset			next MSI;

	present MSL	if (!s1) & !reset		next MSL;
			if (s1 & bus_err) & !reset	next MSZ;
			if (s1 & byteport) & !reset	next MSI;
			if (s1 & wordport) & !reset	next MSI;
			if (s1 & longport) & !reset	next MSI;
			if (s1 & noport) & !reset	next MSI;
 			if reset			next MSI;

	present MSM	if (!s1) & !reset		next MSM;
			if (s1 & bus_err) & !reset	next MSZ;
			if (s1 & byteport) & !reset	next MSI;
			if (s1 & wordport) & !reset	next MSI;
			if (s1 & longport) & !reset	next MSI;
			if (s1 & noport) & !reset	next MSI;
 			if reset			next MSI;

	present MSN	if (!s1) & !reset		next MSN;
			if (s1 & bus_err) & !reset	next MSZ;
			if (s1 & byteport) & !reset	next MSI;
			if (s1 & wordport) & !reset	next MSI;
			if (s1 & longport) & !reset	next MSI;
			if (s1 & noport) & !reset	next MSI;
 			if reset			next MSI;

	present MSDC	    				next MSI;

	present MSZ					next MSI;
}

sequence	sreg {
	
	present	S3	if reset			next S3;
			if i				next S3;
			if z				next SB;
			default				next S0;

	present S0	if first_term_sample & term & !lsterm & !reset
							next S1;
			if !first_term_sample & term & !lsterm & !reset
							next S0;
			if !term & !lsterm & !reset	next S0;
			if lsterm & !reset		next S1;
			if reset			next S3;

	present S1	if bus_err & !reset		next SB; 
			if !rberr & !(f1 # f2 # f3) & !reset next S3;
			if !rberr & (f1 # f2 # f3) & !reset next S2;
			if reset			next S3;
 
	present	S2					next S3;
 
	present SB					next S3;

/** the remaining states are undefined and return as if S1 **/ 
 
	present 'b'1001 if reset           		next S3; 

	present 'b'1010	if reset           		next S3; 
  
	present 'b'1011	if reset           		next S3; 
 
	present 'b'1100	if reset           		next S3; 
 
	present 'b'1101	if reset            		next S3; 
 
	present 'b'1110	if reset        		next S3; 
 
	present 'b'1111	if reset			next S3; 
} 
/** equations **/