PARTNO	  XXXXX ;
		NAME	  U504;
		DATE	  October 25, 1988 ;
		REV	  3 ;
		DESIGNER  Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  312828 ;
		LOCATION  U504;

/************************************************************************/
/*									*/
/*  A2630	BOSS generation, E (and refresh) counter, E clock	*/
/*  		synchroniser.						*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 16R6A 				*/
/************************************************************************/
/*  Free Pins: NONE							*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Sep 25:	From U308R1, A2630 Rev 2			*/
/*	DBH Oct 25:	Fixed BOSS being dropped on CPURESET		*/
/************************************************************************/

/**  Inputs  **/

PIN 2		=  E		;	/* The 6800 E clock */
PIN 3		=  B2000	;	/* We are in a B2000 machine */
PIN 4		= !DTACK	;	/* 68000 DTACK signal */
PIN 5		=  JMODE	;	/* Special Johann reset mode */
PIN 6		= !ABG		;	/* Amiga bus grant */
PIN 7		= !AAS		;	/* Amiga address strobe */
PIN 8		= !HALT		;	/* Halt from A2000 */
PIN 9		=  MODE68K	;	/* Force us back to the 68000 */
PIN 19		= !RESET	;	/* Plain old system reset */

/**  Outputs  **/

PIN 12		= !BOSS		;	/* We are the BOSS of the bus */
PIN [13..16]	=  [A0..3]	;	/* counter bits 0..3 */
PIN 18		= !REGRESET	;	/* Global reset */

/**  Used Internally **/

PIN 17		=  ESYNC	;	/* the E clock synchroniser */


/** Declarations and Intermediate Variable Definitions **/

sync		= !ESYNC # E;

/**  Logic Equations  **/

/* BOSS is a signal used by the B2000 to hold the 68000 on the main board 
   in tristate (by using bus request). Our board uses BOSS to indicate that
   we have control of the universe.  The inverse of BOSS is used as a CPU,
   MMU and ROM control register reset.  BOSS gets asserted after we request
   the bus from the 68000 (we wait until it starts it's first memory access
   after reset) and recieve bus grant and the indication that the 68000 has
   completed the current cycle.  BOSS gets held true in a latching term until
   the next cold reset or until 68KMODE is asserted.

   We wanna be the boss, but we have to be careful.  We're never the boss
   during a cold reset, or during 68K mode.  We wait after reset for the
   bus grant from the 68000, then we assert BOSS, if we're a B2000.  We
   always assert BOSS during a non-reset if we're an A2000.  Finally, we
   hold BOSS on the B2000 until either a full reset or the 68K mode is
   activated. */

BOSS		= ABG & !AAS & !DTACK & !HALT & !RESET & B2000 & !MODE68K 
		#  !HALT & !MODE68K & BOSS
		# !RESET & !MODE68K & BOSS
		# !B2000 & !HALT & !RESET;

/* This is a special reset used to reset the configuration registers.  If
   JMODE (Johann's special mode) is active, we can reset the registers
   with the CPU.  Otherwise, the registers can only be reset with a cold
   reset asserted. */

REGRESET.D	= !JMODE & HALT & RESET
		#  JMODE & RESET;

/* ESYNC is simply a one clock delay of E. It is used by the counter to do 
   edge detection.  When a high to low transition of the E clock is detected,
   the counter is forced to a known state. This allows an absolute count to 
   be used for VMA and peripheral DTACK.  This sync-up is only required when
   the board is in a B2000, since that board will be receiving E from the 
   motherboard.  On an A2000, the E clock is absent (because the processor 
   is pulled) and thus WE create the E clock, and can create it in such a way
   as to make it automatically synced. */

ESYNC.D		= E & B2000;

/* Here's the 68xx/65xx family state counter.  The counter bits A0 .. A3 are 
   used by both the 6800 cycle logic and the DRAM refresh logic. The 6800 
   cycle logic uses the counter to generate the E clock and VMA and to sync 
   DTACK to the E clock.  The DRAM refresh logic uses the counter as the 
   first phase in a larger counter. */

!A0.D		=  A0 & sync;

!A1.D		= !A1 & !A0 
		#  A1 &  A0 
		#  A3 
		# !sync;

!A2.D		= !A2 & !A0 
		# !A2 & !A1
		#  A2 &  A1 & A0
		# !sync;

!A3.D		= !A3 & !A2 & sync
		# !A1 &  A0 & sync
		# !A3 & !A0 & sync;