PARTNO	  XXXXX ;
		NAME	  U306;
		DATE	  May 24, 1988 ;
		REV	  9 ;
		DESIGNER  Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  xxxxxxx ;
		LOCATION  U306;

/************************************************************************/
/*									*/
/*  A2630	FPU chip select, Avec generation, Extern		*/
/*		generation, and data cache control.			*/
/*									*/
/************************************************************************/
/*  Allowable Target Device Types: 20L8B 				*/
/************************************************************************/
/*  Free Pins: NONE							*/
/************************************************************************/
/*  HISTORY								*/
/*	DBH Mar  5:	New, based on U306-10 and U307-13 for A2620.	*/
/*	DBH Mar  5:	Added CPUACC output for A2000 bus control.	*/
/*	DBH Mar 10:	What, we're only caching CHIP RAM data?	 Fixed.	*/
/*	DBH Apr 18:	Added logic for split address strobe; the 	*/
/*			system PAS doesn't show CPU space cycles.	*/
/*	DBH May  3:	Added EXTERN logic here and on system		*/
/*			board.  Works like AS split, only faster.	*/
/*	DBH May  3:	Added BGACK qualifier to EXTERN.		*/
/*	DBH May  5:	Qualified mapping with A24.			*/
/*	DBH May 24:	Changed A24 to EXTSEL, input only.		*/
/************************************************************************/

/**  Inputs  **/

PIN [1..3]	= [FC2..0]	;	/* Function control from the '030 */
PIN 4		= !BGACK	;	/* Bus Grant Acknowledge */
PIN 5		= !SENSE	;	/* Is there a 68881/68882? */
PIN [6..11]	= [A21..16]	;	/* CPU Address A21-16 */
PIN [13,14]	= [A15,A14]	;	/* CPU Address A15-14 */
PIN [19,20]	= [A22,A23]	;	/* CPU Address A22-23 */
PIN 23		= A13		;	/* CPU Address A13 */
PIN 21		= EXTSEL	;	/* External memory board selected */

/**  Outputs  **/

PIN 15		= !FPUCS	;	/* Floating point unit chip select */
PIN 16		= !AVEC		;	/* Avec for a interrupt cycle */
PIN 17		= !BERR		;	/* Bus error iff !SENSE & FPUCS */
PIN 18		= CACHE	 	;	/* 68030 cache enable */
PIN 22		= !EXTERN	;	/* A CPU or daughter access */

/** Declarations and Intermediate Variable Definitions **/

field cpustate	= [FC2..0] ;			/* CPU state types */
cpuspace	= (cpustate:7) ;		    /* CPU */
userdata	= (cpustate:1) ;		    /* User data */
userprog	= (cpustate:2) ;		    /* User program */
superdata	= (cpustate:5) ;		    /* Supervisor data */
superprog	= (cpustate:6) ;		    /* Supervisor program */
normspace	= (cpustate:[1,2,5,6]) ;	    /* Normal CPU access */

field spacetype	= [A19..16] ;			/* CPU space type */
interruptack	= (spacetype:f0000) ;		    /* Interrupt acknowledge */
coppercom	= (spacetype:20000) ;		    /* Coprocessor */
breakpoint	= (spacetype:00000) ;		    /* Breakpoint acknowledge */

field copperid	= [A15..13] ;			/* Copper types */
mc68881		= (copperid:2000) ;

field cpuaddr	= [A23..13] ;			/* Normal CPU space stuff */
chipram		= (cpuaddr:[000000..1fffff]) ;    /* All Chip RAM */
busspace	= (cpuaddr:[200000..9fffff]) ;    /* Main expansion bus */
ciaspace	= (cpuaddr:[a00000..bfffff]) ;    /* VPA decode */
extraram	= (cpuaddr:[c00000..cfffff]) ;    /* Motherboard RAM */
chipregs	= (cpuaddr:[d00000..dfffff]) ;    /* Custom chip registers */
iospace		= (cpuaddr:[e80000..efffff]) ;    /* I/O expansion bus */
romspace	= (cpuaddr:[f80000..ffffff]) ;    /* All ROM */

/**  Logic Equations  **/

/* This selects the 68881 or 68882 math chip, as long as there's no DMA 
   going on.  If the chip isn't there, we want a bus error generated to 
   force an F-line emulation exception.  Add in AS as a qualifier here
   if the PAL ever turns out too slow to make FPUCS before AS. */

FPUCS		= cpuspace & coppercom & mc68881 & !BGACK;

BERR		= cpuspace & coppercom & mc68881 & !SENSE & !BGACK;
BERR.OE		= cpuspace & coppercom & mc68881 & !SENSE & !BGACK;

/* This forces all interrupts to be serviced by autovectoring.  None
   of the built-in devices supply their own vectors, and the system is
   generally incompatible with supplied vectors, so this shouldn't be
   a problem working all the time.  During DMA we don't want any AVEC
   generation, in case the DMA device is like a Boyer HD and doesn't
   drive the function codes properly.  */

AVEC		= cpuspace & interruptack & !BGACK;

/* This is the cache control signal.  We want the cache enabled when we're
   in memory, but it can't go for CHIP memory, since Agnus can also write
   to that memory.  Expansion bus memory, $C00000 memory, and ROM are prime
   targets for caching.  CHIP RAM, all chip registers, and the space we leave
   aside for I/O devices shouldn't be cached.  This isn't prefect, as it's
   certainly possible to place I/O devices in the normal expansion space, or
   RAM in the I/O space.  Note that we always want to cache program, just not
   always data.  The "wanna be cached" term doesn't fit, so here's the 
   "don't wanna be cached" terms, with inversion. */

!CACHE		= chipram & (userdata # superdata) & !EXTSEL
		# ciaspace & !EXTSEL
		# chipregs & !EXTSEL
		# iospace & !EXTSEL;

/* Here's the EXTERN logic.  The EXTERN signal is used to qualify unusual
   memory accesses.  There are two kinds, CPU space and daughterboard
   space.  CPU space is given by the function codes.  Daughterboard space
   is defined to be a processor access with EXTSEL asserted.  DMA devices 
   can't get to daughterboard space.  */

EXTERN		= cpuspace & !BGACK
		# EXTSEL & !BGACK ;