PARTNO	  XXXXX ;
		NAME	  U406 ;
		DATE	  July 21, 1988;
		REV	  4;
		DESIGNER  Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  QUICKRAM ;
		LOCATION  U406;

/******************************************************************/
/*								  */
/*  QUICKRAM 	DRAM BYTE select and page control logic		  */
/*								  */
/******************************************************************/
/*  Allowable Target Device Types: 20R4B 			  */
/******************************************************************/
/*  Free Pins: 10(I),23(I)					  */
/******************************************************************/
/*  Clock:     !CPUCLK						  */
/******************************************************************/
/*  HISTORY							  */
/*	DBH May  7:	Made from BIGRAM's U107R1, no QUICK logic */
/*			added here just yet.			  */
/*	DBH Jul 19:	Changed DELAY1 for proper RAS recovery	  */
/*	DBH Jul 20:	Removed latched PAGE output		  */
/*	DBH Jul 20:	Added INVALID logic here		  */
/*	DBH Jul 21:	Fix INVALID logic polarity		  */
/******************************************************************/

/**  Inputs  **/

PIN 2		= RW		;	/* 68030 read/write line */
PIN 3		= !WANT		;	/* DMA Bus Request */
PIN [4..5]	= [A0..1]	;	/* Low order '030 addresses */
PIN 6		= MEMSEL	;	/* This board is selected */
PIN 7		= !AS		;	/* 68030 address strobe */
PIN [8..9]	= [SIZ0..1]	;	/* 68030 sizing bits */
PIN 11		= !GRESET	;	/* Global reset signal */
PIN 14		= !REFACK	;	/* Refresh cycle acknowledge */

/**  Outputs  **/

PIN 22		= !BYTELL	;	/* Qualifies lowest byte */
PIN 21		= !BYTELH	;	/* Qualifies next byte */
PIN 16		= !BYTEHL	;	/* Qualifies next byte */
PIN 15		= !BYTEHH	;	/* Qualifies highest byte */

PIN 20		= !ASQ		;	/* Delayed AS */
PIN 19		= !DEL0		;	/* 1rst order delay */
PIN 18		= !DEL1		;	/* 2nd order delay */
PIN 17		= !VALID	;	/* PAGE cache valid */

/** Declarations and Intermediate Variable Definitions **/

/**  Logic Equations  **/

/* There are several conditions under which a particular byte is selected,
   based on the address on the bus and the size bits.  This is explained in
   the 68030 manual. */

BYTELL	= SIZ1 & SIZ0 & A0
	# !SIZ1 & !SIZ0
	# A1 & A0
	# SIZ1 & A1 ;

BYTELH	= A1 & !A0
	# !SIZ1 & !SIZ0 & !A1
	# !A1 & SIZ0 & SIZ1
	# A0 & !A1 & !SIZ0 ;
		   
BYTEHL	= !SIZ0 & !A1
	# !A1 & A0
	# SIZ1 & !A1 ;

BYTEHH	= !A1 & !A0 ;

/* The delayed address strobe is simply AS delayed via a simple clocked
   output. */

ASQ.D	= AS ;

/* Currently DEL1 is correct, and used by the RAS generator for proper
   PAGE miss TRP timing.  DEL0 is used by the refresh logic for the
   same thing.  But there's a trick.  In the refresh counter, I want
   more delay than just what DEL0 could provide being based on 
   REFACK.  So I use the DEL1 line with DEL0 in this case as a 2 bit
   counter.  This is permitted, since the RAS machine qualifies
   it's use of DEL1 with !REFACK.  Or at least, that's the theory. */

DEL0.D	= DEL1 & REFACK ;
DEL1.D	= ASQ & AS & !REFACK
	# REFACK ;

/* Here's the PAGE cache is valid signal.  What I actually create here
   are the terms under which the PAGE cache is invalid.  There are two
   specific times the PAGE may be considered invalid.  First of all, on
   a global reset, I know that whatever the PAGE latches come up with
   it's incorrect.  The other time we can go invalid is for a refresh.  
   I only _need_ to invalidate for the DRAM cycle that follows the 
   refresh, but I use this signal in the refresh logic, so I set it before 
   servicing refresh.  The end result is the same.  And I must hold off 
   any changes 'till the end of any cycle in progress.

   The rest of the logic concerns when validity can change.  I certainly
   want it to be held throughout refresh, so that's what the first
   hold term does.  The second hold term just hold VALID through any
   memory cycle.  I know that the page latch always goes valid at
   the end of a cycle.
*/

!VALID.D = GRESET				/* System reset */
	 # WANT & !AS				/* Refresh request */
	 # !VALID & REFACK			/* Hold through refresh */
	 # !VALID & AS;				/* Hold through cycle */