PARTNO	  XXXXX ;
		NAME	  U104 ;
		DATE	  July 20, 1988 ;
		REV	  2 ;
		DESIGNER  Haynie ;
		COMPANY   Commodore ;
		ASSEMBLY  QUICKRAM ;
		LOCATION  U104 ;

/******************************************************************/
/*								  */
/*  BIGRAM 	Refresh arbiter and state machine.		  */
/*								  */
/******************************************************************/
/*  Allowable Target Device Types: 16R8B 			  */
/******************************************************************/
/*  Free Pins: 8(I)						  */
/******************************************************************/
/*  HISTORY							  */
/*	DBH May  8:	New, based on BIGRAM's U104R2, no QUICK	  */
/*			added in here just yet.			  */
/*	DBH Jul 20:	Added DELAY0 into refresh logic to insure */
/*			TRP.					  */
/*	DBH Jul 20:	Added INVLD qualifier to REFACK logic	  */
/*	DBH Jul 20:	Added ECS qualifier to REFACK logic	  */
/******************************************************************/

/**  Inputs  **/

PIN 2		= !EREFREQ	;	/* Unsynchronised refresh request */
PIN 3		= !AS		;	/* 68030 address strobe */
PIN 4		= !INVLD	;	/* PAGE cache invalid */
PIN 5		= !NORAM	;	/* RAM disable jumper */
PIN 6		= !PAGE		;	/* Page match */
PIN 7		= !DELAY0	;	/* 1rst order delay */
PIN 8		= !ECS		;	/* Early Cycle Strobe */
PIN 9		= MEMSEL	;	/* Memory select input */

/**  Outputs  **/

PIN 19		= !REFACK	;	/* Refresh request acknowledge */
PIN 18		= !WANT		;	/* We want to bus to do refresh */
PIN 17		= !IRAS		;	/* Refresh RAS control */
PIN 16		= !ICAS		;	/* Refresh CAS control (REFRESH) */


/**  Used Internally **/

PIN 15	     = !IREFREQ  ;	/* Synchronised refresh request */
PIN 14	     = !StBit0	 ;	/* State bit 0 */
PIN 13	     = !StBit1	 ;	/* State bit 1 */
PIN 12	     = !StBit2	 ;	/* State bit 2 */


/** Declarations and Intermediate Variable Definitions **/

/**  Logic Equations  **/

/* This is the refresh acknowledge, gets asserted in response to a
   refresh request (WANT).  First of all, it waits for WANT to generate 
   a PAGE cache invalidation.  Then it must consider what's happening on
   the bus.  If we haven't started a cycle yet, we can run the refresh 
   cycle immediately.  If we're in a cycle, but not a cycle for this 
   memory board, than we proceed.  Otherwise, we'll just wait for one of 
   the above cases.  Once refresh is acknowledged, it is latched until 
   WANT goes away, indicating a successful refresh cycle has been run.  */

REFACK.D = (WANT &    !ECS & INVLD & !AS)
	 # (WANT & !MEMSEL & INVLD & AS)
	 # (WANT & REFACK);

/* This creates an internally synchronized version of the raw refresh request
   EREFREQ.  It's latched on refresh acknowldege. */

IREFREQ.D = EREFREQ
	  # IREFREQ & !REFACK;

/* The want signal is based on the raw refresh request and whether or not
   refresh is acknowledged. */

WANT.D =	( IREFREQ & !StBit0 & !StBit2)
	#	( REFACK & !StBit0 & !StBit1 & StBit2)
	#	( !REFACK & !StBit0 & !StBit1 & StBit2)
	#	( StBit0 & !StBit1 & !StBit2)
	#	( StBit0 & !StBit1 & StBit2)
	#	( !StBit0 & StBit1 & !StBit2)
	#	( !StBit0 & StBit1 & StBit2);

/* These become the RAS and CAS for a refresh cycle.  Note that we're doing
   a CAS before RAS cycle. */

IRAS.D = 	( !StBit0 & StBit1 & !StBit2)
	#	( !StBit0 & StBit1 & StBit2)
	#	( StBit0 & !StBit1 & !StBit2);
ICAS.D = 	( REFACK & DELAY0 & !StBit0 & !StBit1 & StBit2)
	#	( !StBit0 & StBit1 & !StBit2)
	#	( !StBit0 & StBit1 & StBit2);

/* This is the refresh state machine.  We acknowledge refresh to the
   rest of the system, but don't start an actual refresh cycle here,
   until DELAY0.  That gives us the required TRP time we need.  */

StBit2.D =	( IREFREQ & !StBit0 & !StBit2)
	#	( !REFACK & !StBit0 & !StBit1 & StBit2)
	#	( StBit0 & !StBit1 & !StBit2)
	#	( !StBit0 & StBit1 & !StBit2);
StBit1.D =	( REFACK & DELAY0 & !StBit0 & !StBit1 & StBit2)
	#	( StBit0 & !StBit1 & StBit2)
	#	( !StBit0 & StBit1 & !StBit2);
StBit0.D =	( StBit0 & !StBit1 & !StBit2)
	#	( StBit0 & !StBit1 & StBit2)
	#	( !StBit0 & StBit1 & StBit2);