PARTNO XXXXX ; NAME U103; DATE July 28, 1988; REV 8; DESIGNER Haynie ; COMPANY Commodore ; ASSEMBLY QUICKRAM ; LOCATION U103; /******************************************************************/ /* */ /* QUICKRAM RAS generation logic */ /* */ /******************************************************************/ /* Allowable Target Device Types: 20L8B */ /******************************************************************/ /* Free Pins: NONE */ /******************************************************************/ /* HISTORY */ /* DBH May 7: Made from BigRAM's U103R1, no QUICK logic */ /* in here just yet. */ /* DBH May 27: Fast logic added here. */ /* DBH Jul 20: Changed RAS logic to remove spurious RAS */ /* DBH Jul 20: Changed non-paged RAS into cases for */ /* valid and invalid page cache. */ /* DBH Jul 20: Added glitch free (me thinks) logic */ /* for invalidation. Counts on the INVALID */ /* signal being synced better than it is. */ /* DBH Jul 20: Fixed INVALID case so RAS stays for the */ /* entire cycle. */ /* DBH Jul 28: Added DELAY0 to all non page hit cycles */ /* to always make TRP, even if we don't */ /* need to. */ /* DBH Jul 28: Added GRESET to RAS terms so we don't */ /* accidently latch on powerup. */ /* DBH Jul 28: Fixed REFRAS, assigned to wrong pin. */ /******************************************************************/ /** Inputs **/ PIN 1 = !AS ; /* 68030 address strobe */ PIN 2 = INVALID ; /* Page latch invalid */ PIN 3 = RW ; /* 68030 read/write line */ PIN 4 = !PAGE ; /* Page compare output */ PIN 5 = !DELAY1 ; /* 2nd order delay */ PIN 6 = !ASQ ; /* Delayed address strobe */ PIN 7 = MEMSEL ; /* Memory select (also, A24 here) */ PIN [8..10] = [A23..21] ; /* 68030 address lines */ PIN 11 = !REFACK ; /* Refresh request acknowledge */ PIN 13 = !GRESET ; /* Global reset */ PIN 14 = !REFRAS ; /* Refresh RAS */ PIN 23 = !PCASEN ; /* Page mode CAS Enable */ /** Outputs **/ PIN 20 = !RASEN0 ; /* RAS Enable for BANK 0 */ PIN 16 = !RASEN1 ; /* RAS Enable for BANK 1 */ PIN 17 = !RASEN2 ; /* RAS Enable for BANK 2 */ PIN 18 = !RASEN3 ; /* RAS Enable for BANK 3 */ PIN 19 = !RASEN ; /* Any RAS Enabled */ PIN 15 = !PCAS ; /* Page mode CAS output */ PIN 21 = !STERM ; /* Synchronous cycle terminate */ PIN 22 = !DSACKEN ; /* DSACK out enabled */ /** Declarations and Intermediate Variable Definitions **/ field addr = [A23..21] ; bank0 = addr : [000000..1fffff] ; bank1 = addr : [200000..3fffff] ; bank2 = addr : [400000..5fffff] ; bank3 = addr : [600000..7fffff] ; paw = AS & !ASQ ; stdras = !REFACK & MEMSEL & !GRESET; /** Logic Equations **/ /* This is the basic RAS enable. There are three possible cases in which RAS gets asserted here, two holding terms, and a refresh term which is driven by another PAL. I only assert RAS here if I'm not in a refresh acknowledge cycle AND my memory's selected. This is the "stdras" term. The first complete term is for the case when the page cache is INVALID. This looks just like a slow memory cycle -- I assert RAS during AS. All the other local terms apply only for a valid page cache. The second RAS term will assert RAS for a valid PAGE hit. This term is only asserted during "paw", the Page Arbitration Window. This allows the PAGE input to fluctuate at all other times, making the page match logic simpler and much faster (no external latching required). The next term applies for a PAGE miss. Here I wait out DELAY1 to assure TRP before asserting RAS. Since DELAY1 happens later in the same cycle than "paw", I'm safe to count on the PAGE line being valid at this point. The next two terms are holding terms for PAGE cycles. The first holding term keeps RAS asserted as long as we're valid and PAGE hits occur. The second holding term makes sure that RAS doesn't change between cycles, since PAGE can possibly glitch between cycles, and a corresponding glitch on RAS would be a disaster. The final term is the refresh term, from the refresh state machine. This term is responsible for asserting RAS after a refresh arbitration. The refresh state machine assures TRP and asserts the refresh CAS before asserting REFRAS. Everywhere I assume that only RESET or REFRESH can cause a cache invalidation, and that we can't go INVALID during a cycle. This assumption is guaranteed by the RESET operation automatically, and by the refresh state machine if it's doing it's job correctly. */ RASEN = stdras & INVALID & AS /* Assert 1 */ # stdras & !INVALID & paw & PAGE /* Assert 2 */ # stdras & !INVALID & AS & !PAGE & DELAY1 /* Assert 3 */ # RASEN & !INVALID & PAGE & !GRESET /* Hold 1 */ # RASEN & !INVALID & !AS & !GRESET /* Hold 2 */ # REFRAS ; /* Refresh */ /* Bank-related RAS enables are the same as the above RAS enable, only the bank term is added in for access cycles. */ RASEN0 = stdras & INVALID & bank0 & AS # stdras & !INVALID & bank0 & paw & PAGE # stdras & !INVALID & bank0 & AS & !PAGE & DELAY1 # RASEN0 & !INVALID & PAGE & !GRESET # RASEN0 & !INVALID & !AS & !GRESET # REFRAS ; RASEN1 = stdras & INVALID & bank1 & AS # stdras & !INVALID & bank1 & paw & PAGE # stdras & !INVALID & bank1 & AS & !PAGE & DELAY1 # RASEN1 & !INVALID & PAGE & !GRESET # RASEN1 & !INVALID & !AS & !GRESET # REFRAS ; RASEN2 = stdras & INVALID & bank2 & AS # stdras & !INVALID & bank2 & paw & PAGE # stdras & !INVALID & bank2 & AS & !PAGE & DELAY1 # RASEN2 & !INVALID & PAGE & !GRESET # RASEN2 & !INVALID & !AS & !GRESET # REFRAS ; RASEN3 = stdras & INVALID & bank3 & AS # stdras & !INVALID & bank3 & paw & PAGE # stdras & !INVALID & bank3 & AS & !PAGE & DELAY1 # RASEN3 & !INVALID & PAGE & !GRESET # RASEN3 & !INVALID & !AS & !GRESET # REFRAS ; /* This generates DSACK for the DRAM. This simple term just checks that we're in a cycle, but not a refresh cycle. */ DSACKEN = !REFACK & MEMSEL & AS; /* This generates the CAS used during page mode operation. */ PCAS = AS & MEMSEL & PAGE & !INVALID & !GRESET;